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Name: Roll No: ..ABES Institute of Technology

(ECS-301 DIGITAL LOGIC DESIGN)2

NDYEAR (11CS & 11IT)

MODEL TEST PAPER # 2

Time: 3.00 hrs. Max. Marks: 100

Note: The question paper contains three Sections. All Sections are compulsory.

PART A

(2 10= 20)

Attempt all questions. Answers are expected to be in 50-75 words.

All questions are of same marks.

1. Perform the given conversions : (i) (62.7)8 = ( )16 = ( )2 (ii) (BC64)16 = ( )10 = ( )2(iii) (111011)

2= ( )

5

2. Represent the unsigned decimal numbers 965 and 672 in BCD and find their sum.3. Minimize the function F(A,B,C,D) = m(0,1,2,9,11,15) + d(8,10,14) using a K Map and

realize it using Basic gates.

4. Express the Boolean function F = AB + AC +AD in standard SOP form.5. Implement the function F = ABC + ABCD + ABCD + AB + C using a PLA.6. A memory chip has a capacity of 8K x 16. How many words are being stored and what is

the size of each word. How many pins would be there in the address bus.

7. Design a 2 bit magnitude comparator using logic gates.8. Show the timing waveform of a 3 bit up counter.9. Generate the even parity hamming code for the 6 bit data 110011.10.Discuss in brief how the carry is generated in a carry lookahead adder.

PART B

(3 10 = 30)

Attempt any three questions out of five. All questions are of equal marks. Answer should

be in 100 to 200 words.

11. (a) Write down the truth table of Half-subtractor and full subtractor. Implement a fullsubtractor using two half subtractors.

(b) Design a Mod 10 asynchronous counter.

12.Plot K map of the given functions. Determine Hazard free implementation in both casesusing NAND and NOR gates. Assume that the gates have a maximum fan-in of three.

i. F(A,B,C,D) = m(0,2,4,5,6,8,9,11,12,14,15)ii. G(A,B,C,D) = m(3,4,5,6,11,12,13,14,15)

13.Design a sequence generator for the sequence 1101011.14.Explain different type of memories in detail. Differentiate between SRAM and DRAM

with the help of neat diagrams.

15.Convert (i) SR FF to JK FF (ii) T FF to D FF showing all the relevant steps.PART C

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(5 10= 50)

Attempt all the five questions. All questions are of equal marks. Answer should be in 300 to

500 words.

16. (a) Design a sequence detector to detect the sequence 10101(b) Design a sequence generator for the sequence 1101011

OR

Implement the following using (i) PAL and (ii) PLA F1 = m(0,1,3,5) F2 =m(2,3,5,6) F3 = m(0,1,6)17. (a) Draw and explain the memory cycle timing waveform for the memory write and read

operations. Assume a CPU clock of 50 MHz and memory cycle time of 50ns.

(b) Design a synchronous recycling MOD 8 binary down counter using D Flip-Flops.

ORImplement the following function using 16 x 1 MUX and 8 x 1 Mux : F(A,B,C,D) = m

(0,1,3,4,7,8,9,11,14,15)

18. (a) Design an Excess-3 to BCD code converter(b) Design modulo 3 counter using SR Flip Flops

OR

Explain the Hazards in combinational and sequential circuits. Also explain the remedyfor eliminating a Hazard. What are critical races and Non-critical races.

19. (a) Explain the design and working of a Carry Look Ahead Adder(b) Explain the Hamming Error detection/correction code. Generate the Odd parity

Hamming code for the 5 bit data 11010

ORImplement the function F(A,B,C) = A'B'C + A'BC' + AB'C' + ABC using (a) 4:1 MUX

and (b) 3:8 Decoder20.What is an ASM chart. Design the process of designing with Multiplexers.

ORSuppose the shown circuit is operating in fundamental mode. Analyse the circuit by

forming the (a) Flow Table (b) Transition Flow Diagram and (c) Transition Flow Table