Elec 2041 Microprocessors and Interfacing Lecture Introduction
Mp1-Introduction to Microprocessors
description
Transcript of Mp1-Introduction to Microprocessors
1
COM 353 MicroprocessorsCOM 353 Microprocessors
Prof. Dr. Halûk Gümüş[email protected]
[email protected] http://www.gumuskaya.com
Computer Engineering Department
Saturday, October 06, 2012 2
Computer Organization and Introduction to Microprocessors
Computer Organization and Introduction to Microprocessors
Prof. Dr. Halûk Gümüş[email protected]
http://www.gumuskaya.com
Saturday, October 06, 2012
3
1. Introduction2. Views of Computer Systems3. Processor Based System4. Processor5. Memory6. Input/Output7. Interconnection: The Glue8. Historical Perspective
Lecture Outline
4
Outline
• Introduction Basic Terminology and
NotationViews of Computer Systems• User’s view• Programmer’s view
Advantages of high-level languages
Why program in assembly language?
• Architect’s view• Implementer’s view
• Processor Execution cycle Pipelining RISC and CISC
• Memory Basic memory operations Design issues
• Input/Output• Interconnection: The glue• Historical Perspective
5
Introduction
• Some basic terms Computer organization Computer architecture Computer design Computer programming
• Various views of computer systems User’s view Programmer’s view Architect’s view Implementer’s view
6
1. Introduction
2. Views of Computer Systems3. Processor Based System4. Processor5. Memory6. Input/Output7. Interconnection: The Glue8. Historical Perspective
7
From Personal Computer to Mobile Devices
8
Personal Computer: Components
control unit
RAM
registers flags ALU cache
central processing unit
address dataROM
address data
memory
tape
hard disk
floppy
CD-ROM
mouse
keyboard
monitor
modem
storage I/O
buses
9
A User’s View of Computer Systems
10
A Programmer’s View
• Depends on the type and level of language used• A hierarchy of languages
Machine language Assembly language increasing level High-level language of abstraction Application programs
• Machine-independent High-level languages/application programs
• Machine-specific Machine and assembly languages
11
A Programmer’s View (cont’d)
12
A Programmer’s View (cont’d)
• Machine language Native to a processor Consists of alphabet 1s and 0s1111 1111 0000 0110 0000 1010 0000 0000B
• Assembly language Slightly higher-level language Human-readable One-to-one correspondence with most machine
language instructionsinc count
13
A Programmer’s View (cont’d)
• Readability of assembly language instructions is much better than the machine language instructions
» Machine language instructions are a sequence of 1s and 0s
Assembly Language Machine Language(in Hex)
inc result FF060A00mov class_size,45 C7060C002D00and mask,128 80260E0080add marks,10 83060F000A
14
A Programmer’s View (cont’d)
• Assemblers translate between assembly and machine languages TASM MASM NASM
• Compiler translates from a high-level language to machine language Directly Indirectly via assembly language
15
A Programmer’s View (cont’d)
16
A Programmer’s View (cont’d)
• High-level languages versus low-level languagesIn C:result =
count1 + count2 + count3 + count4In Pentium assembly language:
mov AX,count1add AX,count2add AX,count3add AX,count4mov result,AX
17
A Programmer’s View (cont’d)
• Some simple high-level language instructions can be expressed by a single assembly instruction
Assembly Language C
inc result result++;mov size,45 size = 45;and mask1,128 mask1 &= 128;add marks,10 marks += 10;
18
A Programmer’s View (cont’d)
• Most high-level language instructions need more than one assembly instruction
C Assembly Language
size = value; mov AX,valuemov size,AX
sum += x + y + z; mov AX,sumadd AX,xadd AX,yadd AX,zmov sum,AX
19
A Programmer’s View (cont’d)
• Instruction Set Architecture (ISA) An important level of abstraction Specifies how a processor functions
» Defines a logical processor
• Various physical implementations are possible All logically look the same Different implementations may differ in
» Performance» Price
• Two popular examples of ISA specifications SPARC and JVM
20
Advantages of High-Level Languages
• Program development is faster» High-level instructions
– Fewer instructions to code
• Program maintenance is easier» For the same reasons as above
• Programs are portable» Contain few machine-dependent details
– Can be used with little or no modifications on different types of machines
» Compiler translates to the target machine language» Assembly language programs are not portable
21
Why Program in Assembly Language?
• Two main reasons: Efficiency
» Space-efficiency» Time-efficiency
Accessibility to system hardware• Space-efficiency
Assembly code tends to be compact• Time-efficiency
Assembly language programs tend to run faster» Only a well-written assembly language program runs faster
– Easy to write an assembly program that runs slower than its high-level language equivalent
22
Architect’s View
• Looks at the design aspect from a high level Much like a building architect Does not focus on low level details Uses higher-level building blocks
» Ex: Arithmetic and logical unit (ALU)
• Consists of three main components Processor Memory I/O devices
• Glued together by an interconnect
23
Architect’s View (cont’d)
24Page 24
Architect’s View (cont’d)
25
Implementer’s View
• Implements the designs generated by architects Uses digital logic gates and other hardware circuits
• Example Processor consists of
» Control unit» Datapath
– ALU– Registers
• Implementers are concerned with design of these components
26
Implementer’s View (cont’d)
27
Implementer’s View (cont’d)
28
Implementer’s View (cont’d)
29
1. Introduction2. Views of Computer Systems
3. Processor Based System4. Processor5. Memory6. Input/Output7. Interconnection: The Glue8. Historical Perspective
30
A Processor Based System
31
Microprocessor Based System: Collection of Addressable Registers
We can view the entire system –microprocessor, ROM, RWM, and I/O ports– as a collection of addressable registers.
• Those registers reside within the microprocessor are internal registers,
• and those exist in the ROM, RWM (RAM), and I/O ports are external registers.
32
Microprocessor Busses
Address Bus – input bus to memory device specifying location of data to read/write
Data Bus – input/output bus to memory device containing data value being read or written.
Control Bus – control signals of a processor for memory and I/O devices
33
Address, Data and Control Buses
34
1. Introduction2. Views of Computer Systems3. Processor Based System
4. Processor5. Memory6. Input/Output7. Interconnection: The Glue8. Historical Perspective
35
Processor
• Execution cycle– Fetch– Decode– Execute
• von Neumann architecture» Stored program model
– No distinction between data and instructions– Instructions are executed sequentially
36
Processor Integration Early computers had many separate chips for the different
portions of a computer system
37
Microprocessors First microprocessors placed control, registers, and arithmetic
logic unit (ALU) in one integrated circuit (one chip).
38
Modern Processors Modern microprocessors (general purpose Processors) also integrate
memory onchip for faster access. External memory and I/O components are still required. Memory integrated on the microprocessor is called cache memory.
39
Microcontrollers Microcontrollers integrate all of the components (control, memory,
I/O) of a computer system into one integrated circuit. Microcontrollers are intended to be single chip solutions for
systems requiring low to moderate processing power.
40
Pipelining: Overlapping Processor Operations
• Pipelining Overlapped execution Increases throughput
41
Pipelining (cont’d)
• Another way of looking at pipelined execution
42
RISC and CISC Processors
• RISC and CISC designs Reduced Instruction Set Computer
» Uses simple instructions» Operands are assumed to be in processor registers
– Not in memory– Simplifies design
Example: Fixed instruction size Complex Instruction Set Computer
» Uses complex instructions» Operands can be in registers or memory
– Instruction size varies» Typically uses a microprogram
43
CISC and RISC Implementations
44
Microprogramming
• Variations of the ISA-level can be implemented by changing the microprogram
45
4
1. Introduction2. Views of Computer Systems3. Processor Based System4. Processor
5. Memory6. Input/Output7. Interconnection: The Glue8. Historical Perspective
46
Memory
• Ordered sequence of bytes The sequence number is called the memory address Byte addressable memory
» Each byte has a unique address» Almost all processors support this
• Memory address space Determined by the address bus width Pentium has a 32-bit address bus
» address space = 4GB (232) Itanium with 64-bit address bus supports
» 264 bytes of address space
47
Memory (cont’d)
48
Memory (cont’d)
• Memory unit Address Data Control signals
» Read» Write
49
Memory (cont’d)
• Read cycle1. Place address on the address bus2. Assert memory read control signal3. Wait for the memory to retrieve the data
» Introduce wait states if using a slow memory4. Read the data from the data bus5. Drop the memory read signal
• In Pentium, a simple read takes three clocks cycles» Clock 1: steps 1 and 2» Clock 2: step 3» Clock 3 : steps 4 and 5
50
Memory (cont’d)
• Write cycle1. Place address on the address bus2. Place data on the data bus3. Assert memory write signal4. Wait for the memory to retrieve the data
» Introduce wait states if necessary5. Drop the memory write signal
• In Pentium, a simple write also takes three clocks» Clock 1: steps 1 and 3» Clock 2: step 2» Clock 3 : steps 4 and 5
51
Byte Ordering
52
Byte Ordering (cont’d)
• Multibyte data address pointer is independent of the endianness 100 in our example
• Little-endian Used by Pentium
• Big-endian Default in MIPS and PowerPC
• On modern processors Configurable
53
Design Issues
• Slower memoriesProblem: Speed gap between processor and memorySolution: Cache memory
– Use small amount of fast memory– Make the slow memory appear faster– Works due to “reference locality”
• Size limitations Limited amount of physical memory
» Overlay technique– Programmer managed
Virtual memory» Automates overlay management» Some additional benefits
54
Design Issues (cont’d)
55
Design Issues (cont’d)
56
1. Introduction2. Views of Computer Systems3. Processor Based System4. Processor5. Memory
6. Input/Output7. Interconnection: The Glue8. Historical Perspective
57
Input/Output
• I/O devices are interfaced via an I/O controller Takes care of low-level operations details
• Several ways of mapping I/O Memory-mapped I/O
» Reading and writing similar to memory read/write » Uses same memory read and write signals» Most processors use this I/O mapping
Isolated I/O» Separate I/O address space» Separate I/O read and write signals are needed» Pentium supports isolated I/O
– Also supports memory-mapped I/O
58
Input/Output (cont’d)
59
Input/Output (cont’d)
• Several ways of transferring data Programmed I/O
» Program uses a busy-wait loop– Anticipated transfer
Direct memory access (DMA)» Special controller (DMA controller) handles data transfers» Typically used for bulk data transfer
Interrupt-driven I/O» Interrupts are used to initiate and/or terminate data transfers
– Powerful technique– Handles unanticipated transfers
60
1. Introduction2. Views of Computer Systems3. Processor Based System4. Processor5. Memory6. Input/Output
7. Interconnection: The Glue8. Historical Perspective
61
Interconnection
• System components are interconnected by buses Bus: a bunch of parallel wires
• Uses several buses at various levels On-chip buses
» Buses to interconnect ALU and registers– A, B, and C buses in our example
» Data and address buses to connect on-chip caches
Internal buses» PCI, AGP, PCMCIA
External buses» Serial, parallel, USB, IEEE 1394 (FireWire)
62
Interconnection (cont’d)
• Bus is a shared resource Bus transactions
» Sequence of actions to complete a well-defined activity» Involves a master and a slave
– Memory read, memory write, I/O read, I/O write Bus operations
» A bus transaction may perform one or more bus operations– Pentium burst read
Transfers four memory wordsBus transaction consists of four memory read
operations Bus arbitration
63
1. Introduction2. Views of Computer Systems3. Processor Based System4. Processor5. Memory6. Input/Output7. Interconnection: The Glue
8. Historical Perspective
64
Historical Perspective
• The early generations Difference engine of Charles Babbage
• Vacuum tube generation Around the 1940s and 1950s
• Transistor generation Around the 1950s and 1960s
• IC generation Around the 1960s and 1970s
• VLSI generation Since the mid-1970s
65
Intel CPU Family40048008
1971-1972 4 ve 8bit
MikrodenetleyicilerMikroişlemciler
80808085
1974-768-bit
80868088
1978-197916-bit
80286198216-bit
80386DX80386SX
1985-198832-bit
80486DX198932-bit
8018680188
198216-bit
80386198532-bit
80488051
19768-bit
8025180151
8-bit8096
8019616-bit
Pentium Mikroişlemcileri(32-bit iç mimari, 64-bit veri yolu)
Pentium (1993) Pentium Pro (1995) Pentium MMX (1997) Pentium II (1997) Pentium III (1999) Pentium IV (2001)
66
Intel CPU FamilyProcessor Year
Register/ Data Bus Width
Address Space Önemli Özellikler
4004 1971 4/4 640 byte İlk mikroişlemci, 2300 transistör, 10 mikron
8008 1972 8/8 16K İlk 8-bit işlemci, 108 Khz
8080 1974 8/8 64K İlk genel amaçlı CPU, 6 mikron, 6000 transistör
8085 1976 8/8 64K Gelişmiş 8080, 6200 transistör
8086 1978 16/16 1M İlk 16-bit CPU, 5 – 10MHz, 29000 transistör, 3 mikron
8088 1979 16/8 1M 1981’de üretilen IBM PC�deki ilk işlemci, 8-bit veri yollu 8086
80186 1982 16/16 1M 8086 + I/O
80188 1982 16/8 1M 8088 + I/O
80286 1982 16/16 16M/1G* 134000 transistör, 1.5 mikron, IBM PC/AT’nin ilk işlemcisi
80386DX 1985 32/32 4G/64T* Intel’in ilk 32-bit işlemcisi, 275000 transistör, 1 mikron
80386SX 1988 32/16 4G/64T* 80286 yoluna sahip 80386
80486DX 1989 32/32 4G/64T* 80386 + FPU + cache, 1.2 milyon transistör, 0.8 mikron
Pentium 1993 32/64 4G/64T* 3.1 milyon transistör, 0.8 mikron, 60 – 200 MHz, superscalar mimari
Pentium Pro 1995 36/64 64G/64T* 5.5 milyon transistör, 0.32 mikron, tümdevre üzeri L2 cache, P6 mimarisi: çoklu dallanma tahmini, veri akışı analizi ve tahmini yürütme
Pentium MMX 1997 36/64 4G/64T* 4.5 milyon transistör, multi-medya ekleri
Pentium II 1997 36/64 64G/64T* 7.5 milyon transistör, 0.25 mikron, 300 – 450 MHz, MMX + Pro teknolojisi
Pentium III 1999 36/64 64G/64T* 9.5 milyon transistör, 0.18 mikron, 450– 500 MHz, 3D grafikler ve daha fazla multi-medya desteği
Pentium IV 2001 36/64 … …
67
80x86 Evolution: First Microprocessors
68
8085, 8086, and 80286
69
80386 and 80486
70
Pentium I
71
Pentium Pro
72
Pentium II
73
Pentium III
74
Pentium IV
75
AcknowledgementThe slides have been based in-part upon original slides of a numberof books including: Fundamentals of Computer Organization and Design, S. P.
Dandamudi, Springer, 1060 pages, 2003. Mikroişlemciler ve Bilgisayarlar, 6. Basım, H. Gümüşkaya, ALFA,
2011.