4.1 Basic Physics and Band Diagrams for MOS Capacitors

Fig.4.1 (a) The schematic of a two-terminal MIS structure. (b) Band diagram of a two-terminal MIS structure at zero gate voltage, showing accumulation of holes near the surface. VFB is the flatband voltage, Xm is the metal work function, Xi is the electron affinity of the insulator, Xs is the electron affinity of the semiconductor, and Eg is the band gap of the semiconductor.y

Two-terminal metal-insulator-semiconductor (MIS) structure: characteristic crucial to understand the operation of MOSFETs. Assumptions: -Ideal MIS structure with no charges in the insulator layer and no surface states at the semiconductor-insulator interface.

y

y

y

-The insulator layer has infinite resistivity, thus there is no current across the insulator when a bias voltage is applied => Fermi level constant across the device. Some definitions: -Work function: energy required to remove an electron from the Fermi level to the vacuum level (free space). -Electron affinity: energy required to remove an electron from the conduction band to the vacuum level. At zero bias voltage, the band bending in the semiconductor layer is determined by the work function difference between the metal and the semiconductor, and it can be compensated by applying a voltage VFB to the gate

where VFB is called the flat-band voltage, Xm is the metal work function, and Xs is the semiconductor electron affinity.y

Note: this equation for VFB is applicable for an ideal MIS structure; however, if there are charges in the insulator or at the insulator-semiconductor interface, then the gate voltage required to obtain flatband condition would change.

Fig.4.2 The band diagram of the two-terminal MIS structure under the flatband condition. Vg is the applied gate voltage.

EXAMPLE 4.1: A two-terminal Si MIS structure has a substrate doping of Calculate the flatband voltage VFB of the structure if it employs (a) Al gate (Xm =

(p-type).

-poly gate. Assume that there is no charge in the oxide, Xs(Si) = 4.05 eV, and Eg(Si) = 1.12 eV. SOLUTION: Ei EF = kT ln(NA/ni) = 0.026 ln[1016/(1.5 1010)] = 0.35 eV Therefore, Si work function s = Xs + (Eg/2) + (Ei EF) = 4.05 + 0.56 + 0.35 = 4.96 eV (a) For Al gate, VFB = 4.1 4.96 = 0.86 V Note: all these numbers can be equivalently represented either in volts or in electron-volts, depending on whether potential or energy is represented. (b) -poly gate, hence, Xm = Xs = 4.05 eV

It is assumed here that the Fermi level of the n+-poly gate is coincident with the conduction band. Therefore, VFB = 4.05 4.96 = 0.91 V

y

y

y

y

y

y

y

y

In Fig.4.1(b), note that Ev has come closer to EF near the semiconductor-insulator interface => hole concentration is greater near the interface than that in the bulk => this is referred to as the accumulation regime. In Fig.4.2, note that after the application of a positive VFB to the gate, the bands in the semiconductor become flat => uniform concentration of holes throughout the semiconductor. If the gate voltage is further increased, the holes near the insulator-semiconductor interface are pushed back deep into the bulk, leaving behind ionized acceptors near the surface and the bands bend downwards => formation of depletion region near the surface starts => referred to as the depletion regime [Fig.4.3(a)]. For even larger positive gate voltage, the band bending near the surface becomes so large that EF becomes closer to EC than to EV => the surface behaves like an n-type material => referred to as the inversion regime [Fig.4.3(b)]. Note: the increase in the band bending leads to an exponential increase in the electron concentration near the surface, e.g., an increase in the band bending by the amount of the thermal voltage VTH (= kT/q 26 mV at room temperature), increases the electron concentration by Thus, a large change in the electron concentration near the surface can be accommodated by a small change in the surface potential Vs, and since the induced charge is proportional to the gate voltage Vg, hence, the derivative dVs/dVg becomes small in the inversion regime, whereas this derivative has a large value in the depletion regime. When the difference between EF and Ei at the interface becomes equal and opposite of the bulk potential [ =(Ei EF)bulk = VTHln(NA/ni), where NA is the substrate doping concentration and ni is the intrinsic carrier concentration], i.e., it is referred to as the onset of strong inversion. The surface potential Vs is defined as (Ei,bulk Ei,interface)/q.

y

y

Operating regions: o VS < 0 => accumulation o > Vs > 0 => depletion o => weak inversion o => strong inversion. It is assumed that beyond strong inversion, the value of Vs does not change any more and it becomes pegged at . An alternate definition has been proposed by Tsividis, which states that = |dVs/dVg| is quite large in the weak inversion regime, whereas it becomes relatively small in the strong inversion region.

y

Fig.4.3 The band diagram of a two-terminal MIS structure at (a) depletion and (b) inversion.y y y y

Thus, he defines Vs = as the onset of moderate inversion, and strong inversion actually takes place when Vs is greater than by several (3-5) VTH. In today's context, the moderate inversion region (which can extend by 0.5 V or more) is extremely important for low power device applications in analog circuits. However, for the time being, we would stick to the standard definition of strong inversion, and would discuss about moderate inversion later. The surface electron and hole concentrations are given by

where pp0 = NA, and np0 = substrate respectively.

are the equilibrium hole and electron concentrations in the

y

Note: at the onset of strong inversion Vs = , and also, that nsps = => consequence of zero current in the semiconductor (perpendicular to the semiconductor-insulator interface) => corresponds to constant (as a function of distance) EF in the semiconductor.

4.2 Surface Chargey

The potential distribution in the semiconductor is described by the Poisson equation where the space charge density and p(x) expressed respectively as with n(x)

where V(x) (Ei,bulk Ei(x))/q.y y

Note: deep into the bulk, from charge neutrality condition, NA = pp0 np0. Thus,

y

Using the definition of the electric field F = dV(x)/dx, the above equation can be rewritten as

y

Integrating this equation with respect to V, one gets

y

Thus,

y

Introducing the Debye length

the equation for F become

where

EXAMPLE 4.3: Draw the low- and high-frequency C-V characteristics, clearly showing all the relevant points, including the flatband capacitance, for a two-terminal MIS structure having 30 nm thick oxide and substrate doping of 1015 cm 3 (p-type). Assume VFB = 1 V.

SOLUTION: The oxide capacitance per unit area

The bulk potential = (kT/q) ln(NA/ni) = 0.026 ln[1015/(1.5 1010)] = 0.29 V The threshold voltage

The maximum width of the depletion region

The semiconductor capacitance per unit area at threshold

Therefore, the total capacitance per unit area at threshold

The Debye length

The flatband capacitance per unit area

y y y

The capacitance Csc becomes dominant in the strong inversion region, when the surface electron concentration is appreciable, since the band bending is largest at the surface. Note: the electrons, which create the inversion region near the surface, are actually generated in the bulk due to thermal EHP generation. Due to the electric field near the surface (recall that electric field points uphill in the band diagram), the electron and hole of the generated EHP are separated; the electron moves towards the surface and the hole moves towards the bulk => thus the rate of electron build-up near the surface proceeds at a rate limited by the rate of thermal EHP generation.

Fig.4.9 (a) The exact high-frequency equivalent circuit of a two-terminal MIS structure, and (b) its simplified equivalent.y

Two new components in the equivalent circuit: o where T is the thickness of the semiconductor layer, and is the hole mobility] is the resistance of the quasi-neutral p-region, and o Rgen (= dVs/dIgen) is a differential resistance, which is a characteristic of the EHP generation process. Igen is the generation current, given by generation time constant. Thus, for gate voltages smaller than the threshold voltage VT, is an effective

y y

y

In the small-signal equivalent circuit, the parameters Ceq and Req are given by

where

andy

Note: both Ceq and Req are frequency dependent: in the limiting case of + Cdep, and in the other limiting case of

Fig.4.10 The C-V characteristics for a two-terminal MIS structure at different frequencies.

4.4.1 Extraction of Parameters from the C-V Characteristic

Fig.4.11 Parameter extraction from the C-V characteristic for a two-terminal MIS structure. The parallel shift in the characteristic after the bias-temperature stress test (described later) is also shown.y y

The maximum measured capacitance Cmax in the accumulation region gives the dielectric thickness The minimum measured capacitance Cmin at high frequency gives the doping concentration (assumed uniform) in the substrate. Steps: o First, determine the depletion capacitance Cdep in the strong inversion region from 1/Cdep = 1/Cmin 1/Cmax.o o

Then, obtain the depletion region thickness from And, finally, calculate the doping concentration from the following two equations:

y

These two equations need to be solved by iteration: first choose a suitable value for (say, 0.3 V), obtain NA, recalculate , obtain another fine tuned value of NA, and repeat the process until the desired accuracy is achieved. It also gives the information about the flatband voltage VFB. Steps: o The device capacitance CFB under flatband condition can be given by CFB =o

CiCs0/(Ci + Cs0) =o o

Thus, From a knowledge of di and NA, CFB/Cmax can be obtained, and the intercept can be found on the C-V curve to yield VFB.

4.5 Non-ideality in an MIS Structure: Oxide Chargesy y

In most of the commercially available MOS capacitors and MOSFETs, silicon (Si) is used as the semiconductor and silicon dioxide (SiO2) is used as the insulator. Si being a crystalline material and SiO2 being an amorphous material, there is a sudden discontinuity in the lattice structure at the Si-SiO2 interface.

Fig.4.12 Different types of charges in the Si-SiO2 interface and in the SiO2 layer.

y

y

This interface has attracted considerable interest over the last few decades, and significant studies have been made on this structure, however, a detailed understanding of many of its features is still lacking. The interface and the oxide contains various types of charges, which can be broadly categorized into the following:o

Charges due to fast surface states (or interface trapped charges) the interface. within SiO2.

located at

Charges due to mobile impurity ions o Charges due to traps ionized by radiationo o

located in SiO2.

Fixed surface state charges

located at the interface.

4.5.1 Fast Surface States

y y

y

y y

These are also referred to as Tamm and Shockley states, after their inventors. These are created at the interface due to the sudden termination of the crystal periodicity, since all the bonds of the atoms at the surface are not fulfilled these unfulfilled bonds are referred to as the dangling bonds. Obviously, the density of these states is a function of the crystal orientation (since (100) planes have lower atom density than (111) planes, MOSFETs are universally fabricated on (100) oriented Si). Roughly, one fast surface state is assigned for every surface atom, resulting in a density Proper cleaving of the surface and consequent heat treatment with H2 drastically reduces the density of these states to or so, since H2 compensates some of these dangling bond by the formation of SiH. These states behave acceptor-like or donor-like, depending on the position of the Fermi level at the surface and the amount of band bending, and these are referred to as fast states, since they capture and release the carriers at a fast rate. When the surface potential changes, the charges in the surface states change as well, and leads to a shift in VT and a change in the C-V characteristics.

y

y

Fig.4.13 The experimental C-V characteristics showing the difference between them due to the presence of fast surface states.y y

There is a shift of the C-V curve towards the left due to the fast surface states, which changes the flatband voltage. In the equivalent circuit of an MIS structure, the fast surface states can be represented by an additional series combination of an equivalent capacitance Css of the surface states, and an additional resistance Rss, with the time constant RssCss representing the time response of the surface states.

Fig.4.14 The overall high-frequency equivalent circuit for a two-terminal MIS structure showing the additional components Css-Rss to account for the effects of fast surface states.y

Measurements of frequency-dependent MIS capacitance and conductance give information about the density of the surface states.

4.5.2 Ionic Contaminationy y

A major difficulty with early MOS devices was the instability of the threshold voltage VT, i.e., it used to vary with bias under elevated temperatures. This happens due to the rearrangement of the mobile ions within the oxide, which are introduced into the oxide from the furnace walls during oxidation.

Fig.4.15 Shift in the C-V characteristic after the bias-temperature stress test due to ionic contamination in the oxide, and its partial recovery after annealing with gate-substrate shorted.

y

The initial C-V characteristic is marked by (1), while those observed after 30 minutes at 127 C with VG = +10 V applied is marked by (2), and after heating the device for 30 minutes at the same temperature with the gate shorted to the substrate yields characteristic marked by (3)- this experimental procedure is known as the bias-temperaturestress test.

Fig.4.16 Charge distribution during the various stages of the bias-temperature stress test and post annealing.y

y y

Initially, all the positive ionic charges are located at the metal-SiO2 interface, exerting no influence on Si; after positive gate bias at high temperature, all these ionic charges cluster near the Si-SiO2 interface and induce all the image charges in Si; finally after recovery, the ions create an arbitrary distribution (x) within the oxide, inducing image charges in both the gate and the semiconductor. For any arbitrary distribution of the oxide charges (x), the shift in the flatband voltage can be given by

where di is the oxide thickness.y

The menace created by mobile ions is reduced to a large extent in today's technology due to the improvements in the fabrication process.

EXAMPLE 4.4: In a two-terminal MIS structure having 40 nm thick oxide, the shift in the flatband voltage after a bias-temperature stress test was found to be 10 mV. Determine the mobile ionic contamination per unit area in the oxide in numbers per unit area. SOLUTION: The oxide capacitance per unit area

The shift in the flatband voltage due to the mobile ionic contamination after bias-temperature stress test is given by oxide Thus, the mobile ionic contamination per unit area in the

4.5.3 Radiation-Induced Space Chargey

y y y

y

y

A positive space charge is seen to build up in SiO2 films when it is irradiated by ionizing radiation of various kinds, e.g., X-ray, gamma ray, low- and high-energy electron irradiation, etc. (potential danger during ion implantation). The physical origin of this charge is completely different from the ionic contamination. Due to irradiation, EHPs will be generated within the SiO2. In the absence of any electric field within the oxide, these carriers will immediately recombine; however, under a positive applied gate bias, due to the electric field within the SiO2, the generated electrons and holes would separate, with the electron moving towards the metal-SiO2 interface, and the hole moving towards the SiO2-Si interface. Thus, a space charge layer starts to build up within the oxide due to these charges, thus creating an electric field within the oxide, which is opposite to that of the applied field => changes VFB, and, thus, VT. These charges can be eliminated by thermal annealing.

4.5.4 Surface State Chargesy

A fixed charge is seen to exist within the oxide very near the Si-SiO2 interface, which results in a parallel translation in the C-V characteristics along the voltage axis these charges are called the surface state charges, and the density of these charges per unit area is denoted by These surface states have the following properties: o It is fixed, i.e., its charge states cannot be changed over a wide variation in the band bending. o Unchanged under bias-temperature stress test and thermal annealing. It is located within 200 of the Si-SiO2 interface. Its density is not significantly altered by the oxide thickness, or by the type or concentration of impurities in Si. o Its density is a strong function of the oxidation and annealing conditions, and the orientation of the Si crystal.o o

y

y

The ratio o f in (111), (110), and (100) Si are in the ratio 3:2:1, and is a strong function of the oxidation condition.

y

Popular theory: originates from the excess ionic Si in the oxide, which moves into the growing SiO2 layer during the oxidation process. can be reduced by a large extent by H2 heat treatment

y

4.6 General Expression for the Flatband Voltage VFBy

The general expression for the flatband voltage VFB can be given by

where

where m is the metal work function and

is the semiconductor is any

work function; is the oxide charges lumped at the Si-SiO2 interface, and arbitrary distribution of charges within the oxide.

4.7 Some Advanced Models 4.7.1 Unified Charge Control Model (UCCM) for MIS Capacitorsy y

y

The standard charge control model (SCCM) postulates that the interface inversion charge of electrons qns is proportional to the applied voltage swing VGT = VG -VT. This model is an adequate description of the strong inversion region of the MIS capacitor, but fails for applied voltages near and below VT (i.e., in the depletion and weak inversion regions). A new model has recently been proposed which has been shown to model the device behavior adequately both in the weak and strong inversion regions, and is given as:

where is the permittivity of the gate insulator, di is the thickness of the gate insulator, is an ideality factor, and is a correction to the insulator thickness related to the shift in the Fermi level in the inversion layer with respect to the bottom of the conduction band.y y

Note: Eq.(4.24) does not describe the mobile charge in the accumulation region, however, this region is not important for MOSFET operation. This correction is dependent on the interface electron density, however, it can be approximately taken to be a constant for typical values of the interface electron density.

y y y y y

For Si-SiO2 MOS capacitors

hence, it can usually be assumed that

The ideality factor reflects the gate voltage division between the insulator layer capacitance Ci and the depletion layer capacitance Cdep. In the subthreshold regime, At the onset of strong inversion (VGT = 0), the surface potential Vs has the value Below threshold, we have the following approximate relationship:

y

y

Note: in general, is dependent on VGT, and at low substrate doping levels, is close to unity near threshold where the gate depletion width is large (corresponding to Cdep

i.e., in deep saturation, we have

y

From Eqn.(5.105), we obtain

y

The solutions obtained represent only an approximation of the actual potential distribution in the saturation region, however, they clearly show that the potential rises exponentially with distance inside this region.

y

Based on this result and on numerical simulations of the potential in the saturation region, a simplified empirical expression linking the drain-source voltage to the length of the saturation region has been proposed:

where the constant conductance. Subthreshold Regiony

is determined from the condition of continuity in the drain

y

y

y y y y

Area of considerable research for the last few years due to low-voltage/low-power analog/digital circuit operation, where most of the devices operate very near the threshold region and some may even enter subthreshold operation. In the off state of the MOSFET, a finite drain current flows through the device, since the channel is weakly inverted, and also that there is a finite injection rate of carriers from the source into the channel. In the subthreshold regime in short channel devices, a drain voltage induces lowering of the energy barrier between the source and the channel, this effect is called the drain induced barrier lowering (DIBL) effect. DIBL causes excess injection of charge carriers from the source into the channel, and gives rise to an increased subthreshold current. This current is detrimental to both as well as digital operation. Figure 5.27 shows qualitatively the band diagram and the potential distribution at the interface in the channel, At the interface, the channel consists of three regions, the source-channel junction with length the drain-channel junction with length and the middle region of length At the interface potential in the middle of the channel can be taken to be approximately constant. A drain-source bias gives rise to a positive contribution V(x) to the channel potential => the minimum in the interface potential will be localized at the source side of the channel at Associated with the shift in the potential minimum, there will be a reduction in the interface energy barrier between the source and the channel by this is the socalled drain induced barrier lowering (DIBL) effect.

y y

y

y

DIBL is a short channel effect, which causes a drain voltage induced shift in the threshold voltage.

y y

The expression for the drain current in the drift-diffusion form can be given as where is the potential of the channel region referred to the potential of the source.

Fig.5.27 Band diagram and potential profile at the semiconductor insulator interface of an n-channel MOSFET. The symmetrical profiles correspond to and the asymmetrical profiles to The figure indicates the origin of the Drain Induced Barrier Lowering (DIBL) effect.y

y

It is also assumed that the longitudinal electric field in the channel is sufficiently small (except for the junction region near the drain) such that velocity saturation can be neglected. Multiplying Eq.(5.108) by the integrating factor the right hand side of this equation can be made into an exact derivative, and a subsequent integration from source to drain yields (assuming that the current density remains independent of x):

where n(L) = n(0) equals the drain and source contact doping density degeneracy).y y

(neglecting

y

With the source contact as the potential reference, at the source end, and at the drain end, where is the intrinsic drain-source voltage. When the device length is not too small, the channel potential can be taken to be independent of x over a portion of the channel length, i.e., and the integral in the denominator of Eq.(5.109) is determined by the contribution from this portion of the channel. Note: from Fig.5.27, the length of this section is approximately equal to and the current density can be expressed as

y

For long channel devices, and the drain current can be obtained by integrating the current density over the cross-section of the conducting channel, thus,

where is the effective channel thickness, and is the constant potential at the semiconductor-insulator interface, and is defined relative to the source electrode.y

Hence, although the interface potential relative to the interior of the p-type substrate is the built-in potential between the source contact and the

y

substrate) is positive, will be negative for n-channel MOSFETs. At threshold, the interface potential in the channel relative to the source can be expressed as is the potential relative to the interior of the substrate at threshold For simplicity, it is assumed that the substrate is shorted to the source; the effects of a substrate-source bias are found simply by replacing of course, such a replacement is only valid for negative or small positive values of , a positive comparable to would lead to a large substrate leakage current. Below threshold, the interface potential can be written as

y

y

y

y

All these equations predict that the subthreshold drain current decreases nearly exponentially with decreasing this current is practically independent of the drain-source voltage. The effective channel thickness is given by

y

y y

Note: this expression in only valid when i.e., in the depletion and weak inversion regions, and this condition is fulfilled for values of the drain current that are many orders of magnitude smaller than the threshold current. For short channel length devices, L should be replaced by as discussed earlier. 5.9.4 Drain Induced Barrier Lowering (DIBL) While dealing with short channel effects, the effective gate depletion charges were distributed evenly along the channel in order to estimate the threshold voltage shift. where are the longitudinal and transverse components of the electric field respectively, is the semiconductor dielectric permittivity, and is the charge density in the semiconductor The charge density consists of a mobile charge density and a depletion charge density is the substrate doping density. Integrating Eqn.(5.92) with respect to y from the semiconductor-insulator interface through the effective channel thickness , one obtains

y

y y

where sheet density in the channel.y

over the channel thickness and

is the electron

y

At low substrate doping and with the device biased in strong inversion such that the vertical electric field at will be small compared to the vertical field at the interface, in which case can be neglected in Eqn.(5.93). Making the substitution where V is the average of the potential over the cross-section of the channel, Eqn.(5.93) can be written as

y

The electric field at the interface is obtained by equating the electric displacement at the two sides of the semiconductor-insulator interface, leading to

y

From the conditions of velocity saturation and current continuity, the electron sheet density should be a constant in the saturated region, and its value can therefore be determined at the boundary point where the GCA is still valid; thus,

wherey

is the threshold gate voltage, given by Eqn.(5.9).

The combination of Eqns.(5.94) to (5.96) and (5.9) leads to the following second order differential equation for the channel potential in the saturated region:

where is the characteristic length in the saturation region and is given by

y

It should be noted that the solution of Eqn.(5.97) is very sensitive to the magnitude of the characteristic length for the saturated region. In comparisons with experimental data, it is therefore convenient to treat as a fitting parameter rather than using Eqn.(5.98), which itself is a result of rough estimates and approximations. The general solution of Eqn.(5.97) can be written in the following form:

y

y

y

The coefficients A and B are determined from the boundary conditions, i.e., from the requirements that with the values respectively, leading to

y

A relationship that links to the drain-source voltage is obtained by considering Eqn.(5.99) at the drain side of the channel:

wherey

with L being the gate length. resulting in

Equation (5.100) can be solved with respect to

y

Combining Eqns.(5.99) and (5.101), we find

y y

y y y

A self-consistent determination of is based on a model for the non-saturated part of the channel Owing to the complexity of Eqns.(5.99) to (5.101), it is extremely difficult to derive explicit, analytical expressions for important electrical properties, e.g., the I-V characteristics, using the present model for the saturation region. However, a numerical solution can readily be obtained which may serve as a physically based reference for simpler, more empirical models. Nonetheless, it is possible to simplify the equations somewhat in certain limiting cases. For i.e., just beyond the onset of saturation, it can be written to the first order in

y

For

>

i.e., in deep saturation, we have

y

From Eqn.(5.105), we obtain

y

y

The solutions obtained represent only an approximation of the actual potential distribution in the saturation region, however, they clearly show that the potential rises exponentially with distance inside this region. Based on this result and on numerical simulations of the potential in the saturation region, a simplified empirical expression linking the drain-source voltage to the length of the saturation region has been proposed:

where the constant conductance. Subthreshold Regiony

is determined from the condition of continuity in the drain

y

y

y y y y

Area of considerable research for the last few years due to low-voltage/low-power analog/digital circuit operation, where most of the devices operate very near the threshold region and some may even enter subthreshold operation. In the off state of the MOSFET, a finite drain current flows through the device, since the channel is weakly inverted, and also that there is a finite injection rate of carriers from the source into the channel. In the subthreshold regime in short channel devices, a drain voltage induces lowering of the energy barrier between the source and the channel, this effect is called the drain induced barrier lowering (DIBL) effect. DIBL causes excess injection of charge carriers from the source into the channel, and gives rise to an increased subthreshold current. This current is detrimental to both as well as digital operation. Figure 5.27 shows qualitatively the band diagram and the potential distribution at the interface in the channel, At the interface, the channel consists of three regions, the source-channel junction with length the drain-channel junction with length and the middle region of length At the interface potential in the middle of the channel can be taken to be approximately constant. A drain-source bias gives rise to a positive contribution V(x) to the channel potential => the minimum in the interface potential will be localized at the source side of the channel at

y y

y

Associated with the shift in the potential minimum, there will be a reduction in the interface energy barrier between the source and the channel by this is the socalled drain induced barrier lowering (DIBL) effect.

y y y

DIBL is a short channel effect, which causes a drain voltage induced shift in the threshold voltage. The expression for the drain current in the drift-diffusion form can be given as where is the potential of the channel region referred to the potential of the source.

Fig.5.27 Band diagram and potential profile at the semiconductor insulator interface of an n-channel MOSFET. The symmetrical profiles correspond to and the asymmetrical profiles to The figure indicates the origin of the Drain Induced Barrier Lowering (DIBL) effect.

y

y

It is also assumed that the longitudinal electric field in the channel is sufficiently small (except for the junction region near the drain) such that velocity saturation can be neglected. Multiplying Eq.(5.108) by the integrating factor the right hand side of this equation can be made into an exact derivative, and a subsequent integration from source to drain yields (assuming that the current density remains independent of x):

where n(L) = n(0) equals the drain and source contact doping density degeneracy).y y

(neglecting

y

With the source contact as the potential reference, at the source end, and at the drain end, where is the intrinsic drain-source voltage. When the device length is not too small, the channel potential can be taken to be independent of x over a portion of the channel length, i.e., and the integral in the denominator of Eq.(5.109) is determined by the contribution from this portion of the channel. Note: from Fig.5.27, the length of this section is approximately equal to and the current density can be expressed as

y

For long channel devices, and the drain current can be obtained by integrating the current density over the cross-section of the conducting channel, thus,

where is the effective channel thickness, and is the constant potential at the semiconductor-insulator interface, and is defined relative to the source electrode.y

Hence, although the interface potential relative to the interior of the p-type substrate is the built-in potential between the source contact and the substrate) is positive, will be negative for n-channel MOSFETs.

y

At threshold, the interface potential in the channel relative to the source can be expressed as is the potential relative to the interior of the substrate at threshold For simplicity, it is assumed that the substrate is shorted to the source; the effects of a substrate-source bias are found simply by replacing of course, such a replacement is only valid for negative or small positive values of , a positive comparable to would lead to a large substrate leakage current. Below threshold, the interface potential can be written as All these equations predict that the subthreshold drain current decreases nearly exponentially with decreasing this current is practically independent of the drain-source voltage. The effective channel thickness is given by

y

y y

y

y

y y y y

Note: this expression in only valid when i.e., in the depletion and weak inversion regions, and this condition is fulfilled for values of the drain current that are many orders of magnitude smaller than the threshold current. For short channel length devices, L should be replaced by as discussed earlier. 5.9.4 Drain Induced Barrier Lowering (DIBL) While dealing with short channel effects, the effective gate depletion charges were distributed evenly along the channel in order to estimate the threshold voltage shift. y While this may be a good approximation for it will fail to accurately predict the effect on of an applied drain-source voltage. y The reason is that a portion of the additional depletion charge induced by the drainsource bias will be distributed nonuniformly from source to drain.

y y

Fig.5.28 Distribution of depletion charge induced by an applied drain-source bias, indicated by the shaded region. is the part of the induced charge located in the central channel region, and which has its counter charge on the gate electrode

y

y y y y

y y y

y Likewise, the drain-source bias will induce a nonuniform shift V(x) in the interface potential along the channel which increases from V(0) = 0 at the source to at the drain. y A model for the distribution of the induced shift V(x) in the interface potential along the channel as a result of the applied drain-source bias is required. y From such a model, it is possible to calculate the interface potential near its minimum, which defines the barrier for charge injection into the channel (refer to Fig.5.27). y An accurate estimate of the shift in the potential minimum is especially important since the channel current is exponentially dependent on the barrier height. y In principle, this involves the solution of a 2-D Poisson's equation for the whole device, using proper boundary conditions, however, this requires extensive numerical calculations. y A simplified analytical calculation is presented below. y Start by considering the 2-D Poisson's equation for the depletion region under the gate, away from the source and drain contact depletion regions. y In the subthreshold region, the influence of the charge carriers on the electrostatics of the channel can be neglected, and the 2-D Poisson's equation can be written as

y y y

where are the longitudinal and perpendicular components of the electric field respectively. y Integrating this equation with respect to y from the semiconductor-insulator interface through the depletion region yields

y y

where is the average of over the thickness of the depletion region, which can be estimated approximately from a one-dimensional theory as

y y

y The vertical component of the electric field at the semiconductor-channel interface can be found by requiring the electric displacement to be continuous across the interface, i.e.,

y y

y In the presence of a drain-source bias, the interface potential can be written as: where is the constant interface potential of the middle part of the channel when and V(x) is the addition to the channel potential caused by the applied drain-source voltage. " Away from the source and drain contacts, it can be assumed that

" Now, consider Eq.(5.114) with and without an applied drain-source bias and express the net effect of the drain-source bias by taking the difference, i.e.,

y y y y

where is the depletion width for V = 0. y In Eq.(5.117), is replaced by assuming that V(x) inside the gate depletion region is relatively weakly dependent on the distance from the interface y The second term on the left hand side of Eq.(5.117) is equal to the difference where is the value of y Since both V(x) and its x-derivatives are small outside the depletion region of the drain contact, all terms in Eq.(5.117) can be expanded to first order in V to give

y

y y

y where

y y

y The general solution of Eq.(5.118) can be written as

y y y

where the coefficients A and B are determined from the boundary conditions. y Without much error, one can assume that Eq.(5.120) is also valid through the sourcechannel junction region in which case one has the boundary condition V(x = 0) = 0, which gives such that Eq.(5.120) can be written as

y y y y

y Here, is a constant that remains to be determined. y Note: the shift in the conduction band at the channel side of the source-channel junction is identical to the DIBL (refer to Fig.5.27). y In order to find the voltage V0, one has to consider the additional charges induced in the gate electrode and in the substrate as a result of the applied drain-source voltage.

y y

Fig.5.29 Schematic overview of the drain bias induced charges and counter charges according to the principle of charge sharing: are the induced charges in the channel and the gate, the remaining charges and counter charges are those between the drain and the substrate and between the drain and the gatey

y In order to be consistent with the potential variation along the channel, calculated earlier, the corresponding sheet charge distribution along the channel has to be as follows:

y y y

where GCA is invoked. y Assuming for simplicity that Eq.(5.122) is valid over the range following expression for range equals is obtained by requiring that the integral of the over this

y y y

y The induced channel depletion charge now remains to be determined. y The shaded region in the substrate in Fig.5.30 indicates roughly the amount of additional depletion charge induced under the gate by the drain source bias, where is the depletion width of the drain-channel junction at zero drain-source voltage. y From the concept of charge sharing, can be taken to some fraction of , i.e.,

y

y y

where is of the order of 0.5, however, the value of this parameter and also can be adjusted to account for the shape and doping profiles in the drain junction (e.g., lowly

doped drain (LDD) MOSFETs) and substrate (e.g., ion implantation); in other words, this fitting parameter is technology dependent.

y y

Fig.5.30 Simplified model of the drain bias induced charge in the substrate under the gate (shown as an estimate of the depletion charge under the gate between the depletion boundaries for The induced channel charge is a fraction of according to the charge sharing principle.y

y The parameter

can be obtained by substituting Eq.(5.124) into Eq.(5.123), i.e.,

y y

y Substituting Eq.(5.125) in Eq.(5.121) and setting injection barrier is found to be

the lowering of the

y y y

y y

y Note: The barrier lowering predicted by Eq.(5.126) decreases exponentially with increasing gate length for y For sufficiently small gate lengths or sufficiently high drain-source bias such that the DIBL diverges and Eq.(5.126) is no longer valid => this condition corresponds to severe punchthrough in the device. y By assuming that the ideality factor does not change significantly with bias conditions the shift in the interface potential can be evaluated as y Thus, as a consequence of the barrier lowering, there will be a drain bias induced shift in the threshold voltage, given by

y

where

y y

y y

Fig.5.31 Experimentally determined threshold voltage shift as a function of drain-source voltage for two NMOS devices with effective gate lengths of 0.21 and 0.25 . Equation (5.127) is fitted to the two data sets, yielding = 0.056 (L = 0.21 ) and = 0.038 (L = 0.25 ).

y y

y

Fig.5.32 Experimental values (symbols), fitted model calculations (solid lines), and exponential approximation (dotted lines) of shift in threshold voltage as a function of effective gate length for T = 85 K (lower curve) and T = 300 K (upper curve). y Note: also varies close to exponentially with

y

y Note: an accelerated shift in the threshold voltage is observed at very small values of The above estimates are simplified and partly empirical, i.e., they do not take directly into account, for example, the effect of the diffusion depth on the short channel effects, which may be important. Experimental studies show that a transition from long to short channel behavior takes place when

y

y

where respectively.y

are the drain-substrate and source-substrate depletion widths

This expression indicates the importance of the contact depth, however, indirectly, this behavior may also by accounted for by a judicious choice of the adjustable parameter

Model for Mobilityy

The mobility model, which has gained wide acceptance and is used almost universally (including BSIM) is given by

where is referred to as the low-field mobility, and degradation coefficient for mobility.y y

is referred to as the field-

This is an extremely hot area of research, and lots of work in this area is going on around the world. There are plenty of other models also available in the literature; however, most of these are empirical and based on heuristics.

Hot Electron Effectsy

y

y

As the device sizes are scaled down, the electric field in the channel increases, and, in the saturation region, the high field region near the drain occupies a large fraction of the channel length. This leads to the so-called hot electron effects, which manifest themselves in a superlinear increase in the drain current in the saturation region (the kink effect) and in the degradation of device parameters with time. These effects represent a major obstacle to further scaling down of MOSFET feature sizes.

y y

The physics of the hot electron effects can be described as follows. Electrons, while traveling from source to drain through the channel, experience a high field near the drain, and acquire large energy. When the energy thus acquired by an electron becomes equal to or greater than the band gap energy, then these electrons can collide with an atom and create EHPs (impact ionization EHP generation). The generated holes are pushed into the bulk due to the electric field, thus constituting the substrate current, and the electrons increase the drain current in the saturation region, thus causing the kink in the drain current characteristics. Some of these electrons may even acquire such a large energy from this field that they can surmount the barrier and get trapped in the oxide => this gives rise to instability in the device behavior, since these electrons can alter the charge states in the oxide. The process of EHP generation can be described by a generation rate G, which is an exponential function of the maximum electric field in the channel , which is reached at the drain:

y

y

y

y

where A is a constant, is the drain current, and is the characteristic field for the impact ionization, given by where is the energy required for an ionization event, and is the mean free path for the ionization process.y y y

Typical value of is 1.7 mV/cm for Si n-channel MOSFETs. The generation rate is proportional to the drain current since it ought to be proportional to the product of the electron sheet density in the channel and the electron velocity. The maximum electric field is given by is the intrinsic drain-source voltage, is the intrinsic drain-source saturation voltage, and is the length of the pinch-off region, given by

where is the field required for velocity saturation, and is a characteristic length of the electric field variation in the high field region near the drain and is given by

y

The substrate current

is proportional to the generation rate, hence,

where B is a constanty

Equation (5.133) can be rewritten as

where

y

Analysis shows that only one iteration is sufficient to accurately solve this equation by iteration if is substituted by in Eq.(5.134). Note: the measured values of Y depend linearly on the drain-source voltage in the kink region, thus, Eq.(5.134) can be used for the extraction of the saturation voltage from the experimental data. Hot electrons can also tunnel into traps in the gate oxide near the drain. The negative charge in the oxide causes partial channel depletion near the drain, leading to an increase in the channel resistance and a decrease in the threshold voltage in this region. Hence, the device characteristics change with time when the drain voltage is high enough to cause significant electron heating (i.e., under voltage stress). The increase in the channel resistance should lead to a shift in the drain-source saturation voltage (it increases) and a reduction in the drain-source current.

y y

y y

Fig.5.33 Measured Y versus

curves.

Fig.5.34y

y y

Measured I-V characteristics and Y-functions for an n-channel Si MOSFET: open symbols data before stress, dark symbols data after stress at for 104 sec. As can be seen from Fig.5.34, the Y versus curves experience a parallel shift as a result of the voltage stress. This electron trapping also causes a change in the drain current, given by

where

is a constant.

y

Fig.74 Measured values of

(in percent) under stress versus time.

MOSFET Models and SPICE Parametersy y

A large number of MOSFET models exist in literature, the most popular among them is the BSIM (Berkeley Short-Channel IGFET Model). Currently, significant research is going on in the area of MOSFET modeling, in order to make these models more accurate in describing device behavior for ultra-short channel length devices. There are different levels of these models, e.g. LEVEL 1: Shichman-Hodges LEVEL 2: Geometric based analytical model LEVEL 3: Semi-empirical short channel model LEVEL 4: BSIM LEVEL 5: New BSIM (BSIM2) LEVEL 6: MOS6 (Sakurai and Newton) LEVEL 7: Universal extrinsic short channel model LEVEL 8: Unified long channel model (UCCM) LEVEL 9: Short channel model LEVEL 10: Unified intrinsic short channel model

LEVEL 11: Unified extrinsic a-Si TFT model LEVEL 12: Polysilicon TFT model The list given above is by no means complete, and there are plenty more new models, which describe short channel device behavior more accurately than their predecessors.y y

y y y y y y y y

For SPICE simulation, the MOS element is defined in the following way: MX ND NG NS NB MNAME where MX is the device number; ND, NG, NS, and NB are the node numbers for the drain, gate, source, and substrate respectively; L and W are the channel length and channel width respectively, AD and AS are the areas of the drain and source respectively, PD and PS are the perimeters of the drain and source respectively, NRD, NRS, NRG, and NRB are the relative resistivities of the drain, source, gate, and substrate respectively in number of squares, OFF indicates an optional initial value for the element in a DC analysis, the optional initial value IC=VDS,VGS,VBS is to be used together with UIC (use initial condition) in a Transient analysis, and the optional TEMP value is the temperature at which this device operates. Parameters for LEVELs 1, 2, 3, and 6: VTO KP PHI zero-bias threshold voltage process transconductance parameter body effect coefficient surface potential

GAMMA

LAMBDA channel length modulation parameter RD quasi-neutral drain resistance RS quasi-neutral source resistance RG gate resistance RB bulk ohmic resistance RDS drain-source shunt resistance CBD zero bias drain-substrate junction capacitance CBS zero bias source-substrate junction capacitance IS source/drain-substrate junction saturation current PB built-in voltage of the source/drain-substrate junction CGSO gate-source overlap capacitance per meter channel width CGDO gate-drain overlap capacitance per meter channel width

CGBO

gate-substrate overlap capacitance per meter channel length

RSH drain/source diffusion sheet resistance CJ zero bias bulk junction bottom capacitance per square meter of junction area MJ bulk junction bottom grading coefficient CJSW zero bias bulk junction sidewall capacitance per meter of junction perimeter MJSW bulk junction sidewall grading coefficient JS bulk junction saturation current per square meter of junction area TOX gate oxide thickness (m) NSUB substrate doping NSS surface state density NFS fast surface state density TPG type of gate material: +1 (opposite of substrate), 1 (same as substrate), 0 (Al gate) XJ metallurgical junction depth (m) LD lateral diffusion along length (m) WD lateral diffusion along width (m) UO surface mobility COMPOUND SEMICONDUCTOR FIELD-EFFECT TRANSISTORS(MESFETs) Introductiony

y

y

y

Currently, compound semiconductor FETs play important role in the electronics industry, e.g., GaAs FET amplifiers, oscillators, mixers, switches, attenuators, modulators, and current limiters are widely used, as well as high-speed ICs based on GaAs FETs and heterostructures FETs (HFETs) have been developed. Basically obtained by combining elements from columns III and V of the periodic table, e.g., GaAs, InP, InAs, InSb, AlAs, etc., having a wide range of band gaps (both direct and indirect), lattice constants, and other physical properties. Solid-state solutions are also possible, e.g., by varying the composition x (from 0 to 1) continuously in the ternary compound , one may obtain a continuous change of the different material properties, as the material changes from GaAs to AlAs. GaAs is the most studied and understood compound semiconductor material, and has proved indispensable for many device applications, e.g., ultra high speed transistors to lasers and solar cells. Room temperature lattice constant of GaAs (5.653 ) is very close to that of AlAs

y

y

(5.661 ) => the heterointerface between these two materials would have very small density of interface states => ideal candidate for heterostructures lasers. Technological innovations, e.g., Molecular Beam Epitaxy (MBE) and Metal Organic Chemical Vapor Deposition (MOCVD), allow growth of heterostructures with very sharp

y

and clean heterointerfaces, and have very precise control over doping and composition profiles, typical resolution being of the order of the atomic distances. Other compound semiconductors having applications in ultra high speed submicron devices include , GaP, InP, AlN, etc.

Advantages of GaAs Systemsy

y

y y

y y

The room temperature electron mobility in GaAs (8500 ) is much higher than that in Si (1250 ), due to the lower electron effective mass in GaAs (0.067 , where is the rest mass for electrons) as compared to Si (0.98 for longitudinal effective mass and 0.19 for transverse effective mass). Also, under high electric fields, the light electrons experience "ballistic transport" in GaAs for submicron devices, i.e., the electrons may move over a small distance without suffering any collision (with either lattice vibration or lattice imperfections) at all, and, thus, their instantaneous velocity can be far higher than that in Si. Such ballistic transport is observed in devices having active device dimensions of 0.1 or less. For devices having active dimensions between 0.1 and 1.5 , electron velocity "overshoot" effects are important, which may also result in boosting the electron velocity to considerably higher levels than the stationary values. These effects are related to the finite time that it takes for an electron to relax its energy. As shown in Fig.6.1, electrons very close to the injecting contact are moving ballistically and the electron velocity is proportional to time.

Fig.6.1 Electron velocity versus distance for electrons injected into a region of constant electric field.y y

Further from the contact, the velocity reaches a peak value, the electron suffers a collision, and then the velocity decreases. Note: due to the overshoot effects, the peak value of the velocity is much higher than the stationary value reached as the distance increases further.

y y

y

y y

In Si, ballistic and overshoot effects may also occur, however, they are much less pronounced due to the larger electron effective mass. Another important advantage of GaAs and InP devices is the availability of semiinsulating substrates, which eliminate parasitic capacitances related to junction isolation, and makes high-speed operation possible and allows fabrication of micro strip lines with small losses (especially important for applications in Microwave Monolithic Integrated Circuits (MMICs)). Also, GaAs being a direct band gap semiconductor, it is highly suitable for optoelectronic applications and makes possible a monolithic integration of ultra high speed submicron transistors together with laser or LEDs on the same chip for use in optical communication. These devices also have better radiation hardness since the direct band gap results in high electron-hole recombination rates. New technologies, e.g., MBE and MOCVD, and availability of excellent heterostructures systems, e.g., AlGaAs/GaAs, GaInAs/InP, InGaAs/AlGaAs, etc., have opened up a plethora of new quantum devices, such as Heterostructure Field Effect Transistors (HFETs), Heterojunction Bipolar Transistors (HBTs), Hot Electron Transistors (HETs), Induced Base Transistors (IBTs), Permeable Base Transistors (PBTs), Vertical Ballistic Transistors (VBTs), Planar Doped Barrier Transistors (PDBTs), etc.

Drawbacks of GaAs Systemsy y y y

y y

y

As compared to Si technology, GaAs technology is far more complex and risky (since As is potentially a lethal substance). Also, since As have very high vapor pressure, they tend to evaporate from the surface, making the crystal Ga rich => technological problem. Si has an excellent native oxide ( ), having reasonably high dielectric constant and excellent breakdown strength. On the other hand, the native oxide grown on GaAs (yielding both ) is nonstoichiometric, have very poor electronic properties, and creates a very high density of interface states => GaAs MOSFETs still remain a dream. Alternate choices: wide band gap AlGaAs and AlN may substitute as an insulator, however, the performance is not encouraging. Recently, on GaAs (oxidizing thin layers of Si deposited on GaAs by MBE) technology holds some promise for developing GaAs MOSFETs sometime in the near future. In any case, currently Schottky barrier MEtal Semiconductor Field Effect Transistors (MESFETs), Junction Field Effect Transistors (JFETs), and Heterostructure Field Effect Transistors (HFETs) are the most commonly used GaAs devices.

Major Application Areasy

y

Mostly used for microwave and ultra high speed applications, where their high speed properties are the most important, hence, scaling down the device sizes in order to exploit the ballistic and/or overshoot effects of the electron velocity are especially important. Use in the areas of

y y y y

optoelectronics (direct band gap) radiation-hard electronics (rapid EHP recombination due to direct band gap) high-temperature electronics (large band gaps of most compound semiconductors permit their use at high enough temperature, without leakage becoming excessive) power devices (high breakdown field and the ability to speed-up their turn on by light)

Modeling Aspectsy

y

y y y y y

Since this technology is much less developed than its Si counterpart, reliable circuit and device modeling is especially important, and development of accurate device models is a prerequisite for the commercialization of compound semiconductor technology. Accurate device models have to be based on insight into the physics of the devices, obtained from numerical simulations such as self-consistent two-dimensional Monte Carlo modeling. Clearly, numerical device simulations are not directly applicable to circuit design involving hundreds to thousands of transistors interacting with each other and with other circuit elements, nor in device design where numerous dependencies of device characteristics on the design parameters have to be optimized, nor in device characterization where the device and process parameters must be extracted from experimental data. All these tasks require accurate analytical or semi-analytical device models, which must be based on physical device and material parameters, rather than using look-up tables and simple interpolations of the measured device characteristics, in order the provide the necessary feedback between the fabrication process and the device and circuit design.

Basic MESFET Modelsy

y

GaAs MESFETs are widely used in both analog as well as digital applications, with their microwave performance challenging that of HFETs, and their IC integration scale rapidly approaching 100,000 transistors per chip and beyond. With thin, highly doped channels and low parasitic resistances, GaAs MESFETs can obtain high currents and transconductances.

Fig. 6.2 Schematic representation of a MESFET.

y

y y

y

y

y

y

The gate electrode is deposited directly on the semiconductor and forms a Schottky barrier contact with the conducting channel underneath, between the source and drain ohmic contacts. The gate bias modulates the depletion region under the gate and, thus, modulates the effective width of the neutral channel and thus the current flow between source and drain. Note: the carriers under motion in the channel do not come under close proximity of the interface due to the depletion region and, thus, the problems related to interface traps are largely avoided. Also, since the forward voltage that can be applied to the gate is limited by the built-in potential of the Schottky barrier, hence, it is a drawback when the device is operated in enhancement (normally off) logic, however, this limitation is less severe for low power circuits operating with a low power supply voltage. Historically, MESFETs were discussed in early days in terms of the Shockley model, where carrier velocity saturation effect was neglected, and it was assumed that current saturation at high drain-source bias took place as a result of the channel getting pinchedoff at the drain side of the channel. This model may be applicable for devices having very long channel lengths, however, gives a poor description of modern day devices having gate lengths of the order of 1 m or less. A deeper insight into MESFET device physics can be obtained from a detailed twodimensional Monte Carlo simulation, however, simple analytical of semi-analytical models based on the device physics are still required for circuit simulators.

The Shockley Modely y

Consider first the gate region of a MESFET (intrinsic device) with a uniform channel doping , a channel thickness d, and a built-in voltage for the gate contact. With a channel potential V(x) (relative to the intrinsic source) and an intrinsic gatesource voltage , the depletion width can be expressed (using the gradual channel approximation [GCA]) as

where is the dielectric permittivity of the semiconductor and of the source-channel junction.y

is the built-in voltage

The threshold voltage corresponds to the gate-source voltage at which the depletion width at zero drain-source bias (V = 0) equals the channel width, or, in terms of Eq.(6.1)

where is referred to as the pinch-off voltage, and for a uniformly doped channel, is given by

EXAMPLE 6.1: A GaAs ( = 12.9) n-channel MESFET has a uniform channel doping of and an active layer thickness d of 1 m. Determine the pinch-off voltage and the threshold voltage , assuming that the -source doping is 5 x . SOLUTION: From Eqn.(6.3), the pinch-off voltage

The source channel junction is a high-low (

-n) junction, thus, the built-in voltage is given by

Therefore, from Eqn.(6.2), the threshold voltage is given by = = 0.16 - 0.7 = - 0.54 V.

y

y y y

y

For > , the channel is not fully depleted and a finite neutral region exists in the channel, which allows a significant drain current to pass, with magnitude increasing with an increase in . For < , the channel is fully depleted, and the drain current drops to a low value, characteristic of the subthreshold region of operation. Note: from Eqn.(6.1), it is obvious that the depletion width under the gate increases from source to drain when a positive drain-source bias is applied. The depletion width at the drain side of the gate , where L is the gate length, is obtained by replacing the channel potential by the intrinsic drain-source voltage in Eqn.(6.1). In the absence of velocity saturation of carriers, increases with increasing until the channel is pinched-off, which occurs when = d, corresponding to In the Shockley model, it is assumed that the electron drift velocity is proportional to the absolute value of the longitudinal electric field E = |dV(x)/dx|, i.e., = E, where is the low-field electron mobility. Under GCA, the potential drop dV across a small length dx along the channel can be written as

y

y

where Id is the drain current, dR is the channel resistance of the small section of length dx, and W is the gate width.y y

Equation (6.4) is valid below pinch-off, i.e., < d. Substituting the expression for dd(x) from Eqn.(6.1) into Eqn.(6.4), and integrating x from 0 to L, and V(x) from 0 to , the following drain current characteristic is obtained

y y

is the conductance of the undepleted channel. Equation (6.5) is referred to as the fundamental equation for FETs, and is valid only for . From Eqn.(6.5), it can be easily shown that the channel conductance becomes zero when = , hence, it can be argued that the drain current saturates at this value of , called the saturation voltage and, according to the Shockley model, = , and the corresponding drain saturation current becomes

EXAMPLE 6.2: Consider the n-channel GaAs MESFET of Example 6.1 with L = 1

and W =

5 . Determine the saturation drain voltage, drain current, and the transconductance for 0.3 V, and VDS = 0.1 V and 0.5 V. Assume n = 8500 . SOLUTION: The saturation drain voltage = = = 0.3 + 0.54 = 0.24 V.

=

The conductance of the undepleted channel

For the first case, (= 0.1 V) is less (= 0.24 V), hence, the device is under linear mode of operation, and the drain current is given by

Since is quite small, hence, from the approximate relation given by Eqn.(6.10), A/V, which is quite close to the answer obtained.

= 60

Now, for the second case, (= 0.5 V) is greater than (= 0.24 V), therefore, the device is under saturation mode of operation, and the drain current is given by

Velocity Saturation Modely

y y

In the Shockley model, it was assumed that the carrier drift velocity increases linearly with the electric field, and from current continuity, it follows that the carrier drift velocity at the drain side of the gate approaches infinity as the pinch-off condition = d is reached, which is, of course, absurd. Rather, carrier velocity saturation would occur at sufficiently high electric fields, which gives an alternate mechanism for current saturation in the device. A simple way of dealing with carrier velocity saturation is to assume a two-piece linear velocity-field relationship of the form

where is the carrier saturation velocity, and carrier velocity saturation.y y

is the electric field required for

For E(L) , the results from the Shockley model are still valid. Hence, the new saturation voltage, defined as the drain-source voltage at the onset of carrier velocity saturation, can be determined from Eqn.(6.4) in combination with Eqns.(6.1) and (6.5), resulting in the expression

y y

y

From Eqn.(6.13), it can be seen that the saturation voltage corresponding to the Shockley model, i.e., = is recovered when >> 1. On the other hand, in the opposite limit, i.e., when