Pergamon Microelectron. Reliab., Vol. 37, No. 9, pp. 1301-1307. 1997

© 1995 IEEE. Published by Elsevier Science Ltd Printed in Great Britain

PII: S0026-2714(97)00002-4 0026-2714/97 $17,00 + 0.00

MOS TECHNOLOGY: TRENDS AND CHALLENGES IN THE ULSI ERAt

ASHWIN SHAH and PING YANG Semiconductor Process and Device Center at Texas Instruments Inc., Dallas, Texas 75243, U.S.A.

Abstract--This paper reviews the trends in the MOS technology as we approach the turn of the century, and addresses the challenges that we face as the device geometries continue to scale and as the need to lower power dissipation grows, albeit with the demand for increasing device performance. © 1995 IEEE. Published by Elsevier Science Ltd,

1. INTRODUCTION

Since the invention of the bipolar transistor in the 1950s the semiconductor industry has grown rapidly. However, the MOS technology, especially the CMOS technology, has given a tremendous boost to the semiconductor industry since the late 1960s. The trend has been to scale down the feature size and the devices for higher density, higher performance, lower cost, and improved reliability. However, as the devices are scaled further down to below 0.5/am the task to maintain these trends becomes much more difficult. In addition to density, performance, cost and reliability improvements, we need to pay very close attention to the power dissipation. The mainframe systems of yesterday are transforming into the hand-held battery operated devices of today. Portable hand-held and pocket devices are the way of the future. The extended battery life of these devices is critical to their success in the market. Even though new battery technologies such as lithium-ion are emerging, with a greater power density, the future semiconductor devices wil have to be much more energy efficient. Since the power dissipation equals CV:f, it is clear that lowering the supply voltage can reduce the power dissipation sufficiently. However, the transistor performance also tends to drop undesirably.

In this paper we first examine these trends in MOS technology for both transistor and interconnect. Next, we examine the impact of the needs arising from low power.

2, TECHNOLOGY TRENDS

The MOS technology process flow can be divided into transistor flow (FEOL--front end of the line) and interconnect (BEOL--back end of the line).

t © 1995. IEEE. Reprinted and revised, with permission from Proceedings of 20th International Conference on Microelec- tronics, NiL 12-14 September 1995, Vol. 1, pp. 3-9.

In this section we examine the general VLSI trends, for both transistor and interconnect technologies. Low power specific trends and challenges will be discussed in the next section.

2.1. General submicron technology trends

2.1.1. Transistor trends. Figure 1 shows the typical structure of a metal-oxide-semiconductor field effect transistor, identifying the major regions. It is helpful to begin the discussion of technology trends by examining a projection of MOSFET technology, beginning with 0.5/am in 1992 and extending to 0.I0/am in 2007. Table 1 shows that the quasi-con- stant voltage scaling scenario which preceded the 0.35/am is forever a thing of the past. Each new technology generation is required to re-examine all aspects of device design. The gate dielectric thickness is decreasing in a way that maintains approximately a constant nominal electric field in the dielectric, for reliability reasons. The junction depth is decreasing as the feature size is reduced, although the trend is for the ratio of junction depth to feature size to increase. The threshold voltage is decreasing as the supply voltage is decreased, in such a way that the ratio of threshold voltage to supply voltage increases at first and then saturates.

The overriding theme in device design as technology scales is the increased importance of two-dimensional (2D) effects. It used to be that transistor design could largely be done by optimizing separate regions which behaved approximately as one-dimensional regions. This included the source and drain (S/D) diffusion region extending under- neath the edges of the MOS transistor, and the channel region in the middle between the source and drain. While 2D simulators that comprehend electrical effects have been available for some time, in the deep submicron regime, the proximity and interactions between the various regions require accurate 2D simulation of process effects as well.

Examples include the use and optimization of a lightly, or medium doped drain (LDD, MDD)

1301

1302 A. Shah and Ping Yang

,,uN i , t-.o-, t . . , . , . .

I l l , . ' . , , , l

Fig. 2. The importance of 2D effects in short channel devices I I [ , . . , . . ~ii)} as illustrated by the effect of interstitial injection from S/D regions and the resulting B dopant pile up in the channel

[ [ I LJIIIIIIIy doped ~ ~ region ensuing from the enhanced diffusion. Compare the I~lmll~l ~ short channel profile to the long channel profile [1].

I IWNnm m i h a

Fig. 1. A typical MOSFET structure, showing the gate, source/drain and channel regions.

extensions, pocket implants at the edges of S/D extensions and the use of super-steep retrograde channel doping. Furthermore, the doping of the channel region can be strongly influenced by its proximity to the S/D regions. Lateral non-uniformity of the channel boron implant in an nMOS transistor can occur due to segregation to the S/D implant region or due to diffusion modulation arising from interstitial injection from the S/D regions. As an example, Fig. 2 shows a comparison of a dopant profile in a short channel and moderately long channel device, from the work of Rafferty et al. [1]. The dopant pile up in the short channel device is caused by the proximity of the channel region to the S/D regions and by the interstitial injection from the S/D regions which enhanced the diffusion towards the surface.

Another important trend in transistor scaling is the oxide electric field Eox. In Fig. 3 this is plotted vs the gate length (these data were compiled from over 40 papers published in the literature). The electric field plotted here is the nominal oxide field. Vdd/tox, without correcting for band bending in the gate and substrate, and hence it is larger than the actual Eox. Earlier, we indicated that the oxide electric field remains approximately constant with scaling. What is interesting about the detailed trend in Fig. 3 is that the oxide electric field is actually increasing, albeit slowly, as the gate length becomes shorter.

One of the problem areas in device design relating to performance and oxide reliability is the limited ability of thermal oxide to block the boron diffusion used to dope the polysilicon (poly) gates of surface channel pMOS transistors. As a consequence, for a given oxide thickness, the doping level is intentionally kept lower that is otherwise desired. This has the electrical effect of causing increasing band bending in the poly gate, which in turn reduces the electric field in the oxide. In turn, a reduced oxide electric field means reduced channel charge in inversion and lower drive currents for the pMOS device. Technology evolution will increasingly require the implemen- tation of alternative gate dielectrics which reduce boron diffusion, and maintain adequately high channel charge and mobility at a dielectric field which has an equivalent reliability to thermal oxide. The continued scaling of dielectric thickness makes this an industry "must-do".

2.1.1. Interconnect trends. Just as gate length characterizes the scaling of the MOSFET transistors, metal pitch and the associated contact, or via size characterize the scaling of metal interconnect systems. Table 2 illustrates trends in metallization interconnect. Reduced pitch at each new technology generation will occur. As we will see later, the increase in the number of levels of interconnect has an impact on interconnect current density con- straints.

It is instructive to understand the implications of technology scaling on technology performance, since these in turn have important implications on reliability requirements for interconnect. The

Table 1. MOSFET technology projection

Feature size (#m) 0.5 0.35 0.25 0,18 0.12 0.10 Year of introduction 1992 1995 1998 2001 2004 2007. Technology voltage Vdd(V) 5.0--3.3 3.3--2.5 2.5--1.8 2.0--1.2 1.5--0.9 1.0-? Threshold voltage VT (V) 0.8-0.7 0.7-0.6 0.64).45 0.5-0.3 0.4-0.2 0.25-? Gate oxide thickness tox (nm) 12-9 9-6 6.5-4 5-4 4-? 3.5-? Junction depth xj (nm) 150 100 60 40 25 15 DRAM density (byte) 16 M 64 M 256 M 1 G 4 G 16 G

MOS technology in the ULSI era 1303

O Ill ~ 1 ~ ....

o.1 o.~ . . . . . . . t . . . . . . i ' o

Fig, 3. Nominal gate oxide electric field vs gate length, Fig. 4. Signal delay scaling vs feature size, showing the showing an increasing trend for Eo~. increase in delay at the smaller dimensions caused by

interconnect resistance and capacitance.

performance of a technology can be most simply summarized by the delay time td for a logic signal, which is given by:

td = Ro(C,, + CJ + (RoC + RC,)L + ~ RCL 2. (l)

Here, Ro, Co and C~ are the output resistance, output capacitance and input capacitance of the CMOS inverter stage driving the signal line, respectively. They are functions of the transistor design and the circuit design W/L ratios used. R and C are the resistance and capacitance per unit length of the signal line, and are functions of the interconnect design. The three terms on the right hand side of eqn (1) represent the intrinsic stage delay, the load delay and the line delay contributions, respectively.

We introduce the scaling parameter S, which is defined as the ratio of feature size of a newer technology generation to the feature size of an older reference technology generation. Thus S is always less than one. There are two simplified scaling scenarios for interconnect:

• Scale the pitch at constant metal thickness. • Scale the pitch and the metal thickness.

Under the first scenario, the load delay, line delay and current density will scale as l/S, 1IS 2, and l IS, respectively. Under the second scenario, the load delay, line delay and current density scale as 1IS 2, I/S 2, and 1/S 2, respectively. In either case, it can

be seen that interconnect delays begin to dominate technology performance and that current density requirements increase with scaling.

This increase in delay from interconnect parasitics can be clearly seen in Fig. 4, where simulated signal delay is plotted vs feature size. The increase in current density under the two interconnect scaling scenarios is illustrated in Fig. 5.

These interconnect scaling requirements plus the low power requirements drive several technology enhancements. Lowering interconnect capacitance drives the use of low dielectric constant materials, particularly for intra-level capacitance. Lower resist- ance and larger current density (with corresponding EM resistance) drive the use of new metallization systems, e.g. copper.

2.2. Low power specific technology trends The most efective ways to achieve low power from

a technology viewpoint are to reduce the supply voltage and interconnect capacitance. In this section we examine the low voltage transistor designs and low dielectric constant (K) material.

2.2,1. Low voltage transistor designs. Although reducing power supply (to 1V or below) is very effective in reducing power consumption, it poses a serious trade-off between speed performance and transistor leakage current (and thus leaking power). One approach to this dilemma is to implement very

Table 2. Interconnect technology projection. Note: all units in #m

Contact size 0.6 0.45 0.35 Metal 1 pitch 1.5 1.0 0.7 Via 1 size 0.6 0.45 0.35 Metal 2 pitch 1.5 1.0 0.7 Via 2 size 0.8 0.45 0.35 Metal 3 pitch 2.0 1.0 0.7 Via 3 size 1.2 0.45 0.35 Metal 4 pitch 4.0 2.6 0.7 Via 4 size - - 0.8 0.6 Metal 5 pitch - - 2.6 1.6 Via 5 size - - - - 0.6 Metal 6 pitch - - - - 1.6

I,.. l 0.1 1

betur, e l r~m)

. . o - I I b ~ r o l l

I-VI - -~- 1ollol l i l l l l l l

I - us:

Fig. 5. Current density scaling vs feature size, showing the increase in current density required as feature size scales

downward.

1304 A. Shah and Ping Yang

) ° i - o., o., .J, E_ L_J o., 0

1 7 -0.1 I , ,V, , , , ,~ l ,, 0.00 0.08 0.10 0.15 0.20

Oepth (urn)

Fig. 6. Typical dopant profiles of SSR, conventional and counterdoping (CD) for NMOS.

0 0.2 0.4 0.6

L G (urn)

Fig. 7. Threshold voltage measured at Voo = 1 V as a function of gate length for NMOS devices with different

channel profiles.

low Vr devices (0 ~ 0.2 V) in addition to the regular VT (0.4--0.6 V) devices. The low lit devices then can be used in the critical speed paths to improve the circuit performance while the high Vx devices can be used effectively to reduce the leakages.

The transistor design for the low- lit CMOS devices is not trivial; the effective substrate concentration for the IoW-VT devices needs to be low to reduce VT which, however, tends to enhance the undesirable short-channel effects. One approach is to use a super-steep retrograde (SSR) profile [2] with surface counter doping (CD) to lower Vx and maintain a reasonable short-channel effect (e.g. Vr-rolloff). Figure 6 shows typical SSR, conventional and arsenic CD profiles for NMOS devices. The counterdoping is needed to lower the Vr to the range desired (0.05-0.15 V), which cannot be easily achieved by SSR only or thin surface epitaxial layer [3]. On the other hand, the underlying SSR profile is shown to be superior to a conventional channel/well dopant profile [4] in terms of reducing VT-rolloff. As for the high-Vr devices, the transistor design issues are similar to those of the higher VDD technologies [2]. Based on the highest nominal IDR[VE, the "optimum" designs for high-VT and low-VT CMOS are deter- mined, and the corresponding SPICE models and figure-of-merit (FOM) [6] are generated and verified with measured inverter delays. The simulated power and delay (or I /FOM) are compared to the values reported in the literature [7, 8].

The evaluation process of the various n-channel profiles is shown in Figs 7-9. Figure 7 compares the VT vs Lc for the various devices. For the high-VT device, the device with SSR profile has a better Vr-rolloff, compared to the conventional one, as was reported in Ref. [2]. With the addition of surface counter doping (CD) to lower VT, the SSR + CD cases are shown to preserve the good Vr-rolioff characteristics of the SSR-only case, while the conventional = CD case has a significantly worse Vr-rolloff. Since the device with conventional + CD profile has a negative Vr at the target Lc = 0.25 #m,

only the SSR, SSR + CD and conventional profiles are chosen for the subsequent /DRWE VS gate length control (L~) comparison shown in Fig. 8. The /DRWE values at LG = 0 correspond to the worst case IOVF of 0.2 mA/#m, while the nominal IDR,VE values corre- spond to LG = 0.25 ~m (the gate length control for LG ----- 0.25 #m CMOS). It is clear that the two SSR + CD cases have the highest nominal IDRWE- Since the SSR + CD (high dose) case has much less /DRWE sensitivity against Lc than the SSR + CD (low dose) case, the former is considered as an "optimum" design for low-lit NMOS. The reason for the higher nominal IDR]VE for the SSR + CD profile is evident from Fig. 9, where the effective electron mobility (m~) of various profiles is plotted as a function of effective field E~. The fact that the SSR + CD (high dose) profile has the highest mo~ vs Ee~ is consistent with the well-known result that buried-channel devices have higher me~ than that of surface channel devices and can be attributed to less Coulombic scattering [9], since the effective substrate dopant concentration is the lowest for the SSR + CD (high dose) case.

Using this same methodology, the "optimum" design for IoW-VT PMOS and high-VT CMOS is

4OO

0 0.02 0.04

AL O (urn)

Fig. 8. Sensitivity of NMOS drive current (at Vt)D = 1 V) to gate length control (L~) for the cases shown in Fig. 2. lor~

at k = 0 is equal to 0.2/aA//~m.

MOS technology in the ULSI era

150I ~ v r

4 II 8 10 0.6 0.8 1 1,2 1.4 1.6 1.8 2 [ , . (x 1o s) [ w / m ) powersupp vobge(v)

Fig. 9. Effective mobility for NMOS devices with different channel profiles as a function of effective electric field (~).

The SSR + CD case has the highest LI0~ at V~ = 1 V.

1305

Fig. 11. Comparison of inverter delay (from SPICE and I/FOM) for high- and low-Vr CMOS with data from Ref.

[8].

chosen, and the corresponding lit vs Lc (Vr-rolloff) characteristics are shown in Fig. 10.

The inverter delays with these optimum channel profiles are evaluated using the performance figure- of-merit (FOM) [6] and SPICE simulations. Figure 11 shows the inverter delays (calculated from I/FOM and SPICE simulation) for the high-Vr and low-Vr inverters operated at different Voo. The delay for the high-VT inverter is comparable to the reported results [8] at Iioo = 1 V. Figure 12 compares the power-delay trade-off for our high-VT and 1ow-VT LG = 0.25 #m CMOS inverters with the reported results of 0.12/tm, 0.25/~m and 0.5#m (L0~) technologies [7]. The Lon = 0.12 #m is the best case as expected, while our 0.25 pm data are reasonably well positioned relative to it.

2.2.2. Low dielectric material for interconnect. As discussed in previous sections, as the features sizes of VLSI technology decreases, the interconnect RC time constant increases rapidly. In addition, the power consumption is directly proportional to the capacitance, In order to achieve low power and to retain the performance advantage, as well as to mitigate the cross-talk disadvantage from scaling, the interconnect capacitance must be reduced through

the use of low K materials. There are many dielectric materials, including pure polymers, spin-on-glasses (SOG) and porous materials, that offer lower values of permittivity than SiO2 (Table 3). Both process integration and materials selection represent a great challenge to the semiconductor industry. In this section we will present a general overview of this topic.

2.2.2.1. Common integration problems

In order to successfully integrate the low-dielectric- constant materials into standard on-chip interconnect structures, the new materials must meet stringent process and reliability requirements such as: (1) high mechanical strength, (2) good dimensional stability, (3) high thermal stability, (4) ease of pattern and etch for submicron features, (5) low moisture absorption and permeation, (6) good adhesion, (7) low stress, (8) good etch selectivity to metal, (9) high thermal conductivity, (10) high dielectric strength, (11) low leakage current, and (12) good gap filling and planarization capability.

The dimensional stability, thermal stability and thermal conductivity of polymeric materials are

0.6 100

0.4 I t 0.2 10 0

~'I"0~" 1

-0.4

-0.6 0.1 0 0.2 0.4 O,e

L a (urn)

~ ,uvo.am Ld [1] 2. uv o:..m p]

, k".% z

IBM V O J l ~ ~ 111

. . . . . . . . . ! I . . . . . .

10 100 1000 I n w W

Fig. 10. Threshold voltage (VT) VS Lo for optimum 1oW-VT Fig. 12. Comparison of simulated power delay trade-off for and high-VT devices, the high-lit and low-lit inverters with data from Ref. [7].

1306 A. Shah and Ping Yang

Table 3. Partial list of materials for intermetal dielectric applications

Dielectric constant Material Method

Inorganic 4.1~,.5 Undoped plasma sin2 CVD

3.5 Fluorine doped SiO2 CVD < 2 Porous sin2 Spin-on

Organic 3.0-3.7 Polyimide Spin-on 2.7-3.0 Polysilsesquioxane (Si polymer) Spin-on

2.7 Benzocyclobutene (BCB) Spin-on 2.7 Parylene N CVD

~ 2.5 Fluorinated polyimide Spin-on 2.3 Parylene F CVD

~ 2.3 Poly-naphthalene CVD 1.9 Amorphous Teflon Spin-on

< 2 Polymer foams Spin-on

inferior to that of sin2 [10]. The decomposition temperature and dimensional instability (such as creeping) of polymers limit the processing tempera- ture and total thermal budget (temperature times time) used in the integration flow. Since pure polymers have a lower mechanical strength than sin2, polymers do not suppress hillock formation in interconnects as effectively as sin2, resulting in a shorter electromigration lifetime of A1 alloys [11]. Delamination due to poor adhesion is a common problem for polymer ILD materials. Figure l(a) shows delamination of a plasma sin2 cap layer from an organic spin-on-glass (polysilsesquioxane) surface during CVD tungsten deposition. The high stress in the tungsten film peels the plasma sin2 layer from the weak plasma SiO2/SOG interface; the exposed SOG surface can be clearly seen in Fig. l(b). The lack of sidewall passivation in the oxygen plasma used to etch polymeric materials is an especially critical issue for submicron via integration. In addition, outgassing from the polymer inside via holes often leads to high via resistance (via poisoning). These processing and reliability problems impede the implementation of low-dielectric-constant polymers in the standard interconnect processing.

2.2.2.2. New schemes for low K integration

Two new schemes for low K integration in a multilevel interconnect system will be described here. Both combine the advantages of sin2 and a low dielectric constant of polymeric materials by using polymers only between tightly spaced lines. The first scheme requires one extra mask to define the trenches for polymer insertion [12]. The second scheme uses conformal coating technology and does not require the extra mask [13]. In the second approach (Fig. 13), a highly conformal dielectric layer, e.g. parylene ( > 95% sidewall coverage), is deposited over the metal lines. Other vapor depositable low-dielectric- constant dielectrics such as parylene-F (K ,-, 2.3) and poly-naphthalene (K ~ 2.3) may also be used. The thickness of the dielectric is chosen so that it

I:ZJIIZCI"U"~'~ LOW,,K POLYM~Pl ~J, , IPME

(a) m PalWlWk~ fo) ~ Pollmw

t ~ d O o .

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polymer process.

completely fills tightly spaced lines but not wider spaced lines. As the thickness of the dielectric on the top of the metal leads is the same as on the fields, a blanket etchback with endpoint detection leaves low-dielectric-constant polymer only between the tightly spaced leads. The inlaid polymer is then encapsulated with an sin2 overlayer.

Since the interlayer dielectric is still mostly comprised of sin2, the new scheme alleviates many of the integration problems associated with polymers. Parylene-N ( K = 2.7) gapfill reduces the line-to- line capacitance of a 0.65 micron line/spacing from 0.149 fF/mm for plasma SiO2 to 0.103 fF/mm, which is a 30% improvement in the line-to-line capacitance. As the total capacitance is dictated by the line-to-line capacitance at deep submicron regions, the insertion of low-dielectric-constant polymers can provide a dramatic reduction in the total capacitance in the new

II

5

4

$

3

1

TOTAL CAPACITANCE

0.1 0.$ O.S 0.7 O.g Metol Vvk:rdv'Sm=~g (p,m)

Fig. 14. Interconnect capacitance as a function of the dielectric constant of gapflll material (1 micron thick top

and bottom sin: and 0.7/zm thick metal lead).

MOS technology in the ULSI era 1307

10"~ I

a x

4 I

2 0,1

TOTAL DELAY

i,. ~ . . . ~.....~ - , - - - - . ~ . : : . . : . ..: . . . . . . . s o . : : .....

Metal Wid~'VSpactng (~m)

Fig. 15. Theoretical delay time of a 2000-micron-long metal line as a function of the dielectric constant of gapfill

material.

interconnect structure (Fig. 14). Figure 15 shows the theoretical improvement in delay times as a function of the dielectric constant of embedded polymers.

3. CONCLUSION

Electronic devices are going through a major revolution and reaching yet another level of miniaturization. This trend in miniaturization will continue well into the next century, and pose many challenges in the areas of device and inter- connects. The demand for higher performance transistors at lower voltages will require a very careful optimization of all aspects of a device

simultaneously. The interconnect is beginning to be the speed bottleneck and a reduction in the parasitic capacitance will not only help the speed, but also reduce the power dissipation and the cross-talk. Also, as we scale the geometries further towards 0.1 #m, the limits of optical lithography, etch, deposition, planarization and wafer clean technologies will be pushed further. Moreover, in the deep submicrocom- puter region the process and device parameters will require much tighter distribution. Automatic real time process control will be critical to high volume manufacture of devices at these feature sizes.

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2. Shahidi, G. G. et al., IEEE EDL, 1993, 14(8), 409. 3. Andoh, T. et al., IEDM, 1994, 79. 4. Hisamoto, D. et al., VLS1 Tech., 1995, 115. 5. Rodder, M. et al., IEDM, 1994, 71. 6. Rodder, M. et al., IEDM, 1993, 879. 7. Mii, Y. et al., VLSI Tech., 1994, 9. 8. Boulin, D. M. et al., VLSI Tech., 1995, 65. 9. Koga, J. et al., IEDM, 1994, 475.

10. Monk, D. and Soan, D. Polymer for Electronic and Photonic Applications, ed. C. P. Wong. Academic Press, 1993, p. 120.

11. Pintchovski, F. IEDM Tech. Dig., 1994, 97. 12. Jeng, S., Chang, M., Kroger, T., McAnally, P. and

Havemann, R., Symp. VLSI-Technol. Dig., Technical Papers, Honolulu, Hawaii, 7-9 June 1994, 73.

13. Jeng, S., Chang, M., Ting, L., Taylor, K., Lee, C., McAnally, P. and Havemann, R. H. Int. Syrup., VLSI-Tech. Systems Appl. Proc. Technical Papers, Taipei, Taiwan, 31 May-2 June 1995 p. 164.