Modeling the effect of non-idealities on III-V/Si and …...1 Modeling the effect of non-idealities...

1

Modeling the effect of non-idealities

on III-V/Si and All-III-V TFETs

S. Sant, M. Luisier, and A. Schenk

Outline

• Energy scaling and Need of Steep Slope FETs

– Can Tunnel FETs compete with MOSFETs?

• Analysis of InAs/Si Tunnel FETs

– Modeling non-idealities such as channel quantization, traps in TCAD

– Impact of non-idealities on TFET characteristics

– Trap-tolerant TFET geometry

• TCAD modeling of InAs/InGaAsSb Tunnel FETs

– Composition and strain variation in the nanowire

– Simulation results of TFET

– Effect of traps

• Conclusions

2

Outline










– Effect of traps

• Conclusions

3

Energy Scaling and Need of Steep Slope FETs

4

𝑃𝑠𝑡𝑎𝑡𝑖𝑐 = 𝐼𝑜𝑓𝑓 ⋅ 𝑉𝐷𝐷

0 VDD’ VDD

Ic

Ioff

𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = 𝐶 ⋅ 𝑉𝐷𝐷2 ⋅ 𝑓

• To lower dynamic power, scale VDD

• Lowering VDD increases static power

• Solution: steep slope devices –Tunnel FETs

• Problem: low IDS of Tunnel FETs

High IDS as well as SS < 60mV/dec needed

𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 =Τ𝐼𝐷𝑆 𝑉𝐷𝐷

𝐶𝑎𝑝𝑎𝑐𝑖𝑡𝑎𝑛𝑐𝑒

Outline










– Effect of traps

• Conclusions

5

Experimental (IBM Zürich)*

Simulated§

• Working principle of a Tunnel FET

– Band-to-band generation of e-h pairs

– Gate control over the generation rate

• Non-idealities severely degrade

performance of Tunnel FETs

6

Non-idealities in a Tunnel FET

*Cutaia et. al. J-EDS 2015§Schenk et. al. ULIS 2016

n+ In

As

i-Silicon

Gate

Source

Drain

2. Surface roughness

1. Channel quantization

3. Band tail states

4. Interface traps

§

• Delay in the onset of line tunneling.

• Reduced tunnel rate – lower field, longer tunnel path,

and modified transition matrix element (not modeled)

• Modeled with path rejection method* – implemented in

TCAD simulator using nonlocal PMI

7

Oxi

de CB

VBFirst subband level

Inactive tunnel paths

n+ In

As

i-Silicon

Gate

Source

Drain

Channel Quantization

CB

VB

E0

✓

X

Oxi

de

InAs

*

*W. Vandenberghe et. al. SISPAD 2011, 271.

8

n+ In

As

i-Silicon

Gate

Source

Drain

Trap-assisted tunneling in Vertical InAs-Si TFETs

EV EC

1x1013 cm-2eV-1 (from exp.)*

*Taken from – Mensch et. al., IEEE Nanotect., vol 12,3, 2013. and Cutaia et. al. J-EDS 2015

Sub-band

Bulk InAs

Gat

e o

xid

e

InAs/oxide interface traps

CB

VB

Multi-phononexcitation

Tunneling

CB

VB

SiliconInAs

Traps at InAs/Si interface

Tunneling Tunneling

EV EC

1x1013 cm-2eV-1

FWHM = 220 meV

9

Model parameters• Work function 4.9 eV

• Channel quantization modeled using path rejection method

• Band-to-band tunneling

Nonlocal BTBT model was used

InAs: mC = 0.023, mV = 0.026

Silicon: mV,LH = 0.15

• Trap-assisted tunneling

• Nonlocal TAT model was used

• e, h effective masses in InAs and Si - same as for bulk

• S = 3.0 and hω = 0.06 eV

• VT= 50 Å3 (InAs/Si)

• VT = 10 Å3 (InAs/Oxide)

• Multi-phonon excitation process

• σ = 10 Å2 (for both Si and InAs)

• vth = 2.04x107 cm/s (Si) and 7.57x107 cm/s (InAs) – temperature-dependent

10

Vertical nanowire TFETs

▪ Diameter = 100 nm

▪ i-Si channel length= 100 nm

▪ Doping = 2x1018 cm-3

*

*Expt data from Cutaia et. al. J-EDS 2015

SS=157mV/dec

SS =103mV/dec

No traps

With traps

T = 300K

With quant.

Without quant.

T = 300K

Effect of channel quantization and traps

• Current degradation observed

experimentally could be attributed

to channel quantization

• Trap-assisted tunneling degrades

SS

11

Individual contributions of TAT mechanisms

• Both trap densities need to be suppressed to

achieve improved performance

12

InAs/oxide traps

InAs/Si traps

Both + BTBT300K

SiliconInAs

Tunneling Tunneling


InAs

Oxi

de

Tunneling

13

Maximum allowable Dit in Vertical NW TFET

• Active trap density - Dit < 5x1011 cm-2eV-1 is necessary to achieve sub-

thermal SS

300K

Scaling of Radius

Solid: IdVg for R=50nm, and 10nm at InAs/oxide Dit=1e13eV-1cm-3 and InAs/Si peak Dit=1e13eV-1cm-3

Sub-band

Bulk InAsG

ate

oxi

de


CB

VB


Tunneling

TAT Active for R=50nm

n+ In

As

i-Silicon

Gate

Source

Drain

R = 50 nm

Inhibition of Oxide TAT

Solid: IdVg for R=50nm, and 10nm at InAs/oxide Dit=1e13eV-1cm-3 and InAs/Si peak Dit=1e13eV-1cm-3

Sub-band

Bulk InAsG

ate

oxi

de


CB

VB


Tunneling

TAT Active for R=50nm

n+ In

As

i-Silicon

Gate

Source

Drain

R = 10 nm

Effect of both gate-alignment and

diameter scaling

Effect of reduction in nanowire radius as well as gate-alignment

• Band-to-band tunneling

“advances” to a lower bias

• Elimination of the leakage

floor

n+ In

As

i-Silicon

Gate

Source

Drain

Conclusions – I

• Trap-assisted tunneling degrades slope of InAs/Si TFETs.

• Channel quantization degrades the on current of the TFETs.

• Diameter scaling and gate alignment can yield steep slope InAs/Si

TFETs even in the presence of traps.

17

Outline










– Effect of traps

• Conclusions

18

Device Design

19

All-III-V Tunnel FET by Lund university

Diameter = 20 nm

65

nm

10

5 n

m

Composition and Strain Dependence

• Composition dependence of InGaAsSb is calculated using Adachi’s formula for

quaternary alloys

• Shift in the band edges due to strain is calculated by Van de Walle’s theory

• All the quantities required to model band-to-band tunneling are extracted from

experiments – minimal fitting

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Trap distributions

• In InAs, the energetic trap

distribution was clipped off at the

band edges.

• Fitting parameters –

– Trap interaction volume

– Trap energy level in R-1

InAs/Oxide trap distribution

EV EC

1.6x1018 cm-3eV-1

Bulk-traps in In1->0.7GaAs1->0.84Sb (R-1)

100meV

Simulation Results

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• I-V plots are weakly temperature dependent (except for linear variation of

the work-function)

• Confirms that TAT at oxide interface is absent

Weak T-dep.

Effect of Bulk Traps – TAT

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• TAT in InGaAsSb region R-1 degrades the swing and off-state leakage

• TAT absent at oxide/InAs interface because of absence of triangular well

No TAT at oxide/InAs interface

TAT only at InGaAsSb region R-1InGaAsSb

Effect of Bulk Trap – Variability in Swing

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• Uniform bulk trap cannot capture variability due to random placement of traps.

• 3D simulations => variations of location of the trap within R-1 change the swing.

• Explains experimentally observed variability in these TFETs*

ID-VG plots with trap at different location

InG

aAsS

bIn

As-

WZ

Source

Drain

Gat

e

Single trap

Radius = 10nm

*Memisevic et. al. Trans. Electron Devices 2017.

Effect of Oxide Traps – VTH Shift

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• Traps at oxide/InAs interface degrade the swing by electrostatic screening

• Variation of VTH due to oxide/InAs traps is captured in our simulations

• Varying VDS changes Fermi level in InAs channel => trapped InAs/oxide

interface charge density changes => VTH changes

ID-VG plots for different VDS

Negative Transconductance

• Negative transconductance observed in the experimental transfer

characteristics – is correctly produced in simulations.

• Reason – shift in the location of band-to-band tunneling from hetero-

junction to the start of the gate

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Outline










– Effect of traps

• Conclusions

27

Conclusions – II

• Traps affect subthreshold swing of All-III-V TFETs as well.

• Still, all-III-V nanowire TFETs can deliver high on-current as well as

steep slope.

28

Thank you!

Questions?

29

30

Modeling trap-assisted tunneling• Capture rate for multi-phonon excitation process (local) -

where

• Capture rate for non-local direct tunneling process -

WKB factorDOS factor Occupation factor

• Capture rate for non-local phonon-assisted tunneling process -

Bulk InAs

oxi

de

CB

VB

Multi-Phononexcitation

Sub-band

Tunneling

*Synopsys Inc. Sentaurus Device User Guide.

Can Tunnel FETs compete with MOSFET

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𝑃𝑠𝑡𝑎𝑡𝑖𝑐 = 𝐼𝑜𝑓𝑓 ⋅ 𝑉𝐷𝐷

𝑃𝑑𝑦𝑛𝑎𝑚𝑖𝑐 = 𝐶 ⋅ 𝑉𝐷𝐷2 ⋅ 𝑓

• To lower dynamic power, scale VDD

• Lowering VDD increases static power

• Solution: steep slope devices –Tunnel FETs

• Problem: low IDS of Tunnel FETs

𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 =Τ𝐼𝐷𝑆 𝑉𝐷𝐷

𝐶𝑎𝑝𝑎𝑐𝑖𝑡𝑎𝑛𝑐𝑒

Memisevic 2017InAs/InGaAsSb

High IDS as well as SS < 60mV/dec needed

2014

2017

2016

Modeling the effect of non-idealities on III-V/Si and …...1 Modeling the effect of non-idealities...

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