800 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 5 , MAY 1996

odeling and Characterization of Electro irectional Curre

Jiang Tao, Jone F. Chen, Nathan W. Cheung, and Chenming Hu, Fellow, IEEE

Abstract-Electromigration reliability of different metallization systems (A1-2%Si, AI-CuITiW, Cu, and TiNIAL2%SilTiN) and structures (Al-via and W-plug) under bidirectional current stress has been studied in a wide frequency range (from mHz to 200 MHz). The experimental results show that at low frequency, the damage healing factor and lifetime under ac stress increases with frequency. At very high-frequency regions, the pure ac lifetime was found to be determined by the thermal process (caused by asymmetrical geometry, etc.) instead of electromi- gration. All the observations are in agreement with an average current model.

I. INTRODUCTION

NTERCONNECT failure as a result of electromigration is one of the main IC reliability concerns. The continuing

trend of scaling-down feature sizes on chips has exacerbated this problem. The electromigration lifetime under dc stress is routinely measured to support new metallization process development as well as to monitor an existing process. The measured dc lifetime is the only link between process technol- ogy and circuit design with respect to reliability of the met- allization material. As many interconnects carry bidirectional currents, it is essential to assess the reliability of a metallization system under ac stress conditions. Electromigration reliability of interconnects under bidirectional (ac) current stress is also an important reliability concem in the development of high- speed ULSI CMOS IC’s. In low-power and high-speed CMOS IC designs, circuit designers must minimize the parasitic capacitances to reduce power consumption and improve circuit speed. As device sizes scale down into deep submicron region, the parasitic capacitance of interconnects becomes dominant [l]. The capacitance of these lines directly affects circuit speed and may seriously limit future system speed. Therefore, reducing the width and height of interconnects that carry bidirectional current, such as clock and signal lines, is very beneficial. In this paper, electromigration failure under ac stress is studied. Experiments have been carried out to charac- terize the electromigration reliability of different metallization systems (AI -2 %Si , Al-4 % Cu/Ti W, Cu , and TiN/A1-2% S i/TiN) and structures (Al-via and W-plug) under ac stress in a wide

Manuscript received August 25, 1995; revised November 15, 1995. The

J. Tao is with Siliconix, Inc., Santa Clara, CA 95056 USA. J. F. Chen, N. W. Cheuug, and C. Hu are with the Department of Electrical

Engineering and Computer Sciences, University of Califomia, Berkeley, CA 94720 USA.

review of this paper was arranged by Editor C.-Y. Lu.

Publisher Item Identifier S 0018-9383(96)03380-1.

I 5 10 20 304050607080 90 95 99

Cumulative Failure Percent(%)

Fig. 1. Log-normal plot of cumulative failure rate under dc and ac stress for Al-2%Si, A1-4%Cu/TiW, and Cu interconnects with J p e & = 1.5 x lo7 Ncm2 and T = 250OC.

range of frequencies (from mHz to 200 MHz). Based on the experimental results, a damage healing model is developed. The damage healing effectiveness is studied as a function of current density and stress current frequency. The failure mechanism under high-frequency pure ac is also discussed.

11. PURE AC STRESS

A. Experimental Results

The samples used in this study (A1-2%Si, Cu, Al- 4%Cu/TiW, TiN/Al-2%Si, Al-via, and W-plug) have been described elsewhere [2]-[5]. A current source regulated by a transistor and driven by the output of a TTL gate was used to generate the ac signals [6]. Electromigration tests were performed on wafers placed directly on a heated stage of a probe station. The median-time-to-failure (MTTF) was determined by fitting the failure data to a log-noma1 distribution.

The lifetime under pure ac stress (i.e., lJ+(k)I = IJ-(t)I, where J+ ( t ) and J- ( t ) are the current densities in the positive and negative cycles of a period) has been found experimentally to be much longer than the dc lifetime [3]-[lo]. Figs. 1 and 2 show the comparison of electromigration lifetimes under ac and dc stresses for interconnect lines and W and Al-via structures. ac lifetimes are orders of magnitude longer than dc lifetimes for every material and structure studied here under

~ _ _ _

0018-9383/96$05.00 0 1996 IEEE

TA0 et al.: MODELING AND CHARACTERIZATION OF ELECTROMIGRATION FAILURES 801

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...... .t ........

I P - Bipolar Stress

w-plug 0 AI-via

0.11 I I I I i ' I I I I I 5 10 20 304050607080 90 95 99

Cumulative Failure Percent(%)

Fig. 2. w and ~ l . ~ i ~ structures with J~~~~ = 1.5

Log-normal plot of cumulative failure rate under dc and ac stress for 107 ~ / ~ ~ 2 and T = 2 5 0 0 ~ . Fig. 4.

the W-plug structure. Via resistance change versus stress time under dc and ac stresses for

Cu line

275OC, J=1 .5x107A/cm2

10-1 10-1 100 10' 10' 1 o3

Time(hour)

Fig. 3. stresses for Cn interconnects.

Normalized resistance change versus stress time under ac and dc

the test conditions. Figs. 3 and 4 show the resistance change under dc and ac stress conditions for interconnect line and via structure. The resistance gradually increases with stress time under dc stress, while under ac stress the resistance is very sta- ble even after stress for hundreds of hours. To understand and explain electromigration failures under bidirectional current stress, experiments under very low-frequency bipolar current stress were carried out to demonstrate the electromigration damage-healing effect due to current reversal as shown in Fig. 5 for Al-2%Si interconnects. We can see during the first half-cycle (positive current stress), a large detectable rise in resistance was created. During the following negative half- cycle, some of the damage induced in the first half-cycle has been healed due to current reversal, and the resistance decreased. The stress cycles caused the resistance to rise and fall, with a continuously increasing average resistance value, due to incomplete healing. A similar phenomenon was observed in the Cu interconnects, TiW/Al-4%Cu/TiW multilayered interconnects as well as in the W-plug structures, as shown in Figs. 6 and 7. For W-plug via structure, the decrease in average resistance may be caused by additional

1.04

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5 1.02

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healing or annealing effects at the W/TiW/A1-4%Cu interfaces when a high current density passes through the via area. When the stress current frequency was increased, similar resistance variation behavior was observed as shown in Fig. 5 (period = 0.5 h). However, the damage induced during each half-cycle is much smaller and the damage healing by the opposite-flowing current is more nearly complete than in the low-frequency case. Therefore, the average value of resistance increases more slowly. Fig. 8 shows the resistance change versus stress time under DC, low-frequency and high-frequency ac stresses for A1-2%Si interconnects. The resistance increases monotonically with stress time for the dc case. Under low-frequency ac stress, the resistance rises and falls with stress time with a continu- ously increasing background. However, under high-frequency ac stress, the resistance remains essentially constant. A similar result was observed in W-plug via structures as shown in Fig. 9. At very high frequencies, there is little change expected in grain boundaries or vacancy density during each half- cycle, therefore the vacancy motion can be almost completely reversed in the following opposite half-cycle. Based on these experimental results, it is seen that a higher stress frequency results in more nearly complete healing during consecutive current pulses of opposite polarity.

so2

1.010

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 5, MAY 1996

. Forward Reverse Forward Reverse

- Bipolar Stressing /#”

0 1 2 3 4 5 Time(hour)

Normalized resistance change versus stress time for Cu interconnects Fig. 6. under low-frequency bipolar current stress.

1.008 Bipolar Stress

1 Forward I Reverse I Forward I Reverie -7 0 1 2 3 4

Stress Time(hour)

0.994

Fig. 7. Normalized resistance change versus stress time for both TiW/Al-4%Cu/TiW and W-plug structures under low-frequency bipolar current stress.

3.0

-4 2.0

1.5

1 .o

10-2 i o - ’ 1 oo IO‘ IO‘ Stress Time (hour)

Fig. 8. Normalized resistance change versus stress time for A1-2%Si inter- connects under dc, low-frequency, and high-frequency bidirectional current stresses.

B. Damage Healing Model

Figs. 10 and 11 show electromigration lifetimes of A1-2%Si and Cu interconnects under pure ac stress versus stress signal frequencies. The most striking behavior is the linear rise of MTTF with ac repetition frequency over several orders of

2 0

1 .a

1 6

1.4

1 .o

0.8

0.6

10’’ 10-1 100 IO’ 1 o2 I o3 Stress Time (hour)

Fig. 9. Normalized resistance change versus stress time for W-plug structures under dc, low-frequency, and high-frequency bidirectional current stresses

i o 4

i o 3

10‘

E Pure AC Stress

f, e .

a g 10‘ J,,,,=l .5x107A/cmZ

U J,,,=8 6x106A/cm2 U +

Model -

10-l

1 o-2 1 0 - ~ 1 0 - ~ 1 0 - ~ 1 0 - ~ i o o i o 1 io‘ 103 104 105 106 107 IO* 109

Frequency(Hz)

Fig. 10. The solid line shows the prediction of the damage healing model.

Frequency dependence of ac lifetime for Al-2%Si interconnects

magnitude frequency range. When the ac stress frequency f < ~ / ~ M T T F D ~ as shown in Fig. 10, metal lines fail before the end of the first half-cycle. Naturally, in those cases, the MTTF is simply equal to the dc lifetime, and is independent of frequency.

In the region where f > ~ / ~ M T T F D ~ , the frequency dependence of electromigration lifetimes under bidirectional current stress has been found to follow the model [2]

TTF,, = 2f x (TTFDc)’. (1)

The calculated results are shown in Figs. 10 and 11 as solid lines. The figures show that the model agrees with experimen- tal results well.

The median-time-to-failure (MTTF) under dc stress is well characterized and usually presented in Black’s equation [ 113

A (2)

where A and n are constants, Ea is the activation energy, and T is the interconnect temperature. The value of n, which is typ- ically 2, is larger at high stress current densities. Substituting

TTFDc = -eEa/kT J&

TA0 et al.: MODELING AND CHARACTERIZATION OF ELECTROMIGRATION FAILURES 803

lo-'

1 o4 AC Stressing

0 J=l .5x107A/cm2 !d - Model

i o 7 E I

in0 t I "

1 06 1 o7 1 08 Current Density(A/cm*)

Fig. 12. Current density dependence of ac and dc lifetimes for AI-2%Si interconnects, showing stronger dependence of ac lifetime on current density.

( 2 ) into (l), we have

f TTF,, = 2f x (TTFDC)' K - exp(2E,/kT). (3)

From (3), it is seen that the current exponent and the activation energy for ac lifetime are twice those of the dc lifetime, as verified in Figs. 12 and 13. In the current density range used in these tests, n was found to be 3.3 and E, = 0.41 eV under dc stress. The current density exponent and effective activation energy were found to be about 6.8 and 0.8 eV, respectively, under ac stress. These values are precisely twice those found in the dc case.

The fact that the MTTF,, is shorter at lower frequency is believed to be due to a decrease in the effectiveness of damage healing by the current pulse in the opposite direction during the second half-cycle of pulsing. This decrease is due to significant changes in properties like grain boundaries and void sizes, which may have occurred between the onset of the positive current pulse and the onset of the negative pulse. When both dc and ac signals are present, Ting et al. [8] have shown empirically that

52"

A eEa/kT MTTF,, = - (J+ - yZ)" (4)

i o 5

i o 4

10' . ' . ' ' ' ' ' ' I ' ' ' I 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5

1OOOTT (K)

Fig. 13. Arrhenius plot of MTTF versus 1000/T(Ii) under dc and pure ac stresses for A1-2%Si interconnects, showing higher activation energy for ac electromigration process.

3 0.8 U) U) 0

0.6

5 0.4

.- c 0 aJ

E

m .- - 2 0.2

/

DF=50%

-Model, n=3.3

0 Jpe,,=8.0x1 06A/cm*

Jpeak=l 5x1 07A/cm2

A J,,,,=4.5x107A/cm2

i o ' i o 2 i o 3 i o 4 i o 5 i o6 l o 7 i o8 i o 9 f 1 f,

Fig. 14. AI-2%Si interconnects under different stress conditions.

Frequency dependence of ac damage healing effectiveness (y) for

where & and are the average absolute-values of current densities during positive and negative pulses. y is the ac damage healing effectiveness. Assuming (4) is correct, the dependence of y on f can be modeled by equating (4) and (1) for the case of pure ac stress, with = = D G and the duty factor D =50%. One can find

I ,. , l l n

y = 1 - 2 [ 3

and

where f 2 f o . In the low-frequency region (f < f ~ ) , TTF,, = TTFDc and y = 0. As the repetition frequency f increases (f > f o ) , y also increases, and when f + oc), y + 1 and MTTF,, + 00 according to (5 ) . Fig. 14 compares (5) with experimental data. We can see the model agrees with experimental results reasonably well. Further study is needed to verify the effect of f 0 , the frequency below which the ac lifetime is equal to dc lifetime, on y.

804

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9.

a Y Independent of frequency

Al-P/&i line T=250°C

J,=J.=4.5x1O7A/cm2 Experimental Data

- Model

i o 2 IO-' loo 10' i o z i o 3 104 105 i o 6 i o 7 i o 8 109

Frequency (Hz)

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 5, MAY 1996

: transition : ' X

: transition :

Fig. 17. Illustration of the temperature profile along a thin metal interconnect caused by joule heating and enhanced heat dissipation near the ends of Stripe. Fig. 15. Frequency dependence Of lifetime for A1-2%Si interconnects

under Jpeak = 4.5 x i o 7 A/cm2.

Fig. 16. connects under ac stress.

Optical micrography shows the failure location for A1-2%Si inter-

C. Failure Mechanism Under High-Frequency Pure AC Stress

The previous section showed that when the stress current frequency is high enough (f > 1 kHz ), the damage healing factor y z 1, and the MTTF,, + 00 for pure ac stress. This means under very high-frequency ac stress, electromigration due to pure ac current stress will not be a major reliability con- cern, and the ac signal lines can be designed more aggressively to achieve greater circuit speed and power performances. However, the severe joule-heating that accompanies a very high current density may set limitations on interconnect design rules. As shown in Fig. 15, when the peak current density was increased to 4.5 x lo7 A/cm2, metal line failures were observed after 20 min of stressing even when the ac stress current frequency was tens of MHz. Examining the failure locations by microscope, the damage was always found at the transition region between wide contact pads and narrow test lines, occurring randomly at either the anode or cathode pad as shown in Fig. 16. For dc tests under the same stress conditions, failure locations were randomly distributed along the test lines.

This observation suggests that the thermal gradient at the line- to-pad transition region is the cause of high-frequency ac stress failure. The phenomenon can be explained by the following model. Including the thermal effect, the atomic flux moving along the grain-boundary during stress can be written as

N D k T F = Fern f Ftherm = -(fern + ftherm) (7)

where N and D are the metal ion concentration and diffusion constant, and fern and ftherm are the electrical and thermal forces acting on the metal ions, respectively. The temperature of interconnects subject to high current density stress is generally increased because of joule heating. A temperature profile along a test stripe is often observed as shown in Fig. 17 [12]. In temperature gradients, atoms can migrate either to cold part or to hot part, depending on the material [13], [14]. When atoms migrate from cold to hot region (as in Al-based alloys), failure will eventually occur and cause a discontinuity. Under dc stress, the lifetime is determined by both electromigration and thermal processes; thermotransport due to a temperature gradient is generally a second-order effect, so the lifetime is dominated by electromigration. In this case, the failure locations should be randomly distributed. Under bidirectional current stress, the atomic flux induced during each half cycle is

N D F+ = + f,',,,,,

during the positive half-cycle and

during the negative half-cycle. (8)

According to (5), when the repetition frequency f is high enough, the damage healing factor y + 1, therefore fem = 0, as fe+m = - On the other hand, the thermal force, ft',,,, and ftTerm, is not directional, it does not change its direction when the stress current reverses polarity. So the atomic flux under ac stress is

F = F + + F -

TA0 et al.: MODELING AND CHARACTERIZATION OF ELECTROMIGRATION FAILURES

AI layer thickness=O.$m SO, layer thickness=O.O$m

400

350 1 Contact pad

~

805

-

300

250

o 200

-

-

-

test stripe

x=o

/ ,i Jd3 .5~1 07A/cm2

I I

0 1 2 3 4 Distance From the Contact Pad X (pm)

Fig. 18. Simulated temperature profile along a metal stripe.

and

where E, is the activation energy of the diffusing species along the grain-boundary. According to Shirley [ 121, the temperature profile along the test stripe is given by

+ Tj(2)] - Ti

x Cosh(X/X)/Cosh(L/2X) 1 + i[Tj(l) - T3(2)]Sinh(X/X)/Sinh(L/2X) (11)

where AT(X) = T ( X ) - T, and T, is the substrate tem- perature, i.e., A T ( X ) is the temperature rise above substrate temperature; T3 (1) and T3 (2) are the temperature rises at both ends of the metal stripe; The metal stripe length is L and 5

is measured from the center of the stripe; Ti = J2psX2 /K and J is the current density pass through the test line, ps is the metal resistivity at temperature T,, K is the thermal conductivity of metal line and X is defined as follows:

where n is the thermal conductivity of SiOz; t , and tsioa are the thickness of metal and Si02 layers; /3 is the thermal coefficient of resistance (TCR) for metal; po is metal resistivity at 0°C and S is the parallel-plate capacitor fringing correction factor, which is dependent on metal line width and relative thickness of metal and dielectric and can be found from the figure shown in reference [ 121. For simplicity, assuming the two contact pads of the metal stripe are two infinity large heat sinks, and the temperatures at both ends of the stripe are equal to the substrate temperature, i.e., T’(1) = T,(2) = 0. Therefore, (1 1) can be simplified as follows:

A T ( X ) = T, - T, C O S ~ ( X / X ) / C O S ~ ( L / ~ X ) (13)

and

180 AI layer thickness=O Wm .

S O , thickness=O 0Wm contact pad L=200pm, W=@m

0 7 0 1 2 3 4

Distance From the Contact Pad X @m)

Fig. 19. Simulated thermal gradient profile along a metal stripe.

Combining (lo), (13), and (14), the ac lifetime can be written as

where A,, is a constant determined by metal material proper- ties, microstructure of the metal line, temperature, test condi- tion, etc.; T, is the substrate temperature and 0 J 2 attributes to self-joule heating as metal line pass through current. Figs. 18 and 19 show the simulated temperature distribution and ther- mal gradient along a metal line during test. At the transition region, the thermal gradient reaches its maximum value as shown in Fig. 19; therefore, the failure location is expected near the transition region, in agreement with the experimental results. Beside the transition region, any location of thickness variation in thin metal films can also induce a thermal gradient, and affect the ac lifetime.

111. GENERAL AC STRESS

In real circuit applications, bidirectional current signals are usually not pure ac waveforms, instead are general ac waveforms (i.e., IJ+(t)I # IJ-(t)J). Assume IJ+(t)J > IJ-(t)l and define JDC as

(16) ~~

JDC = lJ+(t)l - IJ-(t)l.

In the following experiments, we use a rectangular pulse, Jpeak as L ( t ) and J+(t) is a rectangular pulse of height Jpeak + &c. Fig. 20 shows the lifetime distributions for Al- 2%Si interconnects under dc and general ac stresses. The general ac waveform consists of a dc bias (JDC = 1 x lo6 A/cm2) and a pure ac signal (frequency f = 10 MHz, duty factor D =50% and .Jppeak = 1 x 106,6 x IO6, and 2 x lo7 A/cm2, respectively). The ambient temperature was adjusted in order to keep the stress temperature (ambient temperature + self-joule heating temperature) equal under different current density stresses. As we have expected from the discussions of the above section on pure ac stress, the general ac lifetime is determined by the dc bias, and is not affected by the 10 MHz pure ac signal even though the pure ac peak current density

806

h l o

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 5, MAY 1996

. E DC, JDc=l 0x106A/cm2 0 Pure AC(J,,,,=i .0xi06Afcm')+DG(JDc=i .0x106A/cm2)

[ A Pure AC(J,,,,=~.OX~O~A/C~~)+DC(J,~=~ .0x106A/cm2)

f. 2 a - .- m

1:

i=

n i

A

-. . 1 2 5 10 20 30 405060 70 80 90 95 98 99

Cumulative Failure Percent (%)

Fig. 20. Log-normal plot of cumulative failure rate under dc and gen- eral ac stresses for A1-2%Si. The general ac signal consists of a dc bias ( J D ~ = 1.0 x l oG A/cm2) and a pure ac signal (Jpeak = 1.0 x A/cm2. 5.0 x l o 6 A/cm2, 2.0 x l o7 A/cm2, respectively), and T = 250OC.

6

5

4

h

Pure AC, J ~ ~ ~ ~ = I .ox106 ~ c m ' % 2 -

I , , , , ~ , , I , ~ , ~ , ~ ~ , , , , ~ .

0 2 4 6 8 10 12 14 16 18 20 22 24

Time (hour)

Fig. 21, signal off and pure ac stress cases.

Resistance change versus time for A1-2%Si interconnects for stress

varies from 1 x lo6 to 2 x lo7 A/cm2. The general ac lifetime is just equal to the dc lifetime determined by the dc bias.

The effects of pure ac stress on the metal lines that have pre-exist voids were also investigated. First we intentionally introduce some voids in the metal lines by stressing the sam- ples under dc signal and monitor the test metal line resistance change using Kelvin structure. After the resistance change (A RI&) reaching certain level, which corresponds to certain void levels in the metal line, we either switch the dc signal to a pure ac signal or simply turn off the power and monitor the resistance change versus time. Fig. 21 shows the resistance change (ARIRo) versus time after 5% resistance increase has been induced by dc stress. We can see the resistance shows the similar relaxation characteristics under both cases, and no additional effects were observed when a pure ac signal was applied. The resistance relaxation phenomenon has been reported by Lloyd et al. [15], and has been attributed to the stress relaxation as electromigration process induces considerable stress [ 161. This resistance relaxation process is strongly dependent on temperature. As shown in Fig. 22, the metal line was first stressed under a dc signal, after

6 DCi DC Power off

0 2 4 6 8 10 12 14 16 18 20 22 24

Time (hour)

Fig. 22. Resistance change versus time under different temperatures for AI-2%Si interconnects after stress current was turned off

10-1 1.7 1.8 1 9 2.0 2.1 2.2

lOOO/T (K)

Fig. 23. AR/Ro = 4%.

Arrhenius plot for the resistance decay from AR/Ro = 5% to

5% resistance increase was detected, the stress current was turned off, and the resistance change was monitored under different ambient temperatures. The resistance showed almost no change when the ambient temperature was kept at 3OoC, while it showed rapid decay at high temperares. The higher the ambient temperature, the faster the relaxation. Fig. 23 shows the Arrhenius plot of the resistance relaxation process, the decay time was determined as the time for resistance to relax from ARIRo =5% to ARIRo =4%. The activation energy was found to be 0.41 eV, which is equal to the electromigration activation energy (-0.41 eV) for A1-2%Si interconnects shown in Fig. 13. Fig. 24 shows the resistance change after 5% resistance increase has been induced by dc stress. The dc signal was either switched to a pure ac signal or simply be turned off. The peak current density of pure ac signal was either 1.0 x lo6 Akm2 or 1.0 x lo7 A/cm2. We can see the resistance decays faster for higher pure ac peak current density, which can be attributed to higher self-joule heating. The resistance change versus stress time under pure ac stress for different pre-existing void levels induced by dc stress (the resistance changes are 2%, 5%, and 8%, respectively) is shown in Fig. 25. We can see the metal line resistance still shows the similar relaxation characteristics even if the pre-existing

TA0 ef al.: MODELING AND CHARACTERIZATION OF ELECTROMIGRATION FAILURES

~

807

fi

- 12: s i

ff

I Pure AC, J,,,,=I .ox1o7 A/cm‘

0 2 4 6 8 10 12 14 16 18 20 22 24

Time (hour)

Fig. 24. Resistance change versus time for A1-2%Si interconnects for stress signal off and pure ac stress cases, the peak current density of pure ac signal was either 1.0 x lo6 A/cm2 or 1.0 x lo7 A/cm2.

DC i Pure AC, J,,,,=l .0x106 Ncm’ +: -c

0 l: 0 2 4 6 8 10 12 14 16 18 20 22 24

Stress Time (hour)

Fig, 25. Resistance change versus time under pure ac stress (Jpeak = 1.0 x lo6 A/cm2). The pre-existing voids have been induced by dc stress (AR/Ro = 2%, 5% and 8%, respectively).

void levels are different. Fig. 26 shows the general ac lifetime dependence as a function of the stress signal frequency in a wide frequency range (from mHz to 200 MHz). The general ac waveform consisted of a pure ac waveform (peak current density Jpeak = 1.5 x lo7 A/cm2 and duty factor D =50%) and a dc bias. We can see that at low-frequency region, the lifetime increases as the frequency increases due to damage healing effectiveness (y) increase, which has been discussed in Section 11. At high-frequency range, the general ac lifetime is a constant and equal to the dc lifetime determined by the dc bias. All the above results demonstrated that the general ac lifetime can be modeled by the average current model when the stress signal frequency is high enough (kHz).

IV. SUMMARY

Electromigration failure under bidirectional current stress has been studied. The experimental results show that the electromigration lifetime under ac stress is orders of magnitude longer than the dc lifetime in the frequency range of normal circuit operation and can be projected by the average current model. A damage healing model has been developed. This model has been demonstrated suitable not only for Al-based

10’ c I

Pure AC(J,,=l .5x107Ncm2)+DC(J,,=3.0x106Ncm2)

0 Pure AC(J,,,=l .5x107A/cm2)+DC(J,,=1 .5x1 06nlcmz)

.... MTTFDc(JDC=I .65x1 07Ncm2)

1 0-3 1 0 - ~ 1 0 - ~ i o - ~ ioo i o 1 i o2 io3 i o4 i o 5 i o 6 i o7 i o8 i o 9

Frequency( Hz)

Fig. 26. General ac lifetime as a function of stress signal frequency. The general ac signal consists of a pure ac signal ( ~ ~ ~ ~ k = 1.5 x i o 7 A/cm2) and a dc bias ( J D C = 1.5 x l o 6 A/cm2 and 3.0 x lo6 A/cm2, respectively). At high-frequency regions, general ac lifetime is equal to the dc lifetime determined by dc bias.

interconnects, but also for Cu interconnects and W-plug and Al-via structures. In the very low-frequency region ( f < f o ) , the damage healing factor y = 0, and the ac lifetime is just equal to the dc lifetime. In the median frequency range ( f > f o ) , the damage healing factor increases as frequency increases and the ac lifetime is linearly dependent on the repetition frequency. At a very high-frequency region (> 1 MHz), the damage healing factor y FZ 1, the electromigration- induced damage during the positive half-cycle will be nearly completely healed during the negative half-cycle for the pure ac stress, and the lifetime is determined by the dc bias in the stress signal. The severe self-joule heating caused by the higher current densities and the high thermal gradients caused by asymmetrical geometry or nonuniform metal thin- film thickness will set the real limitations on the ac design rules.

REFERENCES

P. L. Pai and C. H. Ting, “Selective electroless copper for VLSI interconnection,” IEEE Electron Device Lett., vol. 10, p. 423, 1989. J. Tao, N. W. Cheung, and C. Hu, “Modeling electromigration failures in TiN/Al-alloy/TiN multilayered interconnects and TiN thin films,” in Proc. 33rd Int. Reliability Physics Symp., 1995, p. 371. __ , “Metal electromigration damage healing under bidirectional current stress,” ZEEE Electron Device Lett., vol. 14, p. 554, 1993. - , “Electromigration characteristics of copper interconnects,” ZEEE Electron Device Lett., vol. 15, no. 5, p. 249, 1993. J. Tao, K. K. Young, N. W. Cheung, and C. Hu, “Electromigration reliability of tungsten and aluminum vias and improvements under ac current stress,” ZEEE Trans. Electron Devices, vol. 40, no. 8, p. 1398, 1993. B. K. Liew, N. W. Cheung, and C. Hu, “Projecting interconnect electromigration lifetime for arbitrary current waveforms,” ZEEE Trans. Electron Devices, vol. 37, p. 1343, 1990. J. Tao, N. W. Cheung, and C. Hu, “An electromigration failure model for interconnects under pulsed and bidirectional current stressing,” IEEE Trans. Electron Devices, vol. 41, p. 539, 1994. L. M. Ting, J. S . May, W. R. Hunter, and J. W. McPherson, “ac electro- migration characterization and modeling of multilayered interconnects,” in Proc. 3Zth Int. Reliability Physics Symp., 1993, p. 311. J. A. Maiz, “Characterization of electromigration under bidirectional (BC) and pulsed unidirectional (PDC) currents,” in Proc. 27th Znf. Reliability Physics Symp., 1989, p. 220.

808 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 5, MAY 1996

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Jiang Tao received the B.S and M.S. degrees in electrical engineering from Pelung University, Beijing, China, in 1984 and 1987, respectively, and the Ph.D degree in electrical engineenng from University of California at Berkeley, in 1995.

From 1987 to 1990, he was an Assistant Profes- sor and Lecturer in the Department of Computer

nologies, Peking University. He ng Researcher at the Electronic

Research Laboratory, University of California at Berkeley, from 1990 to 1992. He is currently work-

ing at Siliconix, Inc , as a Senior Device and Process Engineer responsible for device and process architect design and development, device characterization, process integration, products yield and reliability improvement.

Jone F. Chen received the B.S. degree in electrical engineering from the National Cheng Kung Univer- sity, Tainan, Taiwan, R.O.C. in 1990 and the M.S. degree in electrical engineering and Computer Sci- ences from the University of California at Berkeley, in 1995. He is presently working toward the Ph.D. degree at the University of California at Berkeley, on modeling and simulation of VLSI reliability.

Nathan W. Cheung received the Ph.D. in applied physics from California Institute of Technology, Pasadena, in 1980.

He is currently a Professor, Department of Elec- trical Engineering and Computer Sciences, Univer- sity of California at Berkeley and Associate Faculty of Lawrence Berkeley Laboratory. Dr. Cheung had held research positions at Exxon Research Labo- ratory, Linden, NJ and Bell Telephone Laboratory, Murray Hill, NJ, and was Visiting Faculty at Na- tional Research Resource for Submicron Structure,

Come11 University, Ithaca, NY. His research interests includes ion-beam technologies, electronic materials, integrated circuit processing, integrated circuit reliability, and thin-film technologies.

Dr. Chung is a member of the American Electrochemical Society, Ameri- can Vacuum Society, Materials Research Society, and the Bohmische Physical Society.

Chenming Hu (S’71-M’76-SM’83-F’90) received the B.S degree from the National Taiwan Uni- versity, R.0.C , and the M S and Ph.D. degrees in electrical engineering from the University of California at Berkeley, in 1970 and 1973, respec- tively.

From 1973 to 1976, he was an Assistant Profes- sor, Massachusetts Institute of Technology (MIT), Cambridge In 1976, he joined the University of California at Berkeley, as Professor of Electrical Engineering and Computer Sciences While on m-

dustrial leave from the university in 1980 and 1981, he was Manager of nonvolatile memory development at National Semiconductor. His present research areas include VLSI devices, silicon-on-insulator devices, hot electron effects, thin dielectrics, electromigration, circuit reliability simulation, and nonvolatile semconductor memories He has also conducted research on electro-optics, solar cells, and power electronics

Dr. Hu has been awarded several patents on semiconductor devices and technology He has authored or co-authored three books and over 400 research papers He has delivered dozens of keynote adresses and invited papers at scientific conferences, and has received many best-paper awards. He is an Honorary Professor of Beijing University and of Tsinghua University, China, and of the Chinese Academy of Science. He has been a Guest Editor of PROCEEDINGS OF THE IEEE and of the IEEE TRANSACTIONS ON ELECTRON DEVICES He serves on an editorial board of Semiconductor Science and Technology, Institute of Physics, England. He was Board Chairman of East San Francisco Bay Chinese School from 1988 to 1991. He received the 1991 Design News Excellence in Design Award and the 1991 Semiconductor Re- search Corporation Technical Excellence Award for leading the development of IC reliability simulator, BERT He received SRC Outstanding Inventor Award in 1993 and 1994