Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

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Model Computer Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU

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Transcript of Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Page 1: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Model ComputerModel Computer

Input/Output

Unit

MemoryUnit

ControlUnit

ArithmeticLogicUnit

Data Bus

CPU

Page 2: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Control UnitControl Unit

Input/Output

Unit

MemoryUnit

ArithmeticLogicUnit

IR

InstructionDecoder

PC

MAR

Page 3: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Memory UnitMemory Unit

Input/Output

Unit

ControlUnit

ArithmeticLogicUnit

MAR

MDR

Address Decoder

MainStore

Page 4: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Arithmetic/Logic UnitArithmetic/Logic Unit

Input/Output

Unit

MainMemory

ControlUnit

ACCSR

Page 5: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Model ComputerModel Computer

ACCSRMDR

Address Decoder

IR

InstructionDecoder

PC

MAR

Page 6: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

RegistersRegisters

A register is a single storage unit where data is stored temporary for a special purpose

MAR holds the address of the memory location to be accessed

MDR holds the data item read from or written to the specified memory location

Page 7: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

RegistersRegisters

PC holds the address of the next instruction to be fetched from the main store

IR holds the current instruction fetched from the main store while it is being decoded

Page 8: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

RegistersRegisters

ACC holds the data item to be processed or the results of the most recent operations in the ALU

SR holds a set of condition flags which describe the status of the most recent operation carried out by the ALU

Page 9: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Programming the CPUProgramming the CPU

00001 : Load the contents in memory location 11111 into the accumulator

00010 : Store the contents in the accumulator in the memory location 11101

Page 10: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Fetch CycleFetch Cycle

0011111101011110

00001

00001

1

01000001

PC is set to 00001 initiallyMAR is loaded with 00001

Page 11: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Fetch CycleFetch Cycle

0011111101011110

00001

00001

1

2

01000001

Address decoder selectsthe memory location 00001

Page 12: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Fetch CycleFetch Cycle

0011111101011110

00001

00001

00111111

1

2

301000001

The instruction in location 00001 is loaded into MDR

Page 13: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Fetch CycleFetch Cycle

0011111101011110

00001

00001

0011111100111111

1

2

3

4

01000001

The instruction is then copied to IR

Page 14: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00010

0011111101000001

5

LDA 00001

PC is set to 00010The instruction is decoded

Page 15: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00010

11111

0011111101000001

5 6

LDA

MAR is set to 11111

Page 16: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00010

11111

0011111101000001

5 6

7

LDA

The address decoder selects the location 11111

Page 17: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00010

11111

0011111101000001

01000001

5 6

7

8

LDA

The data in location 11111 is loaded into MDR

Page 18: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00010

11111

0011111101000001

01000001

5 6

7

8

LDA

01000001

9

The data is then copied to ACC

Page 19: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Fetch CycleFetch Cycle

0011111101011110

00010

00010

1

0100000101000001

Page 20: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Fetch CycleFetch Cycle

0011111101011110

00010

00010

1

2

0100000101000001

Page 21: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Fetch CycleFetch Cycle

0011111101011110

00010

00010

01011110

1

2

3

0100000101000001

Page 22: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Fetch CycleFetch Cycle

0011111101011110

00010

00010

0101111001011110

1

2

3

4

0100000101000001

Page 23: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00011

00010

0011111001000001

5

STA

0011111001000001

Page 24: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00011

11110

0011111001000001

00111110

5 6

STA

01000001

Page 25: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00011

11110

0011111001000001

0100000101000001

5 6

STA

PC

MAR 7

Page 26: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00011

11110

0011111001000001

0100000101000001

5 6

7

8

STA

Page 27: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Execution CycleExecution Cycle

0011111101011110

00011

11110

0011111001000001

0100000101000001

5 6

8

9

7

STA

01000001

Page 28: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

SMC Instruction SetSMC Instruction SetLDA load accumulator with memory

STA store accumulator in memory

ADD add memory to accumulator

SUB subtract memory from accumulator

DEC decrement memory by 1

JMP unconditional jump

BNE branch if negative

STP stop

Page 29: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

SMC Instruction SetSMC Instruction SetLDA LoaD Accumulator with memory

STA STore Accumulator in memory

ADD ADD memory to accumulator

SUB SUBtract memory from accumulator

DEC DECrement memory by 1

JMP unconditional JuMP

BNE Branch if NEgative

STP SToP

Page 30: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Fetch/Execution CycleFetch/Execution Cycle Address in PC is sent to MAR Address decoder interpret the address in MA

R and locate the specified memory location Control signal ( read ) is issued Contents in specified location are deposited

into MDR Contents is then sent to IR Execute the instruction held in IR

Page 31: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Example program #1Example program #1

00001 LDA 11111

00010 ADD 11110

00011 STA 11101

00100 STP

1

2

3

4

Address Instruction

Page 32: Model Computer Input/ Output Unit Memory Unit Control Unit Arithmetic Logic Unit Data Bus CPU.

Example program #2Example program #2

00001 LDA 11111

00010 SUB 11110

00011 BNE 00110

00100 LDA 11111

00101 JMP 00111

00110 LDA 11110

00111 STA 11101

01000 STP

1

2

3

4

5

6

7

8

Address Instruction


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