Mobile Memory Technology Roadmap

Hung Vuong Qualcomm Technologies, Inc.

JC42.6 Sub-committee Chairman JC64.1 Sub-committee Chairman

Copyright © 2013 Qualcomm Technologies, Inc.

Mobile Devices, Today & Tomorrow

• Tremendous growth driving demand for Low-Power DRAM solutions across segments

• Multimedia applications continues to drive usage models & memory BW

• LPDDR & eMMC emerged as a mainstream choice for most mobile device – LPDDR4 natural migration from LPDDR2/3 – UFS is target as a replacement for eMMC

Multi-Core Processing Power (1 GHz+)

New User Experience for Content Consumption

Larger display (1080p/2K, 60fps)

High-Speed Connectivity (WiFi/ HSPA+/LTE)

Mobile DRAM Memory Trends

2009 2010 2011 2012 2013 2014 2015 2016

PC DRAM

GraphicsDRAM

3D Mobile DRAM

Mobile DRAM

DDR3-1600 DDR3-1866

DDR3-2133

DDR4-2133

GDDR5-5Gbps

GDDR5-7Gbps HBM – 128GB/s

HBM – 205GB/s

Memory Product available Projection

Wide IO1 – 17GB/s

Wide IO2 – 68GB/s

LPDDR2-800 LPDDR2-1066

LPDDR3-1600 LPDDR4-3200

LPDDR4-4266

3D DRAM

DDR4-2400 DDR4-2666

LPDDR4 and WIO2 Overview LPDDR3 & LPDDR3E LPDDR4 Wide IO2

Die Organization 1ch X 8 banks X 32 IO

2ch X 8banks X16 IO

4ch X 8banks X 64 IO

Channel # 1 2 4 & 8

Bank # 8 8 per channel (16 per die) 32 per die

Density 4Gb – 32Gb 4Gb – 32Gb 8Gb – 32Gb

Page Size 4KByte 2KByte 4KByte (4ch die), 2KB (8ch die)

Max BW per die 6.4GB/s, 8.5GB/s (overclocking)

12.8GB/s, 17GB/s (overclocking)

25.6GB/s & 51.2GB/s 34GB/s & 68GB/s(overclocking)

Max IO Speed 2133Mbps 4266Mbps 1066Mbps

Signal Pin # 62 per die 66 per die ~430 per die (4ch die), ~850 per die(8ch die)

Package POP, MCP POP, MCP KGD,

LOW- POWER DRAM LPDDR4

400 400

800 1066 1066

1600

2133

3200

4266

0

1000

2000

3000

4000

5000

2007 2008 2009 2010 2011 2012 2013 2014 2015

IO D

ata

Rat

e (M

bps)

LPDDRx Bandwidth Evolution

LPDDR4 Target

PC-DDR4 BW

* Projection

LPDDR4 vs. PCDDR4 Comparison Attribute LPDDR4 DDR4 Target Market Mobile Devices Laptop, Desktop, Server Die Architecture 2ch x16 1ch x16 IO Specification ~250-350mV LVSTL POD_12 DLL in DRAM No Yes Termination VSSQ VDDQ Max I/O Capacitance 1.3pF 1.3pF Command/Addressing 6pin SDR CA bus

(12 pins per 2-ch) 22 pins

Topology Point-to-point PoP & MCP

DIMM

Max Frequency 3200/4200MT/s 3200MT/s Low Frequency Operation

Yes Yes (DLL off ≤ 125Mhz

Target Supplies 1.1V 1.2V Pre-Fetch size 32B 16B / 8B(BC4)

LOW- POWER DRAM WIDEIO/3D TECHNOLOGIES

3D DRAM Value Propositions

• Better performance/power, power efficiency, than LPDDRx – 4x lower IO data rate relative to LPDDR4

• Small form factor (X-Y-Z) on PCB by integrating 3D DRAM into AP

• Excellent thermal performance if appropriate system heat spreader applied

Heat Spreader

3D DRAM + AP Structure

CH1 CH2 CH3 CH4

CH1 CH2 CH3 CH4

CH1 CH2 CH3 CH4

CH1 CH2 CH3 CH4

SoC die

Package

• Wide IO is thermally coupled with AP more closely. • Wide IO has lower heat dissipation resistance than LPDDRx POP.

Wide IO Mono Die or Cube

AP Hot Spot

3D DRAM Challenges for Mobile System

• 3D DRAM cost increase by TSV stacking – Limited memory density & BW scalability

• Non-uniform memory architecture for HLOS – System memory performance – Memory power management

• Complicate memory business model – Yield loss liability, RMA

STORAGE SOLUTION

Storage Trends

• Performance – Pressure on RAM increases reliance on storage – Explosive increases in performance – Images, video, applications growing – UI experience demands fluid snappy response

• Capacity – Capacity growth is moderate – Push toward Cloud storage, streaming – Productivity tablets and ultrabooks more

demanding.

Storage Sequential Performance

40 62 65 68 68 68 65

152

260 250

500

650

0

100

200

300

400

500

600

700

WR (MB/s)RD (MB/s)

* Projection

Storage Random IOPs Performance

700 1800 2000

4000 5000

5500

2000

5000

7500

10000

15000 15000

0

2000

4000

6000

8000

10000

12000

14000

16000

WR IOPs (MB/s)RD IOPs (MB/s)

* Projection

eMMC 4.5 Features: Winners & Losers

• Lots of new features, debatable if all of them are useful

Useful Features Debatable Features HS200 Real time clock Packed commands Large sector size Cache System Data Tag Background operations (BKOPS) Context ID Discard Thermal Spec Power-off Notifications Dynamic Capacity Sanitize Partition Type

• The useful features improve performance, help to decrease read and write latency, enhance data security

• The others often require more complex supports from HLOS, driver, and/or device firmware updates

e.MMC v5.0 at a Glance

• Focused on improve sequential performance • Applications include faster boot, USB3.0 performance,

and improve SWAP

Proposal Short description

HS400 DDR data transfer at 200MHz, up to 400MB/s

Field Firmware Update Procedure to upload FW to devices in the field

Production State Awareness

Mechanism to indicate if the production flow is in a pre-soldering phase to cope with re-flow NAND criticalities

Device Health Report Information about EOL approaching, average endurance, vendor specific information

Clarification on Power off notification and Sleep

Clarified power supply requirements in Idle & Sleep state when Power Off Notification is set to POWER_ON

Secure Removal Type Options to implement purge operations

Editorial Clarifications Features, registers, behaviors clarification

e.MMC Roadmap 2011 2012 2013 2014

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

e.MMC Spec. Timeline

e.MMC v4.5

e.MMC v4.51

e.MMC v5.0

e.MMC Security Extension v1.0 e.MMC v5.X?

v4.5 features plus updates • Errata corrections • e2MMC voltages • SecureTRIM/Erase • Invalid command clarification • Boot clarification • +pass through commands

v4.5 is obsolete -- superseded by v4.51 Data encryption Refereces: - IEEE1667 - TCG

= Target publication

Main Updates: • HS200 DDR, 400MB/s • Pre/post-production management • Firmware update • Device health report • Errata corrections • Sleep/Power-Off Notification

clarification and improvement

UFS v2.0 at a Glance

• Improve both sequential and random performance • Better user experience in overall

Proposal Short description

HS-G3 Multi-lane HS-G3 at 6Gbps, up-to 2 lane TX and RX

Unified Memory Extension Utilize host memory to improve latency and random performance

Unipro v1.6 Compatible More power saving features

M-PHY v3.0 Compatible HS-G3 6Gbps speed, lower latency when exiting from hibernate

Disable Firmware Update / Firmware ID Report Increase security by blocking new firmware loading

Editorial Clarifications Features, registers, behaviors clarification

UFS Roadmap 2011 2012 2013 2014

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

UFS Spec. Timeline

MIPI Spec. Timeline

UFS v1.0

UFS v1.1 UFS V2.0

UFS Security Extension v1.0 UFS v2.x?

• M-PHY HS-G1/G2 • Unipro point-to-point

connection • SCSI command protocol • To be superseded by v1.1

M-PHY v1.0/Unirpro™ v1.40

M-PHY v2.0/Unirpro v1.41

M-PHY v3.0/Unipro v1.6

• HS-G1, HS-G2(draft) • Point-to-point

connection

Data encryption Refereces: - IEEE1667 - TCG

Main updates: • e.MMC feature

alignment • Errata corrections • Alignment with M-

PHY v2.0/Unipro v1.41

• HS-G2 (finalized) • Point-to-point connection • Incompatible with Unipro

v1.40

Main updates: • HS-G3 • Multi-lane • Errata corrections

• HS-G3 • More power saving • Support network topology

= Target publication

e.MMC5.x UFS2.0 G2/G3-2lanes

SATA/SATA-Express w/ NVMe

Protocol e.MMC SCSI ATA/Simplified FLASH CMD

Boot ROM support Yes Planned Need boot NOR or change boot ROM

Boot partitions, redundant Yes Yes No

Low power mode STDBY – 0.5mW IDLE – <5mW SLEEP – <1mW

SLUMBER – <15mW DEV_SLEEP – ~5mW

Multiple Partition Yes Yes No

Enhance Area Yes Yes No

Background operation Yes Yes No

Queuing Packed CMD Yes Yes

TRIM Discard/Sanitize Yes TRIM

HW Reset, Write Protection Yes Yes Have RESET but not tied to protection mechanism

Reliable Write Yes Yes No

HCI No Yes AHCI/NVMe_HCI

Market/adoption rate Mobile Not mature Computing

Storage Features Comparison e.MMC5.x UFS2.0

G2/G3-2lanes SATA/SATA-Express

w/ NVMe Protocol e.MMC SCSI ATA/Simplified FLASH CMD

Boot ROM support Yes Planned Need boot NOR or change boot ROM

Boot LU, redundant Yes Yes No

Low power mode STDBY – 0.5mW IDLE – <5mW SLEEP – <1mW

SLUMBER – <15mW DEV_SLEEP – ~5mW

Multiple LU Yes Yes No

Enhance Area Yes Yes No

Background operation Yes Yes No

Queuing Packed CMD Yes Yes

TRIM Discard Yes Yes

HW Reset, Write Protection Yes Yes Have RESET but not tied to protection mechanism

Reliable Write Yes Yes No

HCI No Yes AHCI/NVMe_HCI

Market/adoption rate Mobile Not mature Computing

* Projection

Summary • LPDDR4

– Architecture changes to support higher BW – Signaling definition is optimized for power & performance – Natural migration path from LPDDR3

• DRAM 3D – 3D DRAM provides better performance per energy, small form factor and

thermally sustainable performance in mobile system. – Need “Pioneer/Trailblazer” to address 3D DRAM challenges more effectively

(business model, cost, test/reliability)

• Storage

– Pressure on RAM (performance/density/cost) implies storage performance improvement is needed

– JEDEC need to enable UFS adoption. UFS values are clear, providing higher sequential & random IOPS.

– eMMC5.0 provides sequential performance improvement only, does not address random IOPs

– eMMC in maintenance/sustaining mode, continue to enhance & optimize • eMMC will continue to exist in low- and mid-tier for years