MMIC Design Flow Using ADS

Complete and Fully Integrated

MMIC Design Flow Solution in ADS

Integrated design flow that

starts with system specs and

ends with successful delivery

of packaged MMIC in the

shortest amount of time

MMIC Design Flow using ADS 2012

Jack Sifri

MMIC Design Flow Specialist

Agilent EEsof EDA


Complete MMIC Design Flow Solution in ADS

Front End Design

Back End - Physical Design & Manufacturing

Start

MMIC Specs

2



Start

MMIC Specs

3

Technology Foundry Scope

MMIC

(GaAs / GaN)

• Front-to-Back PDK creation

• DRC rule deck

• EM substrate (.slm )

• MMIC tool bar

• Training

• Joint webinar and customer visit

RFIC

(SiGe/CMOS)

• Front-end PDK creation

• Momentum module support

• Increasing back-end support (for SiGe)

• GoldenGate qualification

• EM Qualification

Foundry Engagement – A Major Focus Area


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Foundry Partner Page: www.agilent.com/find/eesof-foundries


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http://www.agilent.com/find/eesof-foundries



Layout MMIC Tool Bar Available in Agilent EEsof MMIC Foundry Design Kits


Layout editing commands are easily accessible and are configured to work seamlessly

with a foundry process.

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Design Capture - Project Management Allows you to organize your design files in folders and sub folders

An Example

Workspace View of an LTE MMIC

power amplifier (PA) design

Top level PA design has all the

matching networks placed in a

separate sub-folder

Statistical Analysis folder has 6

subfolders. Each subfolder contains

design and data display files.

MMIC PA Layout Cell has the Layout

view and schematic view and

symbol.


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Easily drag and

drop components

from the ADS main

window into the

schematic window

and layout window

Drag & drop

designs into the

schematic page

Design Capture – Component Insertion Drag and drop components into schematic and layout windows


Drag & drop

Drag & drop Drag & drop

designs into the

layout page

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Optimization Optimization Cockpit on a low-noise amp (LNA)

Spec lines

Pause optimization and edit algorithm or

goals and resume optimization

Optimized

component

values and

history

The error

contribution

on each

goal

Store

optimization

solutions

and recall

them at any

time

Tune


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Phase Noise at

VCO’s Output

Phase Noise at

Divider’s Output

AM Noise at Divider’s Output

Custom Data Display and powerful post-processing Provide designers with better insight to circuit behavior


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Front End Design


Start

MMIC Specs

11

• Yield analysis doesn’t pin point the source of a low yield problem

• DOE and YSH are two unique tools in ADS. They work as an “X-Ray

machine” on designs. They pinpoint the source of the problem

Design For Manufacturing (DFM) Statistical Design Tools

Yield Sensitivity Histograms Design of Experiments (DOE)

DOE detects • Sensitive components

• Sensitive matching networks

• Interactions problems

YSH detect • Sensitive components

• Sensitive Specs - YSH allows

for Specs trade-off study

without having to re-perform

yield analysis

Pinpoint the problem & fix it

Help create robust designs that are insensitive to

temperature, bias, and process variation. The end result

is first-pass success and high yield.


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Design for Manufacturing (DFM) Example: K-Band Up-converter Macro Cell


DOE Based Design

Results

Wafer measured Results

Amp2

LO

Mixer 2

X-band

Ku-band

K-band Amp1

LO

Mixer 1

X-band

Ku-band

K-band

Standard Design

Wide, 10 dB Variation – Very sensitive

Wafer measured Results

Standard Design DOE Based Design

Both Designs on

the same wafer

This design used the

DFM design method

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DFM Analysis on LTE MMIC PA


Nominal Results - Pass

Initial Design

1

Yield Analysis on finished design

Lumped elements: +/- 5%

Line widths: +/- .5 um

2

4

DFM Tools helped pin point the

problem area and fixed it

Final Design

Specification:

Pout > 26 dBm @ Pin = 2 dBm

3

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Front End Design


Start

MMIC Specs

15


X-Parameters Bridge Between Our Customers

ESL

Electronic System

Level Design (ESL)

X-pars

IC Design Houses /

Component Vendor

System Integrators

New Designs

Share IP Protected

X-Parameters file

Existing Parts X-parameters

measurement

NVNA

X-Parameters

Component for ADS

Bottom-up Sim-based verification

Bottom-up meas-based verification

Top-Down Design Specs

Non-Linear

X-Parameters

Ideal Specs

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Case I - System Integrator Use Circuit Level Designs Results in lengthy simulation time and has no IP protection


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Case II - System Integrator Uses X-parameter models Results in faster simulation and trade off analysis with IP protected designs

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Generating X-Parameters for the PA One Tone – 50 ohms


Overlaid Results

Model (Red) Vs. Circuit (Blue)

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Front End Design


Start

MMIC Specs

20

Verification to LTE Wireless Standards in ADS


Features • True Circuit Level Co-Simulation

• Fast Co-Simulation (AVM)

• CE ties the circuit with Ptolemy

• Able to optimize for ACPR, EVM…

• Accounts for the Frame structure

• Identical to the real Wireless signal

• True and Accurate verification

LTE: Uplink transmitter EVM measurement

Filter Coupler

MMIC Source

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Verification to LTE Wireless Standards Design House Results


IL=1 dB

Ripple=.9 dB

Elliptic BPF Coupler

IL=.4 dB

MMIC PA

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Wireless Verification Results PA + Filter + Coupler + 50 ohm (Antenna)


Move Marker (m1) to -5 dBm

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Front End Design


Start

MMIC Specs

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Layout MMIC Tool Bar Available in Agilent EEsof MMIC Foundry Design Kits


Layout editing commands are easily accessible and are configured to work seamlessly

with a foundry process.

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MMIC PA 3D View


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Validate layer connectivity using “Cut Plane” cross-section

view in the 3D Viewer.

Layout Layers Validation in the 3D Viewer


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Layout Connectivity Checker Interactively verify physical connections using “Show Physical Interconnect”

Highlights all objects that are

physically connected, throughout

the hierarchy.

Example:

This shunt Capacitor is not shorted.

It is fine.

This series Capacitor is shorted and

needs to be fixed. It is shown by

the metallization run.

Problem Fixed.

Both capacitors

are not shorted


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• Designers are not constrained by always having schematic and

layout “automatically synchronized”

• Ability to switch back and forth between the three different modes

Three “Layout / Schematic” Synchronization Modes Provides optimum flexibility in the development of MMICs

• Allows to efficiently and

accurately fit many

elements designs into

small areas.

• The result is a smaller die

size and lowered overall

cost per chip.

Three bidirectional modes of synchronization

between layout and schematic


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Design Synchronization Provides optimum flexibility in the development of MMICs


• Designers can start in layout and auto generate the schematic

• Can also start in schematic and auto-generate the layout

• Designers can synch incremental changes (both directions)

Start in layout

Auto-generate the schematic

Or auto-generate the layout

from schematic

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Layout look-alike components, used in the schematic page, act as polymorphic

models and allow designers to select and simulate from various models (including

schematic, layout, momentum MW and RF, 3D FEM, data files, X-parameters, circuit-

level subnetworks, and other).

Layout Look-Alike Components Placed on the schematic page


Layout look-alike symbol is automatically

generated using the EM Setup window

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Front End Design


Start

MMIC Specs

32

Example: PDN impedance

Freq sweep 0-3 GHz

Matrix size: 17.501

2005 2008 2010

solve

time

load

time

solve

time

load

time

load

time

2003

Release Load Solve Storage

2005A

2008U1

2011

dense (N2) direct (N3) dense (N2)

dense (N2) iterative (NpN2) dense (N2)

dense (N2) direct (NlogN)1.5 sparse (NlogN)

sparse (NlogN) direct (NlogN)1.5 sparse(NlogN)

2003A

Momentum Solver – 5 years of (R)evolution


* Performance will vary dependent on complexity, frequency and other factors

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Preprocessor Mesher (2nd generation ) Solver

New Momentum 2nd Generation Mesher

• Increased accuracy, robustness and performance

– Fast floating-point interval arithmetic

• Improved mesh quality

– Avoids slivers

– Improved handling of small and wide shapes

– New algorithm for edge mesh and overlap extraction

• Reduced mesh complexity

– New quadrangles


rectangle

NEW

quadrilateral

triangle

OLD

NEW

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New Graphical Layer Definition

• Graphical, unified entry of layer and stackup data

– Defines layers and properties for Layout, Momentum, and FEM

• Easy drag and drop operations

– Easily select and modify properties

• Simpler, faster, and less error prone


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New Streamlined EM Setup Making EM Work for Everyone

• Single dialog replaces 8 – Easily navigate & review the setup options

• Same setup for Momentum, Momentum RF, & FEM

– Easy to try different solvers on the same design

• Setup is automatically saved and can be reused for other EM simulations


Previous EM Setup ADS 2011/2012

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Front End Design


Start

MMIC Specs

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• Catches errors early by running Desktop DRC from within ADS layout

• Runs Calibre and Assura to check designs prior to submitting to the foundries

Design Rule Checker (DRC) in ADS

Via to Via separation

must be > 100 um

Provides exact X,Y

co-ordinates location

of the errors


Run DRC DRC Viewer

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Desktop Design Rule Check (DRC) Results


These two Vias are

separated by < 60 um Auto Zoom and Auto Select Features

Provides X,Y coordinates

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Front End Design


Start

MMIC Specs

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Layout Versus Schematic (LVS) ADS Desktop LVS identifies components missing from schematic or layout

• Catch errors early by running ADS Desktop LVS from within ADS

schematic or layout

• Run Calibre LVS to check designs prior to submitting to the foundries

• Keep schematics and layouts in synch using “Design

Synchronization”


Access ADS Desktop

LVS from the tool bar

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Desktop Layout Vs Schematic (LVS) Results


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Front End Design


Start

MMIC Specs

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MMIC PA – Reticle Design


Draw Reticle

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Front End Design


Start

MMIC Specs

45

Multi Technology design in ADS allows to easily assemble and

EM simulate a whole module (with different substrates) on a

laminate or PCB board. See next section for more details.

MMIC in Package / Board

Board

MMIC

Module


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MMIC PA inside the DFN Package


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Expanded Bondwire Support

• New, fast analysis of bondwires in Momentum

– Automatically modeled as part of Momentum

simulation

– Calculates self and mutual inductance

– FEM provides the most accurate analysis

• Bondwires work for both Momentum and FEM

– Easily create the bondwire in Layout

– Full parametric control of bondwire profile

• Jedec Bondwire – Follows the JEDEC standard

parameters

• Shape Bondwire – More flexible control of the

bondwire profile

• Bondwires now have edit handles


Set parameters

Create and edit in 2D

Render in 3D

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QFN Designer

Predict Packaged Performance in Minutes


Performance w/ & w/o package

Accurately predict real performance

Quickly synthesize complex package,

combine with IC & PCB data

Configure QFN package

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Performance w/ & w/o package

Accurately predict real performance

Amkor Package Design Kit

Predict Packaged Performance in Minutes


Configure QFN package

Quickly synthesize complex package,

combine with IC & PCB data

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Front End Design


Start

MMIC Specs

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• Powerful finite-element 3D EM simulator

• Seamlessly integrated in the Advanced Design System (ADS)

• Solves a wide array of applications with impressive accuracy and speed.

• Layout geometries in ADS automatically used in FEM simulator for 3D EM simulation.

• FEM solutions can then be reviewed and included in a larger ADS circuit.


Advanced 3DEM - FEM Simulator

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Flip chip modeled as a dielectric brick on solder balls in

preparation for EM simulation and visualization of EM results.

3DEM - FEM Simulator


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Agilent EEsof Integrated 3D EM Flow EMPro link with ADS

EMPro Platform ADS Platform

FDTD Simulator FEM Simulator Momentum Simulator

Parameterized

3D

Components

Layout

CAD Data

Package Designers MMIC Designers

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Packaged LTE MMIC PA Fully Verified and Delivered to the System House


True MMIC Design Verification prior to

Manufacturing is done by Verifying and

Co-simulating the MMIC inside the

package and with bond wires using 3D

EM simulation

The Ultimate Verification Test

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Package Analysis using 3D EM Simulator in ADS E and H Field visualization of DFN Package with JDEC Bond wires


The E Field at 1.9 GHz The H Field at 1.9 GHz

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You can Co-Simulate and Optimize the

response in the same way as in Momentum

MMIC LNA in a QFN Package Example of a more sensitive Ku band LNA to package and bondwire effects


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Front End Design


Start

MMIC Specs

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Multi Technology design in ADS allows to easily assemble and

EM simulate a whole module (with different substrates) on a

laminate or PCB board.

MMIC in Package / Board

Board

MMIC

Module


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Module Design

MMIC amp in a package and mounted on a Laminate


Mounting LO Amplifier onto a QFN package, wire bonded, and

mounted on a laminate board – ready for FEM simulation

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Multi Technology Design in ADS2011 Example: Two IC’s mounted on a QFN package


You can perform circuit simulations (schematic and Layout views) and EM simulation

Ku Band Mixer followed by 2GHz PA

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Multi Technology Design in ADS2011 Example: Two IC’s mounted on a QFN package + Laminate layers


Ku Band Mixer followed by 2GHz PA One PDK

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Conclusion Agilent Provides Unique and Compelling Solutions


• Widest selection of PDK support in the industry

• Most accurate and fastest passive modeling (Model Composer and Advanced

Model Composer)

• Advanced Parameter Extraction and Device Modeling with IC-CAP

• Fastest and most accurate 3D planar EM solution available

• Integrated FEM and FDTD 3D EM toolsets

• Comprehensible Multi-technology design solution for IC/Module/Package/Board

• Full support of Agilent’s breakthrough technology in X-Parameter non-linear

modeling

• Flexible dataset post-processing and display capability

• ADS desktop DRC

• ADS desktop LVS

• Proven Design For Manufacturing toolset

• Patented circuit verification using complex waveforms

• GaAs IC and Module co-design and optimization

• Integrated instrument connectivity

• Lowest cost full solution in the industry

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MMIC Applications and Examples Complete MMIC / Module ADS Desktop Flow Solution


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MMIC Design Flow Using ADS

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