MIPS Data Path Control

Ellen SpertusMCS 111

October 25-30, 2001

2

Review: instruction types

Last time, we looked at components of the data path used by different types of instructions– Memory: lw, sw– Arithmetic-logical: add, sub, and, or, slt– Control flow: beq, jump

3

Review: data path components

• Program counter (PC)• Instruction memory• Register file• ALU• Data memory

4

Plan

• Today– MIPS instruction formats – MIPS control signals

• Next time– Going from instructions to control signals

5

Data path with control signals

6

Encoding: r-type

• Register-type instructions• Example: add $r1, $r2, $r3

000000 00010 00011 00001 00000 100000

op rs rt rd shamt funct

• Can you guess what the field names stand for?

7

Practice• or $r4, $r20, $r16

op rs rt rd shamt funct

• sub $r2, $r1, $r3

op rs rt rd shamt funct

operation functadd 100000sub 100010and 100100

or 100101

8

Encoding: i-type (lw, sw)

• Immediate-type instructions• Example: addi $r1, $r0, 15• Examples:

lw $r5, 0x3000($r2)

sw $r5, 0x3000($r2)

• Is rt a source or a destination?

op (6 bits) rs (5 bits) rt (5 bits) address/immediate (16 bits)100011 00010 00101 0011 0000 0000 0000

op (6 bits) rs (5 bits) rt (5 bits) address/immediate (16 bits) 101011 00010 00101 0011 0000 0000 0000

9

Encoding: i-type (beq)

200: beq $r1, $r0, 0x212

204: add $r3, $r1, $r0208: beq $r3, $r4, 204

212: add $r2, $r4, $r3

op (6 bits) rs (5 bits) rt (5 bits) address/immediate (16 bits) 000100 00001 00000 0000 0010 0001 0010

op (6 bits) rs (5 bits) rt (5 bits) address/immediate (16 bits) 000100

10

Encoding: j-type

• Jump-type instructions• Example: j 0x1208

• Practice: j 0x2348

op (6 bits) target address (26 bits)000010 00 0000 0000 0001 0010 0000 1000000010 00 0000 0000 0000 0000 1000 0010

op (6 bits) target address (26 bits)000010000010

11

Three instruction formats– r-type (register)– i-type (immediate)– j-type (jump)

op rs rt rd shamt funct op rs rt 16 bit address

op 26 bit address

R

I

J

Encoding summary

12

Data path with control unit

13

Steps in r-type execution

• Fetch instruction from instruction memory

• Read registers from register file• ALU operation• Write the result back

add $r1, $r2, $r3000000 00010 00011 00001 00000 100000

14

Step 1: fetch instruction

add $r1, $r2, $r3000000 00010 00011 00001 00000 100000

15

Step 2: read registers

add $r1, $r2, $r3000000 00010 00011 00001 00000 100000

16

Step 3: ALU

add $r1, $r2, $r3000000 00010 00011 00001 00000 100000

17

Step 4: write result back

add $r1, $r2, $r3000000 00010 00011 00001 00000 100000

18

Steps in i-type execution (sw)

• Fetch instruction from instruction memory

• Read registers from register file• ALU operation• Write the result

sw $r5, 0x3000($r2)101011 00010 00101 0011000000000000

19

Step 1: fetch instruction

sw $r5, 0x3000($r2)101011 00010 00101 0011000000000000

20

Step 2: read registers

sw $r5, 0x3000($r2)101011 00010 00101 0011000000000000

21

Step 3: ALU

sw $r5, 0x3000($r2)101011 00010 00101 0011000000000000

22

Step 4: write result back

sw $r5, 0x3000($r2)101011 00010 00101 0011000000000000

23

The effect of each control signalSignal name Effect when deasserted (0) Effect when asserted (1) RegDst The register destination number

for the Write register comes from the rd field (bits 15-11)

The register destination number for the Write register comes from the rt field (bits 20-16)

RegWrite None The register on the Write register input is written with the value on the Write data input

ALUSrc The second ALU operand is the sign-extended, lower 16 bits of the instruction

The second ALU operand comes from the second register file output (Read data 2)

PCSrc The PC is replaced by the output of the adder that computes the branch target

The PC is replaced by the output of the adder that computes the value of PC+4

MemRead None Data memory contents designated by the address input are replaced by the value on the Write data input

MemWrite None Data memory contents designated by the address input are replaced by the value on the Write data input

MemToReg The value fed to the register Write data input comes from the ALU

The value fed to the register Write data input comes from the data memory

Note that Figure 5.18 (p. 359) gets some of these wrong!

24

Control signals

Instruction RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0 R-format lw sw beq

25

26

Big picture

• We want to be able to use the same hardware to interpret different types of instructions

• Control signals allow this, by– controlling which path of a multiplexer is

enabled– controlling whether writes are performed– controlling ALU behavior

27

lw $r5, 0x3000($r2)100011 00010 00101 001100000000000031 26 25 21 20 16 15 0 op rs rt immediate/address

28

beq $r2, $r5, 400 000100 00010 00101 0000010000000000 31 26 25 21 20 16 15 0 op rs rt immediate/address

29

ALU control

• How is it done on Mite?• MIPS:

– R-type instructions:– lw instructions:– sw instructions:– beq instructions:

30

ALUOpOperation Opcode ALUOp Operation Funct

field ALU action ALU control input

lw 100011 00 load word XXXXXX add 010 sw 101011 00 store word XXXXXX add 010 beq 000100 01 branch equal XXXXXX subtract 110

R-type 000000 10 add 100000 add 010 R-type 000000 10 subtract 100010 subtract 110 R-type 000000 10 AND 100100 and 000 R-type 000000 10 OR 100101 or 001 R-type 000000 10 set on less than 101010 set on less than 111