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Millimeter-Wave BiST and BiSC using a High-

Definition Sub-Ranged Detector in 90nm CMOSSleiman Bou Sleiman

1, Amneh Akour

1,2, Waleed Khalil

2, Mohammed Ismail

1,2

Analog VLSI Lab1

and ElectroScience Lab2, ECE Department

The Ohio State University

Columbus, OH{bousles, akoura, khalil, ismail}@ece.osu.edu

AbstractA wideband CMOS mm-Wave amplitude detector for

on-chip self-test and calibration is presented. The high-

conversion-gain detector enables accurate on-chip amplitude

measurements and allows for the prediction of key RF

parameters. The detector operates across the 60GHz band and

achieves a dynamic range of 0-0.5V and a sensitivity of -9V/V.

The detectors practical use in mm-wave Built-in-Self-Test

(BiST) and Built-in-Self-Calibration (BiSC) circuits is

demonstrated using a 60 GHz CMOS LNA. Simulation results

show that the LNA gain, compression point, and intermodulation

distortion are predicted with minimal error. The detector and

LNA are built in IBMs 90nm CMOS technology.

I. INTRODUCTION

dvances in semiconductor technology allowed for the

implementation of high performance RF blocks in

CMOS, opening the doors for a full System-on-Chip

(SoC) solution. More recently, CMOS technology is sought

for the millimeter-Wave (mmW) regime albeit many

challenges and critical shortcomings with respect to SoC

integration. mmW and RF circuits, unlike the more robust

digital circuits, suffer from low yield due to process, power

supply, and temperature (PVT) variations and require several

expensive silicon cycles to meet their specifications.

Additionally, parasitics more pronounced at mmW than at

RF quickly come into play and increase the adverse

variability and hence the performance uncertainty of a given

chip. For this reason, the design of mmW/RF IC blocks in

platform baseband SoCs has so far been restricted.

Countering the advantages of decreasing feature size into

the nanometer regime, process variations even in digital

circuits are getting more amplified. This necessitates the

need for a new approach to RF and mmW design through

integration of on-chip Built-in-Self-Test (BiST) and Built-in-

Self-Calibration (BiSC) circuits. While highly beneficial in

GHz RF circuits, BiST(SC) have not been widely

implemented as design complexity was contained by

allowing for overdesign and some area/power sacrifices.

However in mmW and as devices scale down and parasitics

play ever-critical roles, the design complexity becomes very

quickly unbound. Two key components of the new design paradigm are block/system self-awareness and block/system

programmability. The first component is achieved with

accurate and efficient BiST as a precursor to implementing the

latter by leveraging the more robust digital capabilities of

SoCs. In other words, this is achieved using digitally-assisted

mmW circuits within calibration loops to alleviate mmW

shortcomings (Fig. 1.)

In Section II, we present a compact, non-invasive, and

efficient mmW amplitude detector serving the needs for both

BiST and BiSC. In Section III, we verify our detector using a

60 GHz LNA as circuit-under-test/calibration (CUT/C).

II. DETECTORDESIGN

A. Detector RequirementsTo enable testing and measurements of single blocks or an

aggregate of blocks in a transceiver, multiple detectors can be

inserted to extract the signal amplitudes at different points or

conversely a single detector with switches connecting it to thevarious measurement points. Opting for the first configuration,

we need to design area-efficient detectors whereas if targeting

the second, we need to have a very wide dynamic range

detector, as the signal varies considerably along the chain.

Other requirements include low power, wideband operation,

and more importantly high input impedance so as not to load

the circuit it connects to. Another important consideration

when dealing with complete on-chip measurements is the need

for high RF-to- DC conversion gain. A high conversion gain

is very desirable for self-test and self-calibration as it eases the

requirements on the digitizing ADC (see Fig. 1.) However,

with decreasing power supply voltages, an increase in

conversion gain limits the dynamic range. Previous detectors

described in the literature [1]-[7] do not offer high resolutionand most suffer from a low RF-to-DC conversion gain of

around -1V/V (see Fig. 2, [7] uses a 3.3V supply). In the next

section, we present a detector that fulfils the aforementioned

requirements, and to the authors best knowledge, the

implementation presented is the first to operate at mm-Wave

frequencies.

Fig. 1. Radio transceiver architecture with possible BiST and BiSC

configurations using loopback.

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B. Proposed Detector ArchitectureOur proposed architecture is shown in Fig. 3. It is an

implementation of an architecture similar to [1], however it

does not employ a feedback resistor for biasing but depends

on a separate gate biasing circuit. The input transistor is biased

in the subthreshold region and its saturated drain current can

be expressed as [9]

T

GS

n

0DnnV

Vexp

L

WII (1)

where ID0 is a current constant independent of gate-to-source

voltage, (W/L)n is the aspect ratio of the NMOS transistor, n is

a process dependent term related to depletion region

characteristics [4], and VT is the thermal voltage.

Superimposing a small sinusoidal input voltage, Vacos(t) on

the gate bias, Vbias, the following power series approximation

of the current equation holds:

)t2cos(nV2

V)tcos(

nV

V

nV2

V1I

)t(cosnV

V

2

1)tcos(

nV

V1I

nV

)tcos(VexpI

nV

)tcos(VVexp

L

WII

2

T

a

T

a

2

T

a0B

2

2

T

a

T

a0B

T

a0B

T

abias

n

0Dn

(2)

whereIB0 [=ID0(W/L)nexp(Vbias/nVT)] is the dc-bias current ofthe transistor. Initially charged to VDD, DCout is then

discharged by the drain current In through the NMOS

transistor. This creates a negative I-V relationship with respect

to an increase in the mmW signal amplitude. As the detector

output is low-pass filtered by the RC load, it reacts to the dc

component ofIn given by2

T

a0BnDC

nV2

V1II (4)

A high conversion gain can then be achieved with proper

device sizing and biasing. However, in order to achieve a wide

dynamic (i.e. amplitude) range, the detector should employ

several modes of operation each covering an overlapping sub-

range of amplitudes. This is achieved by appropriatelychanging the gate biasing of the input NMOS device: by

decreasing the gate bias, higher amplitude signals are needed

to turn the input transistor on. Using a 3-bit programmable

mode select voltage bias circuit, and setting the overlap to

50mVamp (Vbias=35mV), we achieve 8 modes of operation

covering a wide signal range from 0 to 0.5Vamp. As shown in

Fig. 4, the linear region of the response is between 0.2V and

1V (for a 1.2V supply) providing a slope of around -9V/V . To

reduce the loading impact of the detector, its input impedance

is kept greater than 800 across the 60 GHz band. Further,

the detectors wideband operation is also validated across the

60 GHz band. The complete circuit is built in IBMs 90nm

CMOS technology. As test and calibration do not need to run

all the time but only intermittently, low power requirements

(a)

(b)Fig. 3. The proposed mmW-amplitude detector: (a) Circuit core, (b)

Programmable mode select

]Fig. 4. mmWave-to-dc response of the proposed mmW-amplitudedetector

IN

DCout

Vbias

Pbias

d

VDD

Detector Core

VDD

Vbias

A1 A2 A3 A7

Thermometer-code

A7..1

Mode2..0

Programmable Mode Select

0

0.2

0.4

0.6

0.8

1

1.2

0 0.1 0.2 0.3 0.4 0.5

DCDetectorOutput(V)

High-Frequency Signal Amplitude (V)[55-65 GHz]

MODE0 MODE1 MODE2

MODE3 MODE4 MODE5

MODE6 MODE7

Fig. 2. Response of various detectors in literature

0

0.20.4

0.6

0.8

1

1.2

1.4

1.6

0 0.5 1

DCOutput(V)

Input RF Amplitude (V)

Huang

wang

Fan

Valdes

Jonsson

[6][4][8][7]

[1,2]

50mV

-9V/V

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are not critical for the detector circuits since the detector and

its bias circuit can be simply turned off using switches or

power gating.

C. Detector usage in BiST and BiSCThe detector can be used to quantify a number of transceiver

parameters such as gain, linearity, compression points, and

even IQ mismatchas presented in [10]. Since the detector is

followed by an ADC, a quantized detector response can eitherbe saved in a lookup table or fitted into an equation: possibly

as a function of slope (-9V/V), mode (50mV shifts), or

piecewise linear reconstruction to enable prediction of signal

amplitude. For example, using an 8-bit ADC and saving the

first modes response in a lookup table, a quantized detector

output of 128 (= 256/2, DCout = 1.2/2 = 0.6V) equates to a

0.09Vamp signal in mode0, +50mV per additional mode (ormore accurately +60mVbetween mode0 and mode1, +50mV

hereafter).

In the context of a self-calibration loop, the detector can be

used as an optimization indicator, e.g. following an

optimization step; a decrease inDCoutof a detector monitoring

a specific circuit node indicates an increase in the amplitude of

the signal at that node.

III. BIST AND CALIBRATION OF A60GHZ LNA

The LNA is the first gain stage in the receiver path and

hence needs to be designed to meet tight specifications for the

whole receiver. At 60 GHz, the design of the LNA becomes

very challenging as even the smallest parasitics or disruptions

in operating conditions can completely alter the circuit

performance.

In the following we demonstrate the feasibility of the

proposed detector for test and calibration of the LNA under

test, shown in Fig. 5 [11].

A. Built-in-Self-TestThe accuracy of the proposed detector is verified byconnecting it to a 60 GHz LNA and applying known input

amplitudes. It is worth noting that the detector is verified not

to load the LNA, a critical aspect of this design (see Fig. 7). A

complete on-chip solution to such a BiST configuration

requires loopback between transmitter and receiver chains. In

our demonstration, two detectors are used to sense the input

and output signals and output a dc voltage which is then

quantized (8-bits) and analyzed (see Fig. 6). The detectors

biasing is dynamically adjusted when its output is not

between 0.2 and 1V. In this example, we measure the gain

and compression point by sweeping the input amplitude and

predicting both the LNAs input and output signal amplitudes.

At each sweep instance, a gain value can be computed and

after a sufficient number of iterations, a gain curve is obtained

where the 1dB compression point is readily deduced.

Knowledge of the LNA gain enables more sophisticated tests,

such as two-tone tests for intermodulation (IM) measurements.

The IM3 amplitude can be extracted from the detector output

by measuring the input and output of the LNA and comparing

the latter with the expected output given no distortion (=

inputpredicted gain): the discrepancy between these twosignals is attributed to the IM amplitude. It should be noted

that in the case of two-tone tests, DCout becomes a low-frequency oscillating signal whose mean is to be considered in

the IM3 extraction [10]. The results of this sweep showing the

actual and predicted values using the detector are shown in

Fig. 8. It can be verified that the detector is able to match the

real gain with a maximum 0.3dB error, the 1dB compression

point and IIP3 to within 0.4dB, shown below in Table I.Table I

Actual vs Predicted values for LNA

Actual Predicted Error

Gain, A [dB] 10.14 10.45 0.3

P1dB [dBm] -9.73 -9.32 0.4

IIP3 [dBm] 3.9 4.3 0.4

B. Built-in-Self-CalibrationTo satisfy the growing number of corners, LNAs and

other mmW circuits need to incorporate some dynamic, rather

than static, structures that allow their operating points to adjust

and guarantee optimal operation under varying conditions, as

shown in Fig. 9. To enable the calibration loop, the previous

BiST setup is augmented with an optimization block that runs

a specific algorithm for each CUT/C. In the simple case of a

single tuning knob, the BiSC can perform an algorithm similar

to Fig. 10 which sweeps through the possible digital codes,

while holding the input constant, and keeps track of the

detector output: the code resulting in the minimum-

IN

Vbias

VDD

MatchingCircuit

CPW

Vbias

VDD

MatchingCircuit

CPW

Vbias

VDD

MatchingCircuit

CPW

MatchingCircuit OUT

Fig. 5. Three-stage cascade common-source LNA with interstage

matching

Fig 6. BiST and BiSC setup for the LNA

Fig. 7. Effect of the detectors on the LNA gain, input match, and NoiseFigure

CUT(LNA)

DET DET

BiST BiSCcontrolled

loopback

mmW/RF

Digital

-25

-20

-15

-10

-5

0

5

10

5.50E+10 6.00E+10 6.50E+10

dB S21 S21

NF NF

S11 S11

with detector w/o detector

55GHz 60GHz 65GHz

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DCout/maximum-mode is retained to be applied to the circuit

once the calibration run is finished.The LNA therefore needs to include tuning knobs

programmable voltage-biasing in [11]and possibly variable

passives for matching as in [12].

IV. CONCLUSION AND FUTURE WORK

In this paper, we present the design and implementation of a

wideband mmW amplitude detector largely suited for BiST

and BiSC. The detector is shown to measure, with certain

accuracy, key parameters of a 60 GHz LNA. Ongoing work to

embed programmability in the LNA will enable closing of the

calibration loop.

REFERENCES[1] F. Jonsson, H. Olsson, RF detector for on -chip amplitude

measurements,Electronics Letters, vol.40, no.20, pp. 1239-1240,30 Sept. 2004

[2] C. Zhang, R. Gharpurey, J.A. Abraham, Low Cost RF ReceiverParameter Measurement with On-Chip Amplitude Detectors,

VLSI Test Symposium, IEEE, pp. 203-208, 26th IEEE VLSI Test

Symposium, 2008

[3] A. Valdes-Garcia, R. Venkatasubramanian, R. Srinivasan, J. Silva-Martinez, E. Sanchez-Sinencio, A CMOS RF RMS Detector for

Built-in Testing of Wireless Transceivers, VLSI Test Symposium,IEEE, pp. 249-254, 23rd IEEE VLSI Test Symposium (VTS'05),2005

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Technique for RF Low-Noise Amplifiers, Microwave Theory andTechniques, IEEE Transactions on, vol.56, no.5, pp.1035-1042,May 2008

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8-14, Jan 2004[10] S. Bou Sleiman, M. Ismail, Transceiver Parameter Detection

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[11] A. Akour, M. Ismail, R. Rojas-Terran, Manufacturable 60GHzCMOS LNAs,Proceedings of the SDR 08 Technical Conferenceand product Exposition, Washington D.C., October 2008

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Fig. 9. Digitally-programmable mmW/RF designed with codes

covering a range of operations always including an optimal point

Fig. 10. Example of a simple calibration algorithm running in the

digital part of the SoC and controlling the mmW/RF circuit

Fig. 8. Measurements for LNA gain and linearity. Left: simulated and predicted gain curve, and gain compression point. Right: fundamental and

IM3 component curves, dotted lines show the LNAs simulated fundamental/IM3 behavior, solid lines are extended data-fitted lines from

extracted fundamental/IM3 amplitudes.

-8

-7

-6

-5

-4

-3

-2

-1

0

1

2

-18 -16 -14 -12 -10 -8 -6

OutputSign

alPower(dBm)

Simulated Gain Curve

Predicted Gain Curve

-1dB Line, w.r.t. predicted curve-45

-35

-25

-15

-5

5

15

-20 -15 -10 -5 0 5

OutputSign

alPower(dBm)

Series1

Series2

Linear (trend)

Linear (Series4)

Input Signal Power (dBm)

FundamentalIM3Predicted fund/IM3Simulated fund/IM3

480