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A microprogrammed CPUWe will consider an example that is both simpler and better explained than the one in our textbook. Consider a simple 4-instruction CPU (Smotherman, Figure 1). Each circle represents a control point – a place where, if we put a 1, the event will happen. Note that most of these events are merely gating data from a register onto the bus or from the bus into a register.

Go over each control point. Note that two control points are missing: read (should be an arrow going from memory into the MDR) and write (should be an arrow going out of the MDR to memory). The dark bar is the data bus.The four instructions are:

00 Load 01 Add 10 Store 11 Bnz (branch if not 0)

There are 14 control signals. There are only 12 circles above, but there should be a signal for Write (to memory) and Read (from memory). Each can be a 0 or a 1.

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We can number each control point:


Implementing each instructionBelow are the RTN statements and the control sequences for each of the four instructions:

Fetch (for ALL instructions):T0: MAR PC MAR_in, PC_outT1: read, PC PC + 1 read, PCincrT2: IR MDR IR_in, MDR_outT3: NOP Time to decode the opcode

Load:T4: MAR IR MAR_in, IR_outT5: read readT6: ACC MDR ACC_in, MDR_out, reset timer to T0

Add:T4: MAR IR MAR_in, IR_outT5: read readT6: TEMP ACC+MDR aluaddT7: ACC TEMP ACC_in, TEMP_out, reset timer to T0

Store:T4: MAR IR MAR_in, IR_outT5: MDR ACC MDR_in, ACC_outT6: write write, reset timer to T0

Branch on 0:T4: if ACC=0 PC IR if acceq0 then PC_in, IR_outT5: reset timer to T0


See web pages for the data path and the Register Transfer Notation instructions for the four instructions.

If we look at the 14 control signals side-by-side, we have a 14-bit word that can be considered an "instruction" – a micro-instruction.

The microinstructions for the fetch part of the instruction cycle would look like this:Fetch (for ALL instructions):

T0: MAR PC PC_out, MAR_inT1: read, PC PC + 1 read, PCincrT2: IR MDR MDR_out, IR_inT3: NOP Time to decode the opcode

1 2 3 4 5 6 7 8 9 10 11 12 13 14

ACC_

in

ACC_

out

Alua

dd

IR_in

IR_o

ut

MAR

_in

MDR

_in

MDR

_out

PC_in

PC_o

ut

PC_in

cr

Read

TEM

P_ou

t

Writ

e0 0 0 0 0 1 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0

We can consider each of the above 14-bit lines as an "instruction".We can write each one of these register-transfer "instructions" as a string of 14 0s and 1s.We can write the steps for each machine-language instruction as a series of 14-bit numbers (micro-instructions) and store them in a control memory in the CPU.If we derive ALL of the 14-bit numbers corresponding to ALL of the micro-instructions for all four instructions, we find that there are:

4 micro-instructions to implement the FETCH part of each instruction 3 micro-instructions to implement the LOAD instruction 4 micro-instructions to implement the ADD instruction 3 micro-instructions to implement the STORE instruction 2 micro-instructions to implement the BRZ instruction


This is a total of 16 different micro-instructions. That means we can store all of the micro-instructions in a 16x14 memory. However, we are going to add 6 bits to each micro-instruction:

1 bit for a "branch via table" control signal 4 bits for the address of the next instruction 1 bit for "OR address with acceq"

How this is implemented:The "Control Store Address Register" is a 4-bit number that holds the address of a micro-instruction. The 4-bit address is passed through a 4x16 decoder that will select one of the 16 memory cells. This memory cell is copied into the Control Store Instruction Register.


This micro-program never changes. Therefore, we will only read from the control memory. This can be implemented just like the memory cells from chapter 3, except that there are 4 select lines (to select 1 of 16 cells) at the bottom instead of 2 (to select 1 of 4 cells). And there are 20 Output lines instead of 3. Note that we do not need input lines because data cannot be written to this memory; it can only be read. So we also do not need a write-enable line.

The OUTPUT lines from this memory cell are always connected to the Control Store Instruction Register. And on each tick of the clock, the selected memory cell will be loaded into the Control Store Instruction Register. Each bit in the Control Store Instruction Register is connected to the corresponding control point (see the first figure). Since each bit in the Control Store Instruction Register is connected directly to the corresponding control point, the appropriate registers will have their data transferred.The four address bits of the instruction are connected to the Control Store Address Register, so the address of the next instruction is automatically loaded into the Control Store Address Register. So on each tick of the clock, the appropriate control signals are sent.


The micro-programConsider the microprogram instructions:Locations 0000 through 0100 are the micro-instructions for the FETCH part of each instruction.0000: MAR PC, next instruction is in location 0010 Note: we are SKIPPING over instruction 1. We will return to this later.0010: Read, PC PC + 1 read, PCincr0011: IR MDR MDR_out, IR_in0100: There is a 1 in the "branch via table" bit. So we will use the op code to determine which address in the micro-code to go to to execute the corresponding instruction.If the instruction is 00 (Load), go to 0101 (5)If the instruction is 01 (Add), go to 1000 (8)If the instruction is 10 (Store), go to 1100 (12)If the instruction is 11 (Bnz), go to 1111 (15)How could this be implemented? Run the 2 bits of the op code through a 2x4 decoder. Each output of the decoder is connected to the load signals of the Control Store Address Register, and causes the appropriate address to be loaded into the Control Store Address Register.If the output signals of the op code decoder are named I0 through I3 ("I" stands for instruction), then line I0 is the LOAD instruction, I1 is the ADD instruction, I2 is the STORE instruction, and I3 is the BNZ instruction. And if the Control Store Address Register is abbreviated AR, then the circuit would look something like this. NOTE that Smotherman uses a separate "branch via table" bit, but it is the same thing as T4 (because that is the ONLY place where it occurs!).T4 I0: AR 0101T4 I1: AR 1000T4 I2: AR 1100T4 I3: AR 1111


Implement the LOAD instructionT4: MAR IR IR_out, MAR_inT5: Read readT6: ACC MDR MDR_out, ACC_in, reset timer to T0

The microinstructions that correspond to these three Register Transfer Notation instructions are:

ADDR

ESS

ACC_

in

ACC_

out

Alua

dd

IR_in

IR_o

ut

MAR

_in

MDR

_in

MDR

_out

PC_in

PC_o

ut

PC_in

cr

Read

TEM

P_ou

t

Writ

e

Bran

ch

next

add

r

OR a

ddr w

ith

acce

q0

0101 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0110 00110 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0111 00111 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0000 0

Note that after the instruction in location 5, we go to location 6. After the instruction in location 6, we go to location 7. But after doing the instruction in location 7, we go back to location 0 and start all over with the next instruction.

Implement the ADD instructionT4: MAR IR IR_out, MAR_inT5: Read readT6: TEMP ACC+MDR ACC_out, aluaddT7: ACC TEMP TEMP_out, ACC_in, reset timer to T0

ADDR

ESS

ACC_

in

ACC_

out

Alua

dd

IR_in

IR_o

ut

MAR

_in

MDR

_in

MDR

_out

PC_in

PC_o

ut

PC_in

cr

Read

TEM

P_ou

t

Writ

e

Bran

ch

next

add

r

OR a

ddr

with

acc

eq0

1000 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1001 01001 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1010 01010 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1011 01011 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0000 0


Implement the STORE instructionT4: MAR IR IR_out, MAR_inT5: MDR ACC ACC_out, MDR_inT6: Write write, reset timer to T0

ADDR

ESS

ACC_

inAC

C_ou

tAl

uadd

IR_in

IR_o

utM

AR_in

MDR

_inM

DR_o

utPC

_inPC

_out

PC_in

crRe

adTE

MP_

out

Writ

e

Bran

ch

next

add

r

OR a

ddr

with

acc

eq0

1100 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1101 01101 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1110 01110 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0000 0

Implement the BRZ instructionT4: if ACC=0 PC IR if acceq0 then IR_out, PC_inT5: reset timer to T0

ADDR

ESS

ACC_

in

ACC_

out

Alua

dd

IR_in

IR_o

ut

MAR

_in

MDR

_in

MDR

_out

PC_in

PC_o

ut

PC_in

cr

Read

TEM

P_ou

t

Writ

e

Bran

ch

next

add

r

OR a

ddr

with

acc

eq0

1111

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 1

Note that to implement the Branch on Zero instruction, we need to look at the accumulator, and if it is 0, copy the address part of the instruction to the PC.If the accumulator is NOT 0, we do nothing – just proceed with the next instruction.If the accumulator is 0, we will have a 1 in the acceq0 bit. When we OR the acceq0 bit (1) with the "next address" field (0000), we get 0001.If the accumulator is NOT 0, we will have a 0 in the acceq0 bit. When we OR this with the "next address" field, we get 0000.So if we do NOT branch, we go to location 0 to get the next instruction.If we DO branch, we go to location 1 to get the next instruction. Note that instruction 1 activates the IR_out control signal and the PC_in control signal:PC IRThis is how a branch is implemented!


What we have just done is create a micro-program for implementing a 4-instruction CPU. The alternative would have been to hard-wire the CPU (like the example I did at the beginning of class yesterday). The advantage of using a micro-program to implement the register-transfer statements is that they can easily be changed.

MARIE microcodeConsider the MARIE instruction set. We have developed all of the register-transfer instructions to implement the MARIE instruction set. There are 23 unique register-transfer instructions. Our authors also add two more:

NOP If IR[15-12] = MicroOp2[4-1], branch to Dest

If we were to list all of the micro-instructions that are used to implement the MARIE instruction set, we would get the following list:See page Table 4.9 in text:

This list includes all 23 unique MARIE microinstructions plus two others (the first one 00000 and the last one 11000).We can assign a unique number to each micro-instruction, and use those numbers to create a micro-code instruction set for MARIE (the MicroOp Code column above).Because some micro-instructions can be done in parallel (on the same tick of the clock), we will allow for two micro-operations to be carried out on each tick of the clock. Since we need


5 bits to designate a single micro-operation, we will need 10 bits to designate two micro-operations.We also will use a "destination" field to indicate the address of the next instruction. However, rather than having each micro-instruction indicate the address of the next micro-instruction (as in the Smotherman example), the author uses another 1-bit field to indicate whether a jump is to take place or not. If the "jump" bit is 1, the address in the address field will be used to fetch the next micro-instruction. If the "Jump" bit is 0, we will simply advance to the next instruction. How wide does the "destination" field need to be? It depends on how many micro-instructions are needed to implement the entire MARIE instruction set. The entire MARIE instruction set can be implemented in fewer than 128 micro-instructions. So we will need 7 bits for the destination address. So our micro-instruction format looks like this:MicroOp1 MicroOp2 Jump Dest

17-13 12-8 7 6-0xxxxx xxxxx x xxxxxxx

The first part of the MARIE micro-program looks like this. See page Figure 4.23 of text:

However, the authors cheated – they used the register-transfer notation instead of the binary numbers.


What the first few lines should look like is this:Address MicroOp1 MicroOp2 Jump Dest0000000 01010 00000 0 00000000000001 00110 00000 0 00000000000010 10001 00000 0 00000000000011 01000 00000 0 00000000000100 11000 00000 1 01000000000101 11000 00010 1 0100111 (Load)0000110 10111 00100 1 0101010 (Store)0000111 10111 00110 1 0101100 (Add)0001000 10111 01000 1 0101111… … … … …

Note that having 16 compare instructions in a row is ridiculous. This would have an enormous impact on the speed of the machine! The method used by Smotherman makes much more sense. Another alternative that I have seen is simply taking the op code and adding 3 zeros (or 4 or however many are needed) to the right end of it and automatically jumping to that address. So you would get the following mapping of op codes and addresses:0001 0001000 (op code 1 jumps to address 8)0010 0010000 (op code 2 jumps to address 16)0011 0011000 (op code 3 jumps to address 24), etc.This assumes, however, that each machine instruction can be implemented with 8 or fewer micro-instructions.Our author also gives the microcode for implementing the STORE and ADD instructions. But again, they cheat and use the register-transfer notation rather than the binary micro-code. WE don't cheat! We'll do it in binary!


The STORE (op code = 0010) instruction:Note that the STORE instruction is one where two things can be done in parallel on the first tick (see MicroOp2).

Address MicroOp1 MicroOp2 Jump Destination

0101010 MAR IR[11-0] MBR AC 0 00000000101011 M[MAR] MBR NOP 1 0000000

In binary, this is:0101010 01011 01100 0 00000000101011 00111 00000 0 0000000

The ADD (op code = 0011) instruction:Address MicroOp1 MicroOp2 Jump Destination

0101100 MAR IR[11-0] NOP 0 00000000101101 MBR M[MAR] NOP 0 00000000101110 AC AC + MBR NOP 1 0000000

In binary, this is:0101100 01011 00000 0 00000000101101 01101 00000 0 00000000101110 00100 00000 1 0000000

Homework assignment: Write the 18-bit binary codes for the instructions that start at the following addresses in the control memory:

1. 01001112. 0101111

Use the format on the three lines above (which will actually give you 25 bits because you will precede each 18-bit instruction with its 7-bit address).


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