Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on...

36
Virtualizing NoC resources in chip-multiprocessors Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies Francisco Trivino, Jose L. Sanchez, Francisco J. Alfaro, Jose Flich 王王王 2012.10.24

Transcript of Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on...

Page 1: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

Virtualizing NoC resources in chip-multiprocessors

Microprocessors and MicrosystemsVolume 35, Issue 2, March 2011, Pages 230–245

Special issue on Network-on-Chip Architectures and Design MethodologiesFrancisco Trivino, Jose L. Sanchez, Francisco J. Alfaro, Jose Flich

王健宇2012.10.24

Page 2: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

2

Introduction NoC virtualization Performance evaluation Experimental results Conclusions

Outline

Page 3: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

3

Introduction NoC virtualization Performance evaluation Experimental results Conclusions

Outline

Page 4: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

4

Chip-mutiprocessors (CMP) are expected in the future

Applications run in CMP increase◦ Applications share resource, CMP load increase◦ Affect the performance of applications

Isolate the traffic of different applications to increase applications performance◦ Partition CMP into several regions

Introduction

Page 5: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

5

Introduction (cont.)

Page 6: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

6

Introduction (cont.)

Page 7: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

7

Introduction NoC virtualization Performance evaluation Experimental results Conclusions

Outline

Page 8: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

8

Partition CMP into several regions Virtual-regions (VR)

◦ Traffic can not traverse other regions Virtual-domains (VD)

◦ Message can cross the boundaries of the regions Logic-Based Distributed Routing (LBDR)

NoC virtualization

Page 9: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

9

NoC virtualization (cont.)

Virtual-regions (VR) Virtual-domains (VD)

Page 10: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

10

2 sets of bits per output port◦ 1 bit per port: connection◦ 2 bit per port: routing

Logic-Based Distributed Routing

Page 11: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

11

LBDR (cont.)

Page 12: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

12

Introduction NoC virtualization Performance evaluation Experimental results Conclusions

Outline

Page 13: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

13

Simulation environment System integration CMP model Workload Scenarios

Performance evaluation

Page 14: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

14

Simulation environmentSimics-GEMS

Page 15: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

15

System integration

Page 16: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

16

CMP model A processing element A router A private L1 cache A shared L2 cache A memory directory bank A memory controller

Page 17: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

17

CMP model (cont.)

Page 18: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

18

PARSEC v2.1 benchmark

Workload

Page 19: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

19

Baseline scenarios VR/VD scenarios

◦ Divided the CMP in four regions◦ Each region has the same number of resources◦ Each application is assigned to one region

Scenarios

Page 20: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

20

Baseline scenarios

Page 21: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

21

VR scenarios

Page 22: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

22

VR scenarios (cont.)

Page 23: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

23

VD scenarios

Page 24: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

24

Introduction NoC virtualization Performance evaluation Experimental results Conclusions

Outline

Page 25: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

25

Static Applications start until the first application

end (Blackscholes) Each scenario with 3 different packet

injection rates (PIR) Performance metrics

◦ Execution time◦ Network latency◦ Network throughput◦ Energy consumption◦ Link utilization

Experimental results

Page 26: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

26

Execution time

a

b

c

d

24%

18%

25%

Page 27: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

27

Execution time (cont.)

Blackscholes, Swaptions, Streamcluster, Fluidanimate

4%9%

Applications set two

Page 28: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

28

Network latency

a

b

c

d

29%

32%

33%

19%

Page 29: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

29

Network throughput

a

b

c

d

6%

8%18%

Page 30: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

30

Energy consumption

a

b

c

d

13%

10%

Page 31: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

31

Link utilization

Page 32: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

32

Link utilization (cont.)

Page 33: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

33

Link utilization (cont.)

Page 34: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

34

Link utilization (cont.)

Page 35: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

35

Introduction NoC virtualization Performance evaluation Experimental results Conclusions

Outline

Page 36: Microprocessors and Microsystems Volume 35, Issue 2, March 2011, Pages 230–245 Special issue on Network-on-Chip Architectures and Design Methodologies.

36

Improve the performance in CMP Partition CMP into several regions to isolate

the traffic of different applications Dynamic assign resources is a question

Conclusions