microprocessors

MICROPROCESSORS Based Systems II

E442

Professor Dr Ir Mostafa [email protected] 795 2747

Scheduled Studies

• Overview of Basics of Binary Operations• Review of Digital Electronic Components• Microprocessor and Microcontroller Architectures• Micro processing Using 8051 Architectures• Interrupt and Timing Systems• Real World Interfacing using A/D and D/A

converters, Motors …. Etc.• Appendices for the 8051 descriptions• Laboratory Applications

Short History

• The first Minicomputers appeared in 1964, PDP-8, by Digital Equipment Company

• The Microprocessor name appeared in 1972, using one unit of CPU

• In 1972 the Intel 4 bit, 4004, and the 8 bit, 8008 appeared, using 4 chips, CPU, ROM, RAM and shift register chip for output Expansions

• In 1991 over 750 Million 8 bit microcontrollers were delivered by chip manufactures

Microcontrollers, Microprocessors and

Microcomputers

• A Microcontroller is a Microcomputer with Memory and I/O integrated into one chip

• The Microcomputer is a Microprocessor with added Memory and Input/Output

• The Microprocessor contains the CPU, the ALU (Arithmetic and Logic Unit) and the Control Units, with partial memory and I/O configuration

The Basic Computer System

Registers and an ALU to ADD or SUBTRACT

8 D-type Latches to Construct an 8 bit Register

Adding Inputs & Outputs to the Registers and the ALU

Information Flow after the MOV Operation

A Program to Input two numbers, Add them and display the Result

THE INFORMATION AGE

• Data Processing is involved in Business Transactions, Communications, Transportation, Medical Treatments & Entertainments.

• In Industrial World it is employed in Design, Manufacturing, Distribution & sales.

• In Science & Engineering it would have not been developed Otherwise.

• New Processors Emerge after the evidence of success produced by application of previous processors

Digital Systems Manipulate The Following Discrete Elements of

Information

• The 10 Decimal Digits

• The 26 Digits of the Alphabet

• The 52 Playing Cards

• The 64 squares of the Chessboard

• Numeric Computations are Major applications using the digits, and hence the name

DIGITAL PROCESSORS

Voltage Range for Binary Signals High & Low, True & False, or 1 & 0

In MNOR cases True is 0 and False is 1Reliability of Binary Emerges from Only

Simple 1 and 0 Levels

Generic Block Diagram of a Microprocessor

The CPU (dark area) Includes; the Floating Point Unit (FPU), The Memory Management Unit (MMU)

and The Internal Cache

The Floating Point Unit (FPU)

• Processes Data in the form of the Scientific Notation 1.234x10N, Permitting the Handling of Very Large and the Very Small Numbers

• The CPU and the FPU, each contain a data path and a control path units

• The MMU and the Cache are included in the Memory Block of the Figure

The NUMBER SYSTEMS

Any Number N can be represented in the form N = k = -r m A k b k ,

1. The Decimal (base b = 10)

123.4510 = 1 x 102 +2 x 101 + 3 x 100 + 4 x 10-1 + 5 x10-2,

2. The Binary (base b = 2)

123.4510 = 0x27 + 1x26 + 1x25 + 1x24 + 1x23 + 0x22 + 1x21 + 1x20

+ 0x2-1 + 1x2-2 + 1x2-3 + 1x2-4 + 0x2-5 + 0x2-6 + 1x2-7 + 1x2-8

+ a remainder of 0.0007813

= 01111011.01110011 + 0.0007813 (a 16 bit representation)

The OCTAL and the HEXADECIMAL

3. In the OCTAL (base b = 8), same Number is:

123.4510 = 1x82 + 7x81 + 3x80 + 3x8-1 + 4x8-2 + 6x8-3 + 3x8-4 + 1x8-5 + 0.00002= 173.346318 + 0.00002

4. In the HEXADECIMAL (BASE B = 16), Same Number is:

123.4510 = 7x161 + Bx160 + 7x16-1 + 3x16-2 + 3x16-3 + 0.000048= 7B.73316 + 0.0000488

Note that the fraction is not rational, keeping a remainder dependent on the number of digits used

Powers of Twom 2m m 2m m 2m

0 1 9 512 18 262,144

1 2 10 1,024 19 524,288

2 4 11 2,048 20 1,048,576

3 8 12 4,096 21 2,097,152

4 16 13 8,192 22 4,194,304

5 32 14 16,384 23 8,388,608

6 64 15 32,768 24 16,777,216

7 128 16 65,536 25 33,554,432

8 256 17 131,072 26 67,108,864

Binary Coded Decimal (BCD)

Each Octal Digit can be presented by 3 binary digits

0 000 2 010 4 100 6 1101 001 3 011 5 101 7 111

Each HEXA digit can be presented by 4 binary digits

0 0000 4 0100 8 1000 C 1100 (12)1 0001 5 0101 9 1001 D 1101 (13)2 0010 6 0110 A 1010 (10) E 1110 (14)3 0011 7 0111 B 1011 (11) F 1111 (15)

Important Observations

• Shifting the bits left is multiplication by the base and shifting it right is division by the base (7 is 0111 and 14 is 1110)

• Dividing the binary code to groups of threes yield the BCD in Octal ( 12310= 1738 or 001111011 = 12310 = 173BCD 8 = 001 111 011)

• Dividing the binary code to groups of Fours yield the BCD in Hex ( 12310= 7B16 or 001111011 = 12310 = 7BBCD 16 = 0111 1011)

BCD ADDITION

America Standard Code for Information Interchange ASCII

52 Low & Upper Case, 32 Extra & 34 Controls

Even and Odd Parities

ASCII A = 1000001 = 01000001 for EVEN or = 11000001 for ODD

ASCII T = 1010100 = 11010100 for EVEN or 01010100 for ODD

Negative Numbers

N- = 2n – N+

-10010 = 28 – 10010 = 1000000002 – 011001002

= 100111002

For n = 8 bits –128 ≥ N ≤ 127N- = Nc+ + 1

Digital Logic Gates

The NAND & the Inv-In-OR verify deMorgan’s Theory

1 1 0 1 1 01 0 1 NAND 1 0 10 1 1 0 1 10 0 1 x’ + y’ = (xy)’ 0 0 1

Gate Rules and Properties• AND “ ۸ “ and OR “ ۷ “ gates are fundamental logic

formations

• Reverse of Inputs and Outputs of one yield the performance of the other

• CMOS gates (+3 to 15 V) are superior than DL, RTL or TTL (5V) concerning Low buffering & Delay

• High Speed CMOS (5V) “HCT” is designed to be compatible with TTL

Combinational Logic Design

• Determine the numbers of inputs “n” and outputs “m” from requirement specifications

• Write the Truth table relating n and m • Simplify the Boolean functions relating n & m• Generate the logic diagram• Verify the correctness of the design

The Sum, with sum of the min-terms and Karnaugh Map

The Logic Diagram of the Full Adder

The Carry, with sum of the min-terms and Karnaugh Map

Hardware Description Languages HDL

• VHDL (Very high speed Integrated Circuits Hardware Description Language) and

• Verilog (developed by Cadence Design Systems, Inc)

Both are specified by IEEE to describe and use Hardware compilers to determine the correctness of complex Combinational Logic Networks; essentially applied to design of advanced RISC computers

A Four to One Line Multiplexer

VHDL Conditional Data Flow Description Program

of the 4 to 1 Multiplexer

Verilog Data Flow Description of the 4 to 1 Multiplexer

Using Boolean Equations

Clocked Sequential Circuit Analysis Use the VHDL and Verilog Analysis

• Block Diagram of a Sequential Circuit

• Synchronous Clocked Sequential Circuit

Standard Graphical Symbols of Latches and Flip Flops

Basic Processing Components of Microprocessors and Micro controllersIR instruction Register, MAR memory access register

PC program counter, MDR memory data register

BUS Structures

• Simple two Bus structure

• More Flexible Two Bus Structure

Memory Block Diagram and Contents (RAM)

Memory Cycle Timing FormsChip Select (SC) Read/Write (R/W) Memory Operation 0 X None 1 0 Write to selected word 1 1 Read from selected word

Block Diagram of Dynamic Memory (DRAM)

Memory mapping in 8051

• ROM memory map in 8051 family

0000H

0FFFH

0000H

1FFFH

0000H

7FFFH

8751AT89C51

8752AT89C52

4k

DS5000-32

8k 32k

from Atmel Corporationfrom Dallas Semiconductor

Timing for the DRAM R/W Operations

Three Instruction Format

Memory Representation of Instructions and Data

Three Address Instructions for (A+B)*(C+D)

ADD T1, A, B M[T1]←M[A] + M[B]ADD T2, C, D M[T2]←M[C] + M[D]MUL X, T1, T2 M[X]←M[T1] x M[T2]

Or registers can be used for temporary storage:

ADD R1, A, B R1←M[A] + M[B]ADD R2, C, D R2←M[C] + M[D]MUL X, R1, R2 M[X]← R1 x R2

TWO Address Instructions for (A+B)*(C+D)

• MOVE T1, A M[T1]←M[A]• ADD T1, B M[T1]←M[T1] + M[B]• MOVE X, C M[X]←M[C]• ADD X, D M[X]←M[X] + M[D]• MUL X, T1 M[X]←M[X] x M[T1]

ONE Address Instructions for (A+B)*(C+D)

• LD A ACC←M[A]• ADD B ACC←ACC + M[B]• ST X M[X]←ACC• LD C ACC←M[C]• ADD D ACC←ACC + M[D]• MUL X ACC←ACC x M[X]• ST X M[X]←ACC

ZERO Stack Address Instructions for (A+B)*(C+D)

• PUSH A TOS←M[A]• PUSH B TOS←M[B]• ADD TOS←TOS + TOS-1• PUSH C TOS←M[C]• PUSH D TOS←M[D]• ADD TOS←TOS + TOS-1• MUL TOS←TOS x TOS-1• POP X M[X] ←TOS

Stack Activity for Execution

PUSH A Push B ADD PUSH C PUSH D ADD MUL

A B A+B C D (C+D) (A+B)(C+D)

A A+B C (A+B)

A+B

Use Registers Address Instructions for (A+B)*(C+D)

• LD R1, A R1←M[A]• LD R2, B R2←M[B]• ADD R3, R1, R2 R3←R1+R2• LD R1, C R1←M[C]• LD R2, D R2←M[D]• ADD R4, R1, R2 R3←R1+R2• MUL R1, R4, R3 R1←R1 x R3• ST X, R1 M[X] ←R1

Numerical Example for Addressing Modes

location in MemoryPC=250 250 Opcode modeinstruction at locations 250-251 251 Add or nr=500R1=400 252 next instruction400 700instruction is 500 800load to ACC 750 600800 300900 200

ADDRESSING Modes

Typical Programming Instructions

Data Transfer Instructions Arithmetic instructions

Name Mnemonic Name Mnemonics• Load LD Increment INC• Store ST Decrement DEC• Move MOV Add ADD• Exchange XCH Subtract SUB• Push PUSH Multiply MUL• Pop POP Divide DIV• Input IN Add with Cary ADDC• Output OUT Subtract with Borrow SUBB

Subtract Reverse SUBRNegate NEG


• Logical and Bit Manipulation Shift Instructions

Name Mnemonic Name Mnemonics

• Clear CLR Shift Right SHR• Set SET Shift Left SHL• Complement NOT Arithmetic Shift Right SHRA• And AND Arithmetic Shift Left SHLA• Or OR Rotate Right ROR• Exclusive Or XOR Rotate Left ROL• Clear Carry CLRC Rotate Right with Carry RORC• Set Carry SETC Rotate Left with Carry ROLC• Complement Carry COMC


• Control Instructions Conditional Branching, with PSR

Name Mnemonic Name Mnemonics

• Branch BR Br. If Zero BZ Z=1• Jump JMP Br. If not Zero BNZ Z=0• Skip Next Instr. SKP Br if Carry BC C=1• Call Procedure CALL Br. if no Carry BNC C=0• Return from Prc. RET Br. If Minus BN N=1• Comp. (by Sub.) CMP Br. If plus BNN N=0• Test (by ANDing) TEST Br. If Overflow BV V=1• Br. If no Overflow BNV V=0


Conditional Branch Instructions for Unsigned Numbers

Branch Condition Mnemonic Condition Status Bits

• Branch if Higher BH A > B C + Z = 0• Br If Higher or Equal BHE A ≥ B C = 0• Branch if Lower BL A < B C = 1• Br. If lower or Equal BLE A ≤ B C + Z = 1• Br. If Equal BE A = B Z = 1• Br. If not Equal BNE A ≠ B Z = 0


Conditional Branch Instructions for Signed numbers

• Br. If Greater BG A > B (N Ө V) + Z = 0• Br. If Greater or Equal BGE A ≥ B N Ө V = 0• Branch if Less BL A < B N Ө V = 1• Br. If Less or Equal BLE A ≤ B (N Ө V) + Z = 1

Block Diagram

CPU

On-chip RAM

On-chip ROM for program code

4 I/O Ports

Timer 0

Serial PortOSC

Interrupt Control

External interrupts

Timer 1

Timer/Counter

Bus Control

TxD RxDP0 P1 P2 P3

Address/Data

Counter Inputs

Pin Description of the 8051

1234567891011121314151617181920

4039383736353433323130292827262524232221

P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST

(RXD)P3.0(TXD)P3.1

(T0)P3.4(T1)P3.5

XTAL2XTAL1

GND

(INT0)P3.2(INT1)P3.3

(RD)P3.7(WR)P3.6

VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)

8051(8031)

Port 0 with Pull-Up Resistors

P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7

DS500087518951

Vcc10 K

Port 0

Port 3 Alternate Functions

17RDP3.7

16WRP3.6

15T1P3.5

14T0P3.4

13INT1P3.3

12INT0P3.2

11TxDP3.1

10RxDP3.0

PinFunctionP3 Bit

RESET Value of Some 8051 Registers:

0000DPTR

0007SP

0000PSW

0000B

0000ACC

0000PC

Reset ValueRegister

RAM are all zero.

Registers

A

B

R0

R1

R3

R4

R2

R5

R7

R6

DPH DPL

PC

DPTR

PC

Some 8051 16-bit Register

Some 8-bitt Registers of the 8051

Sequence Controller Allow High Speed Execution

The Sequential State Diagram

Wait State is added to allow Synchronization with Slow devices

MOV instruction copies contents

ORG, MOV, ADD, END and Label:

Operation Codes for MOV, ADD and Label:

DB (Define Byte) and its Label:

Assembling and Running a Program

PSW (Program Status Word) Register

Register Banks and RAM Addresses

RAM Addresses are usable instead of the Register name

Selecting Register Bank 2

• RAM memory space allocation in the 8051

7FH

30H

2FH

20H

1FH

17H

10H

0FH

07H

08H

18H

00HRegister Bank 0

(Stack ) 1Register Bank

Register Bank 2

Register Bank 3

Bit-Addressable RAM

Scratch pad RAM

Stack in the 8051

• The register used to access the stack is called SP (stack pointer) register.

• The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.

7FH

30H

2FH

20H

1FH

17H10H

0FH

07H

08H

18H

00HRegister Bank 0

(Stack ) Register Bank1

Register Bank 2

Register Bank 3

Bit-Addressable RAM

Scratch pad RAM

Program Interrupts

• Interrupts are initiated at unpredictable point during program execution

• Address of the interrupt service routine (ISR) is determined by hardware procedure

• Interrupt necessitates storage of all or part of the performing register set (not only the program counter)

Three Major Interrupts

• External Interrupts (from input or output devices requesting transfer of data or time out of an event)

• Internal Interrupts (caused by traps of illegal or erroneous use of instruction or arithmetic overflow of data)

• Software Interrupts (are initiated by executing instructions. It is a special call instruction)

Response to an Interrupt

• Enable Interrupt (EI=1) flag should be on• Complete execution of present instruction• Enabling of Interrupt Acknowledgement output (INTACK)• Response by providing Interrupt Vector Address (IVAD) • Typical micro instructions are

SP←SP-1 decrement stack pointerM[SP]←PC store return address on stackSP←SP-1 decrement stack pointerM[SP]←PSR store processor status word on stackEI←0 Reset Enable InterruptINTACK←1 enable interrupt acknowledgmentPC←IVAD transfer interrupt vector address to PC

Example of External Interrupt Configuration

Interrupt 6 Vector Table of 8051

Interrupt ROM location Pin

• Reset 0000 9• Ext. hardware 0 (INT0) 0003 P3.2(12)• Timer 0 (TF0) 000B • Ext. hardware 1 (INT1) 0013 P3.3(13)• Timer 1 (TF1) 001B• Serial COM (R1 and T1) 0023

Interrupt Enable (IE) Register

• EA IE7 Interrupt Enable• - IE6 reserved for future use• ET2 IE5 enable or disable timer 2 overflow• ES IE4 enable or disable serial port Int.• ET1 IE3 enable or disable timer 1 overflow• EX1 IE2 enable or disable external Int. 1• ET0 IE1 enable or disable timer 0 overflow• EX0 IE0 enable or disable external Int. 0

Instructions to enable Interrupts

1.MOV IE, #10010110B ;enable serial, ;timer 0 and Ex1 Intrs

2.CLR IE.1 ;mask (disable) T03.CLR IE.7 ;disable all interts.4.Another way is

SETB IE.7 ;global enable Intr.SETB IE.4 ;enable serial Intr.SETB IE.1 ;enable timer o IntrSETB IE.2 ;enable EX1 Intr.

Major Eight Bit Microcontrollers

• Motorola 6811

• Intel 8051

• Zilog Z8

• PIC 16X

They are not compatible, each has its own instruction set

Selection Arguments of Micro controllers

• Application Requirements, including:o Clock speed, Packaging configurations (DIP

“Dual in line Packaging”, or ADF “Quad flat Package”, ROM and RAM on the chip, Power consumption, Number of pins, System upgrade capability, and Costing…etc

• Supporting SoftwareCompilers, emulators and Technical Support

• Diversity of SuppliersIntel.com Atmel.comsci.siemens.com Philips.cm dalsemi.com

Intel 8051 Family

Feature 8051 8052 8031

ROM (on-chip) 4K 8K 0KRAM (Bytes) 128 256 128Timers 2 3 2I/O pins 32 32 32Serial port 1 1 1Interrupt Sourcs 6 8 6

Useful Information

• WatchDog is the ultimate application for restricting and monitoring the time you or others spend on the computer (Software example at www.watchdogpc.com)

• Special Function Registers (SFR) are:A, B, PSW, and DPTRThese can be used by name or address

Care for Negative Numbers• As the 8051 is 8 bit chip Watch

MOV A, #-128 ; A = 1000 0000 (A=80H)MOV R4, #-2 ; R4=1111 1110 (R4=FEH)ADD A,R4 ;A =0111 1110 (A=7EH=126)This result is Wrong, as OV is 1 (for overflow)OV in the PSW should be then OV=1

• The following case is true, as OV=0

Correct Negative Results

• The OV flag need to be zero to know the correctness of the negative number operations

MOV A, #-2 ;A=1111 1110 (A=FEH)MOV R1, #-5 ;R1=1111 1011 (R1=FBH)ADD A,R1 ;A=1111 1001 (A=F9H=-7)

Note that OV=0 of (PSW), indicating the correctness

LOOP and JUMP Instructions

• LOOP is repeating a sequence of instructions a number of times which is a widely used action in micro processing. Its instruction is:

“ DJNZ register, label”The register is Decremented repeatedly so long as it is Not Zero and Jumps to the target address referred to by the label.

Example of Repeated Additions

MOV A,#0 ;A=0 or clear AMOV R2,#10 ;load R2 by 10AGAIN: ADD A,#03 ;add 3 to ADJNZ R2,AGAIN ;repeat till R2=0MOV R5,A ;save A in R5

Here the maximum number of repetitions for 8 bit registers is 256 as 255 is the maximum number

Nested Loops are used for more than 256 repetitions

Example of 700 Loops

MOV A,#55H ;A is 55HMOV R3,#10 ;R3 is 10NEXT: MOV R2,#70 ;R2 is 70AGAIN: CPL A ;complement ADJNZ R2,AGAIN ;repeat 70 timesDJNZ R3,NEXT ;repeat 10 times

Specialized JUMP StatementsJZ is jump if accumulator A is Zero, andJNZ is jump if accumulator A is Not Zero

MOV A,R0 MOV A,R5JZ OVER JNZ NEXTMOV A,R1 MOV R5,#55JZ OVER …………………………… ……………OVER: …………….. NEXT: ………..

Conditional Jump Instructions

• JZ Jump if A=0, restricted to A• JNZ Jump if A not 0, restricted• DJNZ Decrement and Jump if any A • CJNE A,byte Jump if A is equal to byte• CJNE reg,#data Jump if byte not equal to #• JC Jump if CY=1• JNC Jump if CY=0• JB JUMP if bit = 1• JNB Jump if bit = 0• JBC Jump if bit=1 and clear bit

Conditional Jumps can put the low byte and high byte in two Registers

• Summation of 79H, F5H and E2HMOV A,#0 ;clear AMOV R5,A ;clear R5ADD A,#79H ;A=79HJNC N_1 ;if no carry add nextINC R5 ;if CY=1 inc R5N_1: ADD A,#0F5H ;A=6E and CY=1JNC N_2 ;jump if CY=0INC R5 ;if CY=1 then increment R5N_2: ADD A,#0E2H ;A=50 ad CY=1JNC OVER ;jump if CY=0 INC R5 ;if CY=1, increment R5OVER: MOV R0,A ;Now R0=50H & R5=02

Port Toggle of H-L bit levels

ORG 0 ;Start LocationBACK: MOV A,#55H ;A=55HMOV P1,A ;P1=55HLCALL DELAY ;time DelayMOV A,#0AAH ;A=AAHMOV P1,A ;P1=AAHLCALL DELAY ;time delaySJMP BACK ;Repeat the sequence

Note: LCALL is 3 bytes and ACALL is 2 bytes, it makes no difference which is used, it only save few bytes of the program size if ADELAY is used

The Delay Subroutine

ORG 30H ;put delay at 30HDELAY: ;nested loop delayMOV R4,#255 ;R4=FFHNEXT: MOV R5,#255 ;R5=FFHAGAIN: DJNZ R5,AGAIN ;repeat till R5=0DJNZ R4,NEXT ;Decrement R4;keep loading R5 till R4 is 0RET

RAM configuration of 8051

7FH

30H

2FH

20H

1FH

17H

10H

0FH

07H

08H

18H

00HRegister Bank 0

(Stack ) 1Register Bank

Register Bank 2

Register Bank 3

Bit-Addressable RAM

Scratch pad RAM

STACK in the 8051• The stack pointer (SP) register (8 bits)

accesses the stack, at address 07 of RAM • RAM location 08 is first to be used stack• To load register content to stack use PUSH• To load a register back from stack use POP• Pushing data increments the SP by 1, in

contrast to many x86 processors using (-1)• RAM address is used instead of RAM name• When using stack do not use R-banks 1 & up

EXAMPLES for PUSH

MOV R6,#25H ;SP = 07MOV R1,#12H ;SP = 07MOV R4,#0F3H ;SP = 07PUSH 6 ;SP = 08 = 25HPUSH 1 ;SP = 09 = 12H & SP-1=25HPUSH 4 ;SP=0A=F3H, SP-1=09=12H;and SP-2 = 08 = 25H

EXAMPLES for POP

• If the stack is:0B = 54H, 0A = F9H, 09 = 76H, 08 = 6CHSP = 0B then the followingPOP 3 ;pop into R3, and SP = 0APOP 5 ;pop into R5, and SP = 09POP 2 ;pop into R2, and SP = 08POP 4 ;pop into R4, and SP = 07

To AVOID stack & bank 1 conflict

MOV SP,#5FH ;make RAM 60H first;stack locationMOV R2,#25H ;insert 25H in R2MOV R1,#12H ;insert 12H in R1MOV R4,#0F3H ; insert F3H in R4PUSH 2 ;SP=60 = 25HPUSH 1 ;SP = 61 =12H & SP-1= 60 = 25HPUSH 4 ;SP = 62 = F3H, SP-1 = 61 = 12H;and SP-2 = 60 = 25H

Block Diagram of 64Kx16 RAM

Block Diagram of 256Kx8 RAM

Examples of Fundamental Functions for 8051

INCLUDE 8051.mcINCLUDE 89S8252.mcButton1 EQU P3.0Button2 EQU P3.1Direction BIT 0HStart:MOV PORT1,#FFHMOV PORT3,#FFHMOV A,#FEH ;set ACCU to FEH=254=1111110Running_Light:MOV PORT1,AJB Direction,Check_1 ;Jump to “Check_1”, if bit direction is setRL ACheck_1:JNB Direction,Check_2RR ACheck_2:LCALL WaitLJMP Running_LightWait:#If NOT DEBUGGING

For Addition the Accumulator A must be involved

MOV A,#0F5HADD A,#0BH ;F5H 1111 0101;+0BH 0000 1011; 100H 0000 0000;CY=1, a carry out from D7;PF=1, number of ones is ZERO (even number);AC=1, a carry from D3 to D4.

Addition of Individual Bytes

;a sequences of 5 addresses carry 5 numbers;40=(70), 41=(EB),42=(C5),43=(5B),44=(30)MOV R0,#40HMOV R2,#5CLR AMOV R7,AAGAIN: ADD A,@R0JNC NEXTINC R7 ;track of carriesNEXT: INC R0DJNZ R2,AGAIN

ADDC, Addition of 16 bit numbers

;Addition of 3C E7 + 3B 8D, addition with carry

CLR C ;make CY=0MOV A,#0E7HADD A,#8DH ;A=74H, and CY=1MOV R6,AMOV A,#3CHADDC A,#3BH ;3C+3B+1=78HMOV R7,A ;save the high byte of the sum

DA instruction corrects for BCD Addition

MOV A,#47HMOV B,#25HADD A,B ;A=6CHDA A ;A=6C+6=72H

; 47H 0100 0111 ;+25H 0010 0101; 6CH 0110 110001100111 0010

SUBB is the only subtraction instruction

CLR C ;make CY=0MOV A,#3FHMOV R3,#23HSUBB A,R3 ;Add 2s comp of ;23 and invert the carry

; 3F 0011 1111 0011 1111;- 23 0010 0011 1100 1101 2s cmp1 0001 11000 CF=0CY=0, AC=0 and programmer looks for +ve or –ve flag

Registers A and B are the only registers to handle MUL and DIV

MOV A,#25HMOV B,#65HMUL AB ;25H*65H=E99H,;B=0EH and A=99HMOV A,#95MOV B,#10DIV AB ;A = 09 and B = 05 ;remainder; CY=0 and OV=0, if number is 0, B=0 and OV=1

LOGIC Instructions

ANL is AND, ORL is OR & XRL is XORThe Destination is normally the AccumulatorMOV A,#35HANL A,#0FH ;Now A = 05HORL A,#02H ;now A = 07HXRL A,#0CH ;now A = 0BH

CPL A ;complements A & CJNE A,#99H,NEXT is compare and jump to NEXT if not equal.

RR, RL, RRC & RLC for Accumulator

MOV A,#36H ;A=0011 0110RR A ;A=0001 1011RR A ;A=1000 1101RL A ;A=0001 1011RRC A ;A=0000 1101, CY=1RLC A ;A=0001 1011, CY=0RLC A ;A=0011 0110, CY=0SWAP A ;A=0110 0011, CY=0SETB C ;A=0110 0011, CY=1

Special Function Register (SFR) Addresses

ACC* Accumulator 0E0HB* B Register 0F0HPSW* Program Status Word 0D0HSP Stack Pointer 81HDPTR Data Pointer (DPL 82H & DPH 83H)P0* Port 0 80HP1* Port 1 90HP2* Port 2 0A0HP3* Port 3 0B0HIP* Interrupt priority control 0B8HIE* Interrupt enable control 0A8HTMOD Timer/counter mode control 89HTCON* Timer/counter control 88H

* Is bit addressable registers

Special Function Register (SFR) Addresses

T2CON* Timer/counter 2 control 0C8HT2MOD Timer/counter Mode control 0C9HTH0 Timer/counter 0 high byte 8CHTL0 Timer/counter 0 low byte 8AHTH1 Timer/counter 1 high byte 8DHTL1 Timer/counter 1 low byte 8BHTH2 Timer/counter 2 high byte 0CDHTL2 Timer/counter 2 low byte 0CCHRCAP2H T/C 2 capture register high byte 0CBHRCAP2L T/C 2 capture register low byte 0CAHSCON* Serial control 98HSBUF Serial data buffer 99HPCON Power control 87H

PUSH & POP use the addresses

PUSH 06 ;put contents of R6 TOSPUSH 0E0H ;put contents of A TOPPOP 0F0H ;put TOS in Register B;contents of B = APOP 02 ;TOS goes to R2;now R2 = R6

Move Code Byte MOVC A,@A+DPTR

ORG 100HMOV DPTR,#200H ;load DPTRB1: CLR A ;A=0MOVC A,@A+DPTR ;Data into AJZ Exit ;exit if char =0MOV P1,AINC DPTRSJMP B1EXIT: ….ORG 200HDT: DB “The Earth is like a ball”, 0END

Moving Data from Table

MOV R3,#9MOV DPTR,#SQR ;Load pointerMOV A,R3MOVC A,@A+DPTR

ORG 100HSQR: DB 0,1,4,9,16,25,36,49,64,81

Move Code Byte MOVC A,@A+PC

MOV A,R3INC AMOVC A,@A+PCRETSQR: DB 0,1,4,9,16,25,36,49,64,81

MOVX @DPTR,A ;Bring Bytes from X data memoryMOVX @Ri,A ;bring Byte from X data (i=0 or 1)

Moving Data from Table to Port

MOV DPTR,300H (or #SQR)MOV A,#0FFH ;A=FFHMOV P1,A ;P1 is inputBACK: MOV A,P1 ;get 0 – x – 9MOVC A,@A+DPTRMOV P2,ASJMP BACKORG 300HSQR: DB 0,1,4,9,16,25,36,49,64,81END

Exercises

1. Write a program to add the following data and store the result in RAM location 36HORG 30HDT: DB 06,09,02,05,07

2. Write a program to calculate y = x2 + 2x + 5, where x is between 0 and 9.

Solution of Exercise 1MOV A,#0 ;clear AMOV R3,A ;clear R3MOV R0,#30H ;set the data addressMOV R2,#5 ;counter for data pntsAGAIN: ADD A,@R0 ;put data point to AJNC NEXT ;go to carry count INC R3 ;move to next dataNEXT: INC R0 ;record the carryDJNZ R2,AGAIN ;go to next additionORG #30H ;start address of dataDT: DB 06,09,02,05,07 ;data sequence in MEND ;end statement

Exercise 2 (y = x2+2x+5)MOV R4,#9 ;set counter for data x pointsMOV DPTR,#30H ;set locations of y in memoryAGAIN: MOV R2,#0 ;starting value of xMOV A,R2 ;put x in the accumulatorMOV B,R2 ;put x in BMUL AB ;get a value for x2MOV R3,A ;put x2 in R3CLR A ;clear AMOV A,#2 ;put 2 in AMUL AB ;2x is now in AADD A,R3 ;x2 + 2x is now in AADD A,#5 ; x2 + 2x + 5 is now in AMOV @DPTR,A ;store the value in #30HINC DPTR ;increment the pointerINC R2 ;increment xDCR R4 ;decrement the counterDJNZ R4,AGAIN ;calculate another pointEND

8051 Serial Communications

• Parallel port communications (where data is transferred in parallel, one byte or more at a time, using 10 or more parallel wires, to short distances) is now obsolete

• Serial communications (one bit at a time) is now the way, using the serial port RS232 (started 1960 by Electronics Industries Association “EIA”), and applying the HyperTerminal of modern PCs. Parallel in, Serial out shift registers are applied. For large distances D/A conversion is also needed

• Synchronous communications transfer blocks of data at a time, while Asynchronous communications transfer single bytes at a time

• USART (Universal Synchronous Asynchronous receivers-transmitters) and UART (Universal Asynchronous receiver-transmitter), which is included in 8051 chips, are used to do the transformations

• Full Duplex data communications are common, at least for short distances. The ASCII 8 bit codes (with even or odd parities) are framed by start bit (0) and stop (1) bit (or two bits))

Serial Connection and Programming• The serial connection RS232 uses 15 connecting

pins, and used to have 25 or 9 connecting pins• The supply potentials are –3 to –25V for 1 and 3

to 25V for 0. It needs another IC converter to generate the TTL values for the 1 and 0

• The chip MAX232 (16 pin) or MAX233 (20 pin) (not pin compatible) is used to transfer the voltages

• The bit rate and the Baud rate are different, the baud rate is modem terminology (signal changes per Second) with standards of 2400,… 9600,……56Kbps….

Baud rate setting

• Machine Cycle Frequency = Xtal frequency / 12 =11.0592 / 12 = 921.6 KHz

• UART to timer 1 = 921.6 / 32 = 28.8 KHz• a) 28.8 / 3 = 9.6 K ;with –3=FDH loaded TH1• B) 28.8 /12=2.4 K ;with –12=F4H loaded TH1• SBUF register is the one responsible for serial

MOV SBUF, # ‘D’ ;load SBUF=44H, ASCII for ‘D’

MOV SBUF, A ; copy from accumulator

MOV A, SBUF ; copy reception to accumulator

SCON Serial Control Register

• SM0 SCON.7 ;serial port mode specifier• SM1 SCON.6 ;serial port mode specifier• SM2 SCON.5 ;multiprocessor comm (0)• REN SCON.4 ;set/clear to enable/disable Rx• TB8 SCON.3 ;not widely used• RB8 SCON.2 ;not widely used• TI SCON.1 ;Tx interrupt flag, must be clr• RI SCON.0 ;Rx interrupt flag, must be clr

TI flag is important to monitor to insure proper transmission when adding the stop bit to the 8 bit

Serial Mode Code

SM0 SM1

0 0 ;Serial Mode 00 1 ;SM 1, 8 b, 1 start bit ; & 1 stop bit1 0 ;Serial Mode 21 1 ;Serial Mode 3

Transfer ‘YES’ SeriallyMOV TMOD,#20H ;timer1, mode2MOV TH1,# -3 ;9.6 K BaudMOV SCON,#50H ;8bit,stpb,REN enbSETB TR1 ;start timer 1AGAIN: MOV A,#”Y” ;transfer YACALL TRANS MOV A,#”E” ;transfer EACALL TRANSMOV A,#”S”ACALL TRANSSJMP AGAIN ;keep sending YESTRANS: MOV SPUF,A ;load SPUFHERE: JNB T!,HERE ;wait for last bit transferCLR TI ;get ready for next byteRET

8051 Programming to Receive Data serially

MOV TMOD,#20H ;timer 1, Mode2, ;Auto ReloadMOV TH1,#-6 ;4800 baudMOV SCON,#50H ;8 bit,1 stop,RENSETB TR1 ;start timer 1HERE: JNB RI,HERE ;wait for char inMOV A,SBUF ;save in byte to AMOV P1,A ;send to port 1CLR RI ;get ready to Rc next byteSJMP HERE ;keep getting data

Serial PC Communications, LEDs at P1and SW at P2 - 1

ORG 0MOV P2, #0FFH ;make P2 inputMOV TMOD, #20H ;Timer 1 Mode 2, ;Auto ReloadMOV TH1,#0FAH ;4800 BaudMOV SCON,#50H ;8 bit, 1 stp, RENSETB TR1 ;start timer 1MOV DPTR, #MYDATA ;Load PTR H_1: CLR AMOVC A,@A+DPTR ;get the characterJZ B_1 ;if last character get outACALL SEND ;otherwise call transferINC DPTR ;next oneSJMP H_1 ;Stay in loop


B_1: MOV A,P2 ;Read on P2ACALL SEND ;Transfer SeriallyACALL RECV ;get serial dataMOV P1,A ;Display on LEDsSJMP B_1 ;Stay in loop;………….Serial data transfer from ACCSEND: MOV SBUF,A ;load dataH_2: JNB T1,H_2 ;stay here till last bitCLR T1 ;get ready for next charRET ;return to caller


;………….Receive data serially in ACCRECV: JNB RI,RECV ;wait for charMOV A,SBUF ;send to AC CLR RI ;get ready for charRET ;return to caller;…………the MessageMYDATA: DB “we are ready”,0END

Use of PCON register D7 (SMOD) to double the BAUD rate

PCON is not a bit addressable then:

MOV A,PCON ;copy PCON to ACCSETB ACC, 7 ;make D7 = 1MOV PCON,A ;now SMOD=1

;mach cycle frequency = 11.0592/12 = 921.6 KHz;Baud rate = 921.6 / 16 = 57.6 KHz (was 28.8 KHz)

Example for serial transmission

MOV A,PCON ;A=PCONSETB ACC,7 ;make D7=1MOV PCON,A ;SMOD=1, Double baudMOV TMOD,#20H ;timer1 mode2, ;auto reloadMOV TH1,-3 ;Baud rate 19.2 KHzMOV SCON,#50H ;8 bit, 1 stop, RI EnSETB TR1 ;start timer 1MOV A,#”B” ;transfer letter BA_1: CLR T1 ;make sure T1=0MOV SBUF,A ;transfer itH_1: JNB T1 H_1 ;stay till last bit is goneSJMP A_1 ;keep sending B

Registers of Timers

TH0-TL0 2 8 bit registers at addresses 8C-8AHTH1-TL1 2 8 bit registers at addresses 8D-8BHTH2-TL2 2 8 bit registers at Addresses CD-CCHTMOD 8 bit register at 89H address, 4H bits for T1 and 4L bits for T0, (GATE), (C/T),(M1),(M0)M1,M0 determine the 4 modes 0 13 bit timerMost usable 1 16 bit timerGATE = 0, using TRx bit SET or CLR 2 8 bit timerGATE = 1, using ext time intr(p3.4,3.5) 3 split modeC/T is counter/timer modes, the first uses external clock

TCON timer/counter register

• TF1 TCON.7 overflow flag for T1• TR1 TCON.6 Timer 1 run control bit• TF0 TCON.5 overflow flag for T0• TR0 TCON.4 Timer 0 run control bit• IE1 TCON.3 External Interrupt 1 edge Flg• IT1 TCON.2 Interrupt 1 type control bit• IE0 TCON.1 External Interrupt 0 edge Flg• IT0 TCON.0 Interrupt 0 type control bit

Bit addressable register at address 88H

Data from P1 sent to P2 and serial port data sent to P0, xtl 11.0591 M

ORG 0LJMP MAINORG 23HLJMP SERIAL ;jump to serial ISRORG 30H MAIN: MOV P1,#0FFH ;P1 inputMOV TMOD,#20H ;timer 1 mod 2, autMOV TH1,#0FDH ;9600 baud rateMOV SCON,#50H ;8bit, 1 stop, REN EnMOV IE,#10010000B ;enable serial interSETB TR1 ;start timer1

Data from P1 sent to P2 and serial port data sent to P0, xtl 11.0591 M

BACK: MOV A,P1 ;read from P1MOV P2,A ;send data P2SJMP BACK ;stay in loop;…………..Serial Port ISRORG 100HSERIAL: JB TI,TRANS ;jump if TI highMOV A,SBUF ;otherwise due RxMOV P0,A ;send to P0CLR RI ;CPU not clearingRETI ;return from ISRTRANS: CLR TI ;CPU not clearingRETI ;return from ISREND

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