Micro Controller

SYLLABUSEC 401 MICROCONTROLLERS AND APPLICATIONS

Contact Hrs. / Week: 4 Hrs Contact Hrs. / Semester: 64 Hrs.

CONTENTLIST AND TIMEALLOCATION

CONTENTS

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Chapter No. Contents No. of Hours

1 Introductionto Microcontrollers 4

2 Architectureof MCS8051 8

')a 3 Introduction to Advanced Microcontrollers 2

">64 Introduction to PIC Controllers 6

5 Program Development Tools 4

Instruction Set of 8051 16

"1<7 Hardware Features of 8051 and Programming 12

8 Applications of 8051 12

TOTAL 64

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CONTENTS

CHAPTER -1 INTRODUCTION TO MICROCONTROLLERS 1-15

Block diagram of microcomputer, microprocessor and microcontrollerMicrocontroller types -embedded, external memory, Harvard and PrincetonRISC and CISC architectures.

Microcontroller memory typesEvolution of microcontrollers - 4-bit, 8-bit, 16-bitand 32-bit

CHAPTER - 2 ARCHITECTURE OF MCS 8051 16-34

Introduction to MCS 8051 family

Pin diagram of 8051 with functions

Block diagram of 8051 with details of GPR, PC, data pointer, flags, PSW, SP,SFR, I/O ports, counter /timer, serial I/O, data memory, program memory, registerbanks and stack

~ CHAPTER-3 INTRODUCTIONTO ADVANCEDMICROCONTROLLERS 35 -44

-f-Features of MCS-96 family

Features of MCS-251 family

CHAPTER -4 INTRODUCTION TO PIC CONTROLLERS 45-53

r Introduction to 16F74

Architectural detailsand block diagramof 16F74-CPU, registers,data memory .

and program memory

CHAPTER -5 PROGRAM DEVELOPMENT TOOLS 54-62

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Definitions of instructions, program and software

Machine instruction format, addressing modes and types

Tools - Assembler, linker, loader and compiler

Flowchart and algorithm

Assembly instruction format

8051 data typ~s and directives

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CHAPTER -6 INSTRUCTION SET OF 8051 63 -82

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Instruction classification -Data transfer, Arithmetic, LQgical, Boolean and Branchgroups .

Details of each instruction with examples

CHAPTER -7 HARDWARE FEATURES OF 8051 ~ND PROGRAMMING 83 -110

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Programming model of the 8051

I/O port programming

I/O bit manipulationBit addressable RAM

Single bit operation with carry

Counter/timer programming in the 8051

Interrupts programming

Programming the serial communication interrupt

Interfacing external memory

CHAPTER -8 APPLICATIONS OF 8051 111-126

Programmable peripheral interface (8255A)

8051 interfacing

Switch / LED / relay / buzzer / optocoupler interface

Analog to digital converter (ADC) interface

Stepper motor interface

Digital-to-analog converter (DAC) interface

LCD (liquid crystal display) interface

Hex keypad interface

APPENDIX A -SAMPLE PROGRAMS 127 -133

MULTIPE CHOICE QUESTIONS

MODEL QUESTION PAPERS

134-137

138 --139

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INTRODUCTION TO MICROCONTROLLERS

. ,BLOCK DIAGRAM OF MICROPROCESSOR

The microprocessor is a general-purpose single-chip central processing unit(CPU) of a digitalcomputer. It is a semiconductor device consisting of electronic logic circuits manufactured by usinglarge scale Integration (LSI) or very large scale integration (VLSI) technique. The microprocessor iscapable of performing various computing functions and making decisions to change the sequence ofprogram execution. The main use of a microprocessor is to fetch data, perform extensive calculationson that data and store those calculations in a mass storage device or display the results for humanuse. The programs used by the microprocessor are stored in the mass storage device and loadedinto RAM as the user directs. A few microprocessor programs are stored in ROM. The ROM-basedprograms are primarily small fixed programs that operate peripherals and other fixed devices that areconnected to the system. To make a complete microcomputer, one must add memory, usually read-only program memory (ROM) and random-access data memory (RAM), memory decoders, anoscillator and a number of input/output (I/O) devices, such as parallel and serial data ports. Additionally,special-purpose supporting devices, such as interrupt handlers or counters, may be added.

Address bus Control busDatabus

MARControl

IR . \ Flag Register \[

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PC

SPALU

Interrupt circuits n general purposeregister

Fig. 1.1: Block diagram of a microprocessor

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Introduction to Microcontrollers 3

stack only. This end is usually called the top of the stack. The stack pointer is a register used as amemory pointer. It contains the address of the current top element of the stack.

Memory Address Register (MAR)

The MARis used to hold the addressof the locationto or from which data are to be transferred.

Interrupt Circuits

Normalexecution of the program maysometimesbe disturbed if some device requiresurgentservicing.Toachieve this, the device can raisean interruptsignal. An inter' u t from theinput/out utdeviceforse,ryJceb...!b~J2r"~;tc;~ssQr.Interrupt circuits han e sue requ~sts. The proces$orprovides the requested service by executing an a£E!£E!iate interrupt service routine (ISR).- "'! ~. l' ~, -~ ~ ";:;:::'

Memory Data Register (MDR) .

The MDR contains the data to be written into or read out of the addressed location.... . ~ -~. --- -

Bus Structure

The universal feature in all microprocessors is bus structure. The microprocessor has an internalbus. All the hardware functional units inside a microprocessor are connected to the internal bus

. consisting of

(a) Address bus

(b) Data bus

(c) Control bus

Addrcss Bus

The address bus consists of 20, 24 or 32 parallel signal lines. On these lines the CPU sends

~ the address of the-.!!I~mory 109atioo that is to be written or to be read from. Address bus!su.oidirec1l9n;;T--. . ~ .. - -"DataBus ,.

The data busconsistsof 1J.IJ6.!..~~ or £?411§.rall§1signal lines.The data bus lines arebidirectional.This means that th.e.~~ r~pjs_!~t€lJ'!.9Q~!~f?S¥line~JLoTmerno~ or from a p~rt as ~Ssends"data out on these lines to a memory location or to a port. . .-~ . "" - ,~ -- - --ControlBus

The CPU sends out.signals_Qnthe cont(ol busto enabL~.~h~<2utput~otaddress§d memorydevicesor port devices.Typical control b~aJ§ 9r~Memory Read, MemoryWrite, I/O ReadandTioWrite.-- - - -~' " -. --- - --

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-- --BLOCK DIAGRAM OF MICROCOMPUTER

As shown in Fig. 1.2, every computer system hasthree basic units:

(1) Centralprocessing unit

(2) Memoryunit

(3) Input/Outputunit.

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4 Microcontrollers and Applications

Data bus Mem 0ry unitInput / Outputr

Address bus

Fig. 1.2: Block diagram of microcomputer

Central Processing Unit

Microprocessor is also called central processing unit (CPU) because it can be designed to dothe functions as the central processing unit in a large computer. The Central processing unit (CPU)does arithmetic operations like addition, subtraction, multiplication, division, comparison and logicoperations such as AND, OR and XOR. It also regulates the operation of the complete machine. Itfetches and interprets and it causes certain parts of the circuitry to respond according to thoseinstructions. The CPU can be considered as the nerve element of the computer's brain.

M'rJ1ory Unit

The memory unit stores programs, data, calculations and results. Two types of memory areincluded in the computer:

(a) Temporary memory called random-access memory (RAM)

(b) Permanent memory called read-only memory (ROM).

RAM is sometimes called "main memory". Information stored in RAM exists only as long aspower is applied to the computer. When power is removed, the programs and data stored in the RAMare lost unless copied to external permanent memory.

The ROM chips are permanently programmed with computer instructions and special data.They are referred to as "firmware" because software is embedded into the hardware.

External memory can be attached to the computer by connecting floppy disk drives or hard diskdrives.

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Input I Output Unit

User communicates with the computer through the input and output units. These user interfacesare called "peripherals". A peripheral is any type of device connected to the basic computer. An inputunit allows commands, programs and data to enter the computer. Keyboards, joysticks, game paddles,graphics tablets, light pens, microphones and analog to digital converters (ADCs) are examples ofinput devices.

The computer communicates with our environment and us via an output unit. Monochrome andcolour displays, printers, plotters, speaker and digital to analog converters (DACs) are examples ofoutput devices,

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s Introduction to Microcontrollers 5

Some devices are used for both input and output. These include the mass storage devices (thefloppy disk drives, the hard disk drives, and archival storage tape systems) and MOdulatorDEModulators (MODEMs) which enable computer to computer communication over long distances.

BLOCK DIAGRAM OF MICROCONTROLLER

Reset Input &outputpins

Power

Clocking

Fig. 1.3: Block diagram of microcontroller

Fig. 1.3 shows the block diagram of a typical microcontroller. It is a true computer on a chip.The design incorporates all of the features found in a microprocessor CPU: ALU, PC, SP and registers.It also has other features needed to make a complete computer: ROM, RAM, parallel 1/0, serial 1/0,counters and a clock circuit.

Like the microprocessor, a microcontroller is a general-purpose device, but one which is meantto fetch data, perform limited calculations on that data and control its environment based on thosecalculations. The prime use of a microcontroller is to control the operation of a machine using a fixedprogram th9tf§; stored in ROM and that does not change over the lifetime of the system. '

... The desig~ approach of the micro controller is similar to that of the microprocessor. Themicroprocessor design accomplishes this goal by having a very flexible and extensive set of multi-pYle instructions. These instructions work in a hardware configuration that enables large amounts ofmemory and I/O to be~connected to address and data bus pins on the integrated circuit package.Much of the activity in the microprocessor has to do with moving code {lnd data words to and fromexternal memory to the CPU. The architecture features working registers that can be programmed totake part in the memory access process and the instruction set is aimed at speeding up this activityin -order to improve throughput. The pins that connect the microprocessor to external memory areunique, each having a single function. Data is handled in byte or larger sizes.

The microcontroller design uses a much more limited set of single- and double-byte instructionsthat are used to move code and data from internal memory to the ALU. Many instructions arecoupled with pins on the integrated circuit package; the pins are Hprogrammable" - that is, capable ofhaving several different functions depending upon the wishes of the programmer..

.Power Control

,. distribution store

Reset ...0 C/)

controlC/) /'C/) t '.......

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timingRAM


DIFFERENCESBETWEENMICROPROCESSORANDMICROCONTROLLER

Table.1.1 showfi he differencesbetween microprocessorand microcontroller

Table. 1.1: Differences between microprocessor and microcontroller

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MICROCONTROLLERTYPES

EMBEDDED MICROCONTROLLERS

When all the hardwar~ required to run the appHc,C!!iQD~provided on the mlcrocontroller chip, itis referred to as an ~~rT1beddedmlcrocOntroller. Fig. 1.3 shows the block diagram of an embeddedmicrocontroller. Power, reset and clock are required to operate the device. I/O pins are provided toallow the interfacing with external devices. .--.

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Merits

.:. Embedded microcontrollers are cheaper

.:. They are much more precise and easier to control

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Microprocessor Microcontroller

Microprocessorshave many operationalcodes Microcontrollersmay have one or two opcodes(opcodes) for moving data from external for moving data from externill memory to thememory to the CPU CPU

Microprocessors have one or two types of Microcontrollershave manytypes of bit-handlingbit-handling instructions instructions

Microprocessor is concerned with rapid Microcontroller is concerned with rapidmovement of code and data from external movement of bits within the chipaddresses to the chip

Microprocessor must have many additional Microcontroller can function as a computerparts to function as a computer without the addition of external parts

Microprocessors are intended to be general- Microcontrollers are intended to be special-purposedigital computers purpose digital controllers

Microprocessors contain a CPU, memory Microcontrollers have additional features such

addressing circuits and interrupt handling as on-chip timers, parallel and serial I/O andcircuits internal RAM and ROM

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5Introduction to Microcontrollers 7

EXETRNAL MEMORY MICROCONTROLLERS

Fig. 1.4: Eternal memory microcontro/lers

External memory microcontrollers allow the connection of external memory as shown inFig. 1.4. The design emphasis is on high-speed computation features r~ther than on-chip features,such as RAM and ROM., The difference between microcomputers and microcontrollers becomes

very fine here. The e~ternal memory microcontrol~e.rqjffers trom a miGroproce~~9r.in ~hearea of built-inperiphei"al features such as timers, interrupt contl'ollers, QMA and I/O devices~The _E!~ernalmemory

DUS -can be used to ~_d9r~s meJ!1.o!YQ1appeg 110 devices ~ ~xe~nd thELcapil"Qilities of themicrocontroller significantly. When external memory is used with tti~ micJ.Q~ntr()!ler, all the built-innanrware Tnterfates can also beacceSSed. This featuremakes the microcontroller flexibletor different

applications. --,

MICROCONTROLLER ARCHITECTURES .

PRINCETON (VON NEUMANN) ARCHITECTURE

Fig. 1.5 shows the block diagram of Princeton architecture. It has COlDDlO..!l.l1lernoryfor storing

instructi?n as well as data. ThE!memory interfac.e unit is responsible for deciding wt}~ther.The..!!l~rnory'access -isfor instruction fetch or data transfer. The processing speed can beTncreased by using thecQ!Jfept of prefetching:"Wlffi1hiscO'ncept, the time required to execute an Tnstruction can be utilizedto fetch the next instruction. - - ., -" ~-.- ,

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Fig. 1.5: Princeton (Von Neumann) architecture

Addressbus ...,

.Micro contro lier Control bus RAM/ROM..., ...... ,...

Data bus- ,...

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CPU

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Merits

.:. Princeton architecture simplifies the microcontroller chip design because only one memory isaccessed.

.:. Random access memory (RAM) can be used for both instruction and data storage.

.:. Availability of program counter stack contents allows greater flexibil~ty in developing software.

HARDVARD ARCHITECTURE

Fig. 1.6 shows the block diagram of Harvard architecture.J1.Y.§J~.~_~eparatememory banks ,forstoring instruction and data. Harvard architecture executes instructions in fewer irlstruction cycles;-_. ""

than the Princeton architecture because of instruction parallelism. Instruction parallelism can bedefined as a technique of simultaneous issue and processing of multiple instructions within a singleprocessor(CPU). -~ ...

Fig. 1.6: block diagram of Harvard architecture

Merits

.:. Harvard architecture executes instructions in fewer instruction cycles than the Princetonarchitecture because of instruction parallelism

.:. Harvardarchitecture is suitable for real-timeapplications~ -

RISC AND CISC ARCHITECTURES

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CISC stands for Complex Instruction Set Computer. CISC has large instruction sets, multipleaddressing modes and multiple instruction formats and sizes. Their control is microprogrammed anddifferent instructions take different number of cycles to execute. The control units are complex.

RISC stands for Reduced Instruction Set Computer. RISC has relatively less instructions,addressing modes and instruction formats. As a result, a relatively small and simple decoding andexecuting hardware subsystem of the CPU is required. The chip area dedicated to the control unit isless. There is more area available for other features. In RISC systems, stroamlined operation isaccomplished by standard, fixed size of the instruction (equal to the word length and to the width ofthe data bus) and single-cycle execution of all instructions.

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RiseVERSUS CISC

Table. 1.2 shows the comparison between RISC and CISC.

RISCRISC stands for Reduced Instruction Set~uterRISC has relatively less instructions,addressing modes and inStruction formats.As a result, a relatively small cmd~simPledecoding and execu~ hardwaresubsystemof the CPU is required.The chip area dedicated to the control unit"isless. There is more area available for otherfeatures. ----§lmpler ang sm'aUer~controlunit results inre9\;!~d number of design errors and higherreliability.

RISC design approach is ..2.ujt,€iJ?I~forefficient handling~elinesThrougb.putis more.It takes a shorter time to complete thedesign of a RiSe control unit. Due to shortE2.rdesign time, the chances of the end productbecoming obsolete are 1El§.S.-Overall design cost of RISC control unit isless~ ..

Because of the simplicity, I~s number ofinstruction formats and standard instructionlengths, design of -virtual memorymanagement subsystem is easier.Since the total number of instructions in a

. R~SCsystem is §!pa,lI, con;:!2ilerdesign is! . I simple.r. RISC instruction - set presents aI r~ burden on the compiler

The availability of a relatively lQr:.9.enumberof CPU registers in a RISC permits a moreefficient code optimization stage in acompiler.RISC compiler is :?imRIEtr.-

CISCCISC stands for Complex Instruction Set~puterRISC has relatively more instructions,addressing modes and instruction formats. Asa result, a relatively large and complexdecoding and executing hardware subsystemof the CPU is required.The chip area,dedicated to the control unit ismore. There is less area available for otherfeatures.More complex and larger control unit resultsin increased number of design errors andreduced reliability.CISC design approach is not suitable forefficient handling of pipelinesThroughput is less.It takes a longer time to complete the designof a CISC control unit. Due to longer designtime, the chances of the end productbecoming obsolete are more.Overall design cost of CISC control unit ismoreBecause of the complexity, more number ofinstruction formats and different instructionlengths, design of virtual memorymanagement subsystem is difficult.Since the total number of instructiCISC system is larg~, Gompilerdesigcomplex. CISC instruction set preincreasedburden on the compiler.CISC system d,gesnqt .provide as mregisters as in RISC. Therefore, itpermit efficient code optimization scompiler. .

CISC compiler is complex

Table.1.2: RiSe versus CISC

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10 Microcontrollers and Applicatiom

MICROCONTROLLER MEMORY TYPES

The microcontroller memorycan becategorizedas:

(1) Controlstorage(2) Variablestorage

CONTROL STORAGE

Control storage is also known as program memory and firmware. Information stored in non-volatile memory remains intact even if the electricq'!'power is turned off. ~on-v9IatiIe memory is usedf6r permanent storaQ..e.The non~ratile memory is known as read only memory (ROM). I! is a broad

-class of semiconductor m-emor~es designed for applications where the ratio of read ~perations towrite operations is very high. A ROM can b~ written into (programmed) only once. Thereafter informationcan only be read from the memory. Tne write operation is more complicated than the read operation.The ROM chips are permanently programmed with computer instructions and'special data... -.. -

TYPES OF CONTROL STORAGE

The following different types of control store may be available in a microcontroller:

Mask ROM (MROM)

The mask ROM is the type in which data are permanently stored in the memory during themanufacturing process.

Programmable ROM (PROM)

The PROM is the type in which the data are electrically stored by the user with the aid ofspecialized equipment.

Erasable PROM (EPROM)

The EPROM is a MOS (metal oxide semiconductor) device. The EPROM is electricallyprogrammable by the user, but the stored gcya9an be e(ased either by expo~ure to UV (Ultraviolet)light or by electrical means. The latter type is called an EEPROM (Electrically Erasable PROM) orEAPROM (Electrically Alterable PROM).

Flash Memory

. Flash memory is a QQ!J:Y..oJatilememorv.haLq,anbeelectricallyerased and reprogrammed.It is, a specific type of ~EPROM.that is erased and programmedin large blocks. Flash memorycosts farless than byte-programmable EEPROM.

VARIABLE DATA STORAGE

Yolatile memory rEttCiinsstoreq_i~formation C!.s~loQ~s electrical power supply is on. If theelectrical power is removed, all information stored in the memory wiWb~ lost. Many semiconductormemories are volatile. Volatile memory is used for temporary storage. Volatile memory is referred to.. -as random access memory (RAM) and can be read from and written to by the microcontroller(sprocessor.

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Introduction to Microcontrollers 11ns

TYPESOF VARIABLE DATA STORAGE

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The following different types of variable data storage are available in a microcontroller:.....

(1) ~its: Single flip-flops ~re called bits. Bit manipulation is efficient and faster.(2) Registers: a-bit (byte) locations accessed by the processor are called registers. The.§~!equire.. - ~ . -

special instructions or addressing modes. < - . .- ---(3) Variable RAM: Temporary storage space used for saving and accessing data in a random

fashion. It is also known as scratchpad RAM. - "-.-(4) ~rogram counter stack: A stack, also knowJJ...aslasJin first out (LIFO), can be thought of as a

s.etof registers, one on top of another. Each register can store one value. A stack is a data --.-- - - ,structurewith two principal operations,~USHand'pOP.A PUSH operation pla~e7anewval~eon top of the stack. The prior top level becomesthe seconq level. A.ppP operatiQndoes the- I

-opposite.It readsthe value fromthe top level,andthen removesit so that the prior second leveloecomes the new top level. Stack is used to store addresses and data while a subprogram

. -- ... ~ -EfXecut~s.

All variable storage is implemented as static random access memory (SRAM). The storageelements used in the static memory are latches, so data can be stored for an indefinite period of timeas long as the power is on. Memory refreshing is not necessary.

MICROCONTROLLER VOSPACE

Input-output (I/O) devices are the means through which the microcontroller communicateswith the outside world. Because more than one device is usually connected to a computer, somemeans have to be provided by which a particular device can be selected to participate in a givenoperation. There are two schemes for addressing I/O devices:

(1) Memory mapped I/O scheme

(2) °1/0 mapped I/O (Isolated I/O) scheme

MEMORY MAPPED I/O SCHEME

In memory mapped I/O scheme there is only one address space. I/O devices are identified byassigning them unique addresses within the memory address space of the computer. Thus it becomespossible to access I/O devices in the same way as any other memory location. Any instruction thatmoves data to or from a memory location can be used to transfer data to or from an I/O device. Theuse of memory mapped I/O offers considerable flexibility in handling I/O operations because anymachine instruction and addressing mode that can be used to deal with memory operands can aisorefer to an I/O device.

I/O MAPPED I/O (ISOLATED I/O) SCHEME

Inthis scheme there are two address spaces: (a) memory address space and (b) I/O addressspace. In this scheme the addresses assigned to memory locations can also be assigned to I/Odevices. I/O transfers may be distinguished from Memory Read and Write operations by including aspecial I/O control line such as 10/ on the bus. Special instructions such as IN and OUT are neededto perform I/O transfers. The IN instruction may be used to read the data from an input device. TheOUT instruction may be used to send data to an output device.

:f12 Microcontrollers and Applications

EVOLUTION OF MICROCONTROLLERS

Microcontroller models vary in data size from 4 to 32 bits. Four-bit units are produced in hugevolumes for very simple applications and a-bit units are the most versatile. Sixteen- and 32-bit unitsare used in high-speed control and signal processing applications. Many .models feature programmablepins that allow external memory to be added with the loss of I/O capability.

4-BIT MICROCONTROLLERS

In four-bit microcontrollers, the word-bit count is 4. Pin count and package size are reduced tominimize the cost. It still allows the implementation of useful intelligence. 4-bit microcontrollers arethe most popular today. 4-bit microcontrollers are intended for use in large volumes as true 1-chipcomputers.

Applications

.) Appliances

.:. Toys

a-BIT MICROCONTROLLERS

Eight-bit microcontrollers are suitable for ~<l!Lcomputjng tasks and control and monitoring_9P..EI!9~i9ns.ASCII data is stored in byte sizes. Therefore, a-bit word size is the natural choice fordata communications. Most integrated circuit memories and many logic functions are arranged in ana-bit configuration that interfaces easily to data buses of a bits.

Applications of eight-bit microcontrollers can range from simple appliance control to high-speedmachine control and data collection. Different microcontroller manufacturers offer different amountsof internal ROM-and RAM. Memory can be expanded to include off-chip ROM and RAM. In somecases the ROM is an Electrically Reprogrammable Read Only Memory (EPROM). The EPROM

.vers~ons can be us~d by the designer in the research and development stage of a product. After thedesign is finalized, ROM version can be ordered in large quantities. EPROM design is suitable incase the configuration is changed frequently or production volumes are less. Some microcontrollersuse fewer external pins to reduce the package size and the cost. Special features' such as analog-to-digital (AID) and digital-to-analog (D/A) converters may be included on the chip.The pulse widthmodulation (PWM) output is useful for controlling motor speed; it can be done using software in thea-bit units. .Applications

.:. Simple appliance control

.:. High-speed machine control

.:. Data collection

16-BIT MICRO CONTROLLERS

.......

Sixteen-bit microcontrollers are suitable for high-speed control such as control ofservomechanisms or for digital sign~1processing (DSP) applications. The 16-bit controllers havebeendesignedto take advantageof high-levelprogramminglanguagesin sophisticatedapplications.

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Applications

.:. Control of servomechanisms such as robot arms

.:. Digital signal processing (DSP)32-BIT MICROCONTROLLERS

Thirty two-bit microcontrollers are suitable for environments in which application programs rununder an operating system. The design emphasis is on high-speed computation features ratherthan on-chip features, such as RAM, ROM, timers and serial ports. The line betweenmicrocomputers and microcontrollers becomes very fine here. The 32-bit controllers have beendesigned to take advantage of high-level programming languages in sophisticated applications.These microcontrollers are called as "embedded controllers" by some manufacturers. Functionsneeded for I/O, data communications and timing and counting are done by adding supportingchips.Applications

.:. Robotics

.:. Highly intelligent instrumentation

.:. Avionics

.:. Image processing

.:. Telecommunications

.:. Automobiles

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IMPORTANT POINTS

(... The microprocessor is a general-purpose single-chip central processing unit (CPU) of a digitalcomputer.

(... The microcontroller is a true computer on a chip. It has features such as ROM, RAM, parallel 1/0, serial I/O, counters and a clock circuit in addition to those found in a microprocessor.

(... When all the hardware required to run the application is provided on the microcontroller chip, itis referredto as an embedded microcontroller. .

I'" Princeton (Von Neumann) architecture has common memory for storing instruction as well asd~a. i

(... Harvardarchitectureuses separate memorybanksfor storing instructionand data. Itexecutes/

instructions in fewer instruction cycles than the Princeton architecture.

r... CISC stands for Complex Instruction Set Computer. CISC has large instruction sets, multipleaddressing modes and multiple instruction formats and sizes. .

I'" RISC stands for Reduced Instruction Set Computer. RISC has relatively less instructions,addressin,g modes and instruction formats.

(... Control storage is also known as program memory and firmware. It is non-volatile.

r... Volatile memory is referred to as random access memory (RAM) and it is used for variablestorage.

(.- In memory mapped I/O scheme there is only one address space. I/O devices are identified byassigning them unique addresses within the memory address space of the computer.

(... In I/O mapped I/O (isolated I/O) scheme, there are two address spaces: (a) memory addressspace and (b) I/O address space. In this scheme the addresses assigned to memory locationscan also be assigned to I/O devices.

REVIEW QUESTIONS

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Objective Type1. The2.3.4.5.6.

is a true computer on a chip.

architecture has common memory for storing instruction as well as data.

architecture uses separate memory banks for storing instruction and data.

microcontroller consists of all the hardware required to run the application.

I/O scheme, there is only one address space.

I/O scheme, the addresses assigned to memory locations can also be assigned

In .

In -to I/O devices.I.....

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Answers

1. microcontroller4. Embedded

2. Princeton (Von Neumann)

5. memory mapped

3. Harvard

6. I/O mapped I/O(isolatedI/O)

Descriptive Type

1. Explainwhy EPROM versions of microcontrollers exist. (2)

2. List four major differences between a micropr?cessorand a microcontroller. (4)3. List four major differences between RISC and CISCo (4)4. List some applications of microcontrollers. (4)

5. Write a short note on microcontroller memory types. (5)6. With the help of block diagrams distinguish between Princeton (Von Neumann)and Harvard

architecture. (6)

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ARCHITECTURE OF MCS 8051

INTRODUCTION TO MCS 8051 FAMILY

The 8051 microcontroller actually includes a whole family of microcontrollers that have numbersranging from 8031 to 8751 and are available in N-Channel Metal Oxide Silicon (NMOS) andComplementary Metal Oxide Silicon (CMOS) construction in a variety of package types. 8052 is anenhanced version of the 8051. All the features of 8052 are the same as that of 8051 except thefollowing: (a) Internal ROM: 8KB, (b) Internal RAM: 256B, (c) Timers: 03 and (d) Interrupt sources: 08

FEATURES OF 8051 MICROCONTROLLER

The 8051 architecture consists of the following specific features:

(1) Eight-bit CPU with registers A (the accumulator) and B

(2) Sixteen-bit program counter (PC) and data pointer (DPTR)

(3) Eight-bit program status word (PSW)

(4) Eight-bit stack pointer (SP)

(5) Internal ROM of 4KB

(6) Internal RAM of 128 bytes:

(a) Four register banks, each containing eight registers

(b) Sixteen bytes, which may be addressed at the bit level

(c) Eighty bytes of general-purpose data memory

(7) Four flags

(8) Thirty-two input/output pins arranged as four 8-bit ports: PO- P3

(9) Two 16-bit timer/counters: TO and T1

(10) Full duplex serial data receiver/transmitter: SBUF

(11) Control registers: TCON, TMOD, SCON, PCON, IP and IE

(12) Two external and three internal interrupt sources

(13) Oscillator and clock circuits

..,

- =:1

Architecture of MCS 8051 17

BLOCKDIAGRAMOF 8051 MICROCONTROLLER

Fig. 2.1 and 2.2 show the simplified and detailed block diagram, respectively, of 8051microcontroller. It consists of the following important functional blocks:

(1) Central processing unit (CPU)

(2) Intemal memory

(3) Special function registers (SFRs)

(4) Timers / Counters

(5) Serial port

(6) Interrupt control

(7) I/O ports

(8) Oscillator and clock

Central Processing Unit (CPU)

. I

The CPU of 8051 does arithmetic operations like addition, subtraction, multiplication, division,comparison and logic operations such as AND, OR, XOR, rotate, cleat and complement. The CPU iscan perform bitwise and bytewise manipulations.

Internal Memory

The internal memory stores programs, data, calculations and results. The 8051 has twotypesof internal memory: (a) Random access memory (RAM) or data memory and (b) Read onlymemory(ROM)or program memory.The 8051 hasseparate address spaces for data and program,.memory.

RandomAccessMemory(RAM)Theintemal RAMis of 128 bytesrangingfrom OOHto 7FH. It is also refenedto as datamemory.

ReadOnlyMemory(ROM)The intemal ROMis of 4KB ranging from OOOOHto OFFFH.It is also referred to as program

memory.

,.

,.

r' .J

I II I

I II

I

External Interrupts

InterruptControl

4KROM

InterruptControl

Osc Bus control

I I. -

Fig. 2.1: Simplified block diagram of 8051 microcontroller

128RAM

Four 110Ports

PO P2~Address I Data

P1 P3

Timer 1

Timer 2

SerialPort

fTXDRXD

L..Q,)(J).....c ~~c.0 c

_0-

~

......())

~n....0n0:J-+a(1)~Q:JCL»"'0"'0nQ=.0:J(I'J


IIiIIIIII1II..

IPSEN- :z-I go::

ALE/PROG-' TIMING t!;;-. 1 AND ::::I<5EANPP I CONTROL !;; ~

RST - ~I

1

I

I

I

I

1 XTAL1

L-

I

I

VsVSS1

-G-:"I

1IIII

I

SFRsTIMERS

PRQG.RAMADDRESSREGISTER

BUFFER

PCNCREMENTE

osc

XTAL2

------ ----------

DATA:SMULTIPLE

-----------

Fig. 2.2: Detailed block diagram of 8051 microcontroller

Special Function Registers (SFRs)

n1

P1.0-P1.7 P3.0 - P3.7

IIIIIIIIIIIII

IIIIIIIII

61IIIIIIIIIIIIIII

The 8051 has several special function registers (not shown in the block diagram) designated asA, 8, DPTR, PSW, IP, IE, TCON, SCON, PCON, Po' P1, P2,P3' S~UF etc. All these are..!?~.address~le andsome of them.are bitaddressablealso.The SFRscan be accessed by their namesQ'rbytheir addresses ranging from 801i to FFH. These are useful in accessing I/O ports, timers/counters.,serial port, power controlling etc.~Someof the addressesfrom 80H to FFH are notdefined, 0' ,.,

for SFRs. Attempting to use such addresses maycause unpredictable results. . .--- -;- ~ ~1

'f;;W "rI..,

\1

\III

, I

I~1\II

~

; I


Counters and Timers

Manymicrocontrollerapplications require the counting of external events or the generation ofprecise internal time delays be~een events. Both of these tasks can be accomplished using softwaretechniques. But software loops for counting or timing consume processor time so that more importantfunctions are not done. To relieve the processor of this burden,~w.2..12-mtup.counter~, ~amed TOandT1 , are provided. Each collnter may be programmed to act qS a !imer to count internal clock P~Jse-sor-asa counferto counfextemal pulses,} The counters are diviaed into two 8-bit registers called the

t!.m~~!~JTLO, TL 1) ~!1d l]igb.~<!Hg, J"IjJJ Bytes. AU,counter actlo,n IS confrontefby b!t states in t~timer mode control register (TMOD), the timer/counter control register (TCON) and certain prograrrfinstructions.~-' -- - t"" - - - ~ ~e::-- - -..Serial Port

The 8051 communicates ~ith other devicE?s by sending anq receiving da_ta121tsseri2-lIy using ac

~e:~aljata goQll'JJunicatio"- ~~~u~. R..=gister SBU Fis ~<? tlQld dat~. Register ~ON controls datacomr!J.Y,!1LGatipn.Register PCON controls data rates. Pins RXD and TXD connect to the serial datanetwork. -. ,l . - ... ~ - ~~ -- - ~ --.....~ ~-'

Interrupt Control

Interrupt is a hardware signal activated by an I/O device to alert the CPU. Interrupts may be

generated ~y ~~~~~ oe.eraj!Q.n~Q.rprovid~d by elitern~1 source~.;..The arrival of an Int~rruptRequestcaus s . e PU to suspend the executionof the main program and start the e,xecutlonofthe Interrup.t Service Routine (ISRtpresent in program Q1emoJY.After responding to the interrupt, theCPU-returns back to the mmn program which it was executing before the interrupt occurred. Program

resumption is done with the help of stac~. The PC (prograr:n counter) address is sayg&tQn ~..$tack~fore chanQing it to !h_einterrupt ~ddre~.s in RQM. The PC address wm b.§r~stored from the stack~Lan~1 il1struction is executed ~t the¥D9 of the IS~. Most applications of micr~contro.Uersinvolve real-time interrupts which require quicker respon~e.\\ -, .

Interrupts can be e~le~_or..gisabled unger program control by altering control bits in theinteJIupt enable register (IE). interrupt Briority re.,glster(IP) and timer control register (TCON). Fiveinterrupts are provided in the 8051. The interrupts are of two types: (1) Internal interrupts and(2) External interrupts. ,

~

Internal InterruptsThe followingthree interrupts aregeneratedby internaloperations:

(a) Timerflag 0 (TFO)

(b) Timerflag 1 (TF1)

(c) Serialport interrupt (RI orTI)Whena timer/counteroverflo~s, the correspondingtimerflag,TFOorTFl, is sett01.Theflag is

clearedto 0 wnenTheresu1tinginterrupfgeneratesa progra'm'camofneappropriate timersubroutinein"memory.If a data byte isreceiv-ea, interrupt bit RI is set to 1 i,nthe qCON register.When a dataoyte has been transmitted. interrupt bifTI is set to 1 in SCaN. These are ORed together to providea single interrupt to the process'or:the serial port interrupt. ,..

- -

.--

ii ]


External Interrupts

Thefollowing two interrupts are triggered by external signals:

(a) INTO (Port.pinP3.2)

(b) INT1 (Port pin P3.3)

Reset

Whenevera high level isappJiedtothe RSTpin, the 8051 enters a resetcondition. ~e!.c"an~ec~ns12~~~d_!9 _~e,a ~on:mas!<~b~einterru.pt:. A reset is an ~~sol!:ltEZJ;OJJl.lrt~nq t9jur1]~~99Lamadttress O_OO.Q~~nd commence execuung from there. Program counter (PC) is not stored fo"f laterprogramresumption. -".110 Ports

Portsrepresent physical c5>nnecti?nof CPLl ~t~_ou!sLd~e_wQIlciMicrocontroller u_s~sthem inorder to m_Ql)itor.orcontrol other compon~l'1tsor devices...Physically, port fsa register inside amrer6COiitrolier~igh js~onngcJ.ea by-~iresto the pins of a 'microcon~ue to tu.n'ctionaTity,'somepinshavemultipleroles.Thereare fourllO gort§)(PO"-P3)of 8 lines each. Some of these ports-can ba,configurecr.asirf~ or output. In addition, po1T~ can performcertain specific functions.~_.- ~ .. -- . - -"" -., _. --special circuits like latch, buffer ana driver are Included in these ports.- - -Oscillator and Clock

In order to synchronize all the i~emal operations of the microcontroller, on-chie °scillator isl.\~d.~.Jtrequires an e~ternal crystal for its operation. A quartz crystal is connected for this'purpcfmr-oy using"flie..reraiTnafsXfAl f~md XfAL2. Different versions of 8051 operate oVer frequencies rangingfrom1 MHzto 16MHz. ~ - ,

PIN DIAGRAM OF 8051 WITH FUNCTIONS

A pinout of the 8051 packaged in aJQ:pin DIP is shown in Fig. 2.3 with the full and abbreviatednames q! the signals for each pin. It is important to note that many of the pins are used for more thanone function (thE}alternate functions are shown in parentheses), Not all of the possible 8051 featu resmay be used at the same time. Programming instructions or physical pin connections determine theuse of any multifunction pins. For-example, port 3 bit 0 (abbreviated P3.0) ll1ay be used as a general-purpose I/O pin, or as an input (RXD) to~U~ the serial data receiver register. The system designerdecides which o~these two functions is to be used and designs the hardware and software affectingthat pin accordingly.

Port 1: P 1.0 - P 1.7 (pins 1 - 8)

Port 1 is a bidirectional 1/0 port consisting of 8 lines.'"

Reset: RST (pin 9)

. RSTisana~tivehig~inputusedt~resettlie microcontrollerwhichterminatesallactivities.Port 3: P3.0 - P3.7 (pins 10 -17)

Port 3 is a bidirectional I/O port consisting of 8 lines. In addition, port 3 provides specialfunctions as listed below:

(I

,

'

,

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22 Microcontrollers-and Applicati<:>ns

\J

Vee 40 +5VPort 1 Bit 0 I 1 P1.0

Port 1 Bit 1 I 2 Pl.l (ADO)PO.O 39 I Port0 Bit 0(Address/Data 0)

Port 1Bit 2 I 3 P1.2 (ADl)PO.l 38 IPort0 Bit 1(Address/Data 1)

Port 1 Bit 3 I 4 Pl.3 (AD2)PO.2 37 I Port 0 Bit 2(Address/Data 2)

Port 1 Bit 4 I 5 P1.4 (AD3)PO.3 36 IPort0 Bit3(Address/Data 3)

Port 1 Bit 5 I6 P1.5 (AD4)PO.4 35 I Port 0 Bit 4(Address/Data 4)

Port 1 Bit 6 I 7 P1.6 (AD5)PO.5 34 I Port0 Bit5 .(Address/Data 5)

Port 1 Bit 7 I 8 P1.7 (AD6)PO.633 IPort0 Bit 6(Address/Data 6)

Reset Input I 9 RSTt (AD7)PO.732 I Port0 Bit7(Address/Data 7)

Port 3 Bit 0 10 P3.0{RXD) (Vpp)/EA 31 External Enable(Receive Data) (EPROMProgramming Voltage)

Port 3 Bit 1 11 P3.l(TXD) (PROG)AlE 30 Address latch Enable(XMIT Data) (EPROMProgramPulse)- -Port3 Bit 2 12 P3.20NTO) PSEN 29 ProgramStoreEnable

(Interrupt 0) -Port 3 Bit 3 13 P3.3C1NTl)

(AI5)P2.7 281 Port 2 Bit 7(Interrupt 1) (Address 15)

Port 3 Bit 4 14 P3.4(TO) (A14)P2.6 27 Port 2 Bit 6(Timer 0 Input) (Address 14)

}

Port3 Bit 5 15 P3.5(Tl) (A13)P2.5 26 Port 2 Bit 5(Timer 1 S"put) (Address 13)

Port3 Bit 6 16 P3.6(WR) (A12)P2.4 25 Port2 Bit 4(WriteStrobe) (Address 12)-

Port3 Bit 7 17 P3.7(RO) (A11)P2.3 ,24 Port2 Bit 3(Read Strobe) (Address 11)

Crystal Input 2 18 XTAL2 (A10)P2.2 23 Port2 Bit 2(Address 10)

CrystalInput 1 I 19 XTAL1 (A9)P2.1 22 I Port2Bit 1(Address 9)

IGround I 20 Vss (A1P2.0 21 I Port 2 BitO,<-... (Address 8)

I "I . -

Note: Alternate functions are shown be'low the port name (in parentheses). Pin numbers and pinnames are shown inside the DIP package.

Fig. 2.3: Pin diagram of 8051

.. ~ .. ]


P3.0 (RXD): Serial input port

P3.1 (TXD): Serial output port

P3.2 (INTO )':External interrupt with vector 0003H

P3.3 (INT1 ): External interrupt with vector 0013H

P3.4 (TO):Timer 0 external input

P3.5 (T1): Timer 1 external input

P3.6 (WR): External data memory write strobe

P3.? (RD ): External data memory read strobe

Crystal inputs: XTAL2and XTAL1: (pins 18 -19)

XTAL 1 is the input to the inverting oscillator amplifier and input to the internal clock generatorcircuits. XTAL 1 is the output from the inverting oscillator amplifier.

Ground: VSS (pin 20)

This is a return (Ground) pin for the supply. It is a OV reference.

Port 2/ High order address bus: P 2.0 - P 2.7/ A8 - A15 (pins 21 -28)

Port 2 is a bidirectional I/O port consisting of 8 lines. In addition, port 2 provides high orderaddressbyte (A8 - A15) through which the 8051 can access 64KB of external memory.

Program Store Enable: PSEN (pin 29)

PSEN is an output pin to access the external program memory (ROM). It is connected to 'OE

(Output Enable)' pin of the ROM chip.

Address Latch Enable / Program Pulse: ALE/ PROG(pin 30)

ALE is an output pin used to perform demultiplexing of multiplexed address/data lines (ADO -AD?). It latches the low order address byte (AO - A7). When ALE = 1, the mC sends out address onADO- AD? Later when ALE =0, data is transferred on these lin~s. This pin is also the program pulse

input (PROG ) during EPROM programming.

External Access Enable I EPROM Programming Voltage: EA I VPP (pin 31)

The lowest 4KB of Program Memory can either be in the on-chip ROM or in an external ROM.- -

This selection is made by strapping the EA pin to either VCC or VSS. If the EA pin is strapped toV'cC,the 8051can access4KBof internalROM(OOOOH- OFFFH)and externalROMof 60KB

(1GOGH- FFFFH). If the EA pin is strapped to VSS, then all program fetches are directed to externalROM (OOOOH- FFFFH).This pin also receivesthe 12.75Vprogrammingsupplyvoltage (VPP)duringEPROM programming.

'l1li

r - -


Port 0 I Address Data Bus: P 0.7 - P 0.0 I AD7 - ADO(pins 32 - 39)

Port 0 is a bidirectional I/O port consisting of 8 lines. Port 0' is also the mujtiplexedJow-order-~dress and data bus AD7 - ADO dlJring ~sses.. t9 extemalprogram and data rl}e!!1<?'l"ALE signalIndicates whether address or data is present on these lines. When ALE = 1, address A7 - AO ispresent. Later when ALE =0, data 07 - DO is transferred on these lines.

VCC: Supply voltage (pin 40)

This is a +5V supply voltage pin.

8051MEMORYORGANIZATION

The 8051 requires memory for program and data. ROM is used for program code and RAMis used for data storage. The 8051 can access 64KB each of ROM and RAM. The 8051 has separateaddress spaces for program and data memory. The total address space of 64KBis arranged as twoparts: (1) Internal (on-chip) ROM/RAM and (2) External ROM/RAM.

PROGRAM MEMORY

The Program memory can be up to 64KB long. The lower 4KB can reside on-chip. If the EA pinis strapped to VCC, the 8051 can access 4KB of internal ROM (OOOOH-OFFFH) and external ROM

of 60KB (1GOGH -FFFFH) as shown in Fig. 2.4 (a). If the EA pin is strapped to VSS, then all programfetches are directed to external ROM (OOOOH - FFFFH) as shown in Fig. 2.4 (b). The read strobe to

external ROM, PSEN , is used for all external program fetches. PSEN is not activated for internalprogram fetches.

FFFF FFFF

60KBYTES

EXTERNAL

OR64K

BYTESEXTERNAL

1000AND

FFFF4k BYTESINTERNAL

" 0000 0000(a) (b)

Fig. 2.4: Program Memory

-- -- --

J

'-Architectureof MCS 8051 25

FFFF

64KBYTES

EXTERNAL

AND

0000

Fig. 2.5: Data Memory

DATA MEMORY

The 8051 can address up to~!iELP.!J1atamemQf.Y. The 8051 has J.g? qYJ~s of on-chip RAMplus a number of Special Function Registers (SFRs). The lower 128 bytes of RAM can be accessedeither by direct addressing or by indirect addressing. Fig. 2.5 shows the data memory organization.

INTERNAL RAM AREA

Fig. 2.6 shows the organization of 128 bytes of internal RAM which can be accessed by bothdirect and indirect addressing. It can be divided into the following three segments:

(1) Register Banks 0-3"

(2) BitAddressable Area --;;

(3) ScratchPadArea

Register Banks 0-3

There are four register banks of 8 bytes each, ranging from OOHto 1FH (32 bytes). The devicedefaults to register bank 0 after reset. To use the other register banks1 the user must select them insoftware. Each register b~anKcontarnseight 1-byte7egisters0 through 7. Reset initializes the stackpointer to location 07H and it is incremented once to start fromlocatfon OSH,which is register ROof.- - ----. - ...reg'isterbank1. ...,-. - - - - .-. -' - -Bit Addressable Area

'"'16 bytes have been assigned for this segment, ranging from 20H to ~H. Each one of the 128

bits of this segment can be directly addressed (0 - 7FH). The bits can be referred to in two ways, bothof which are acceptable by most assemblers. One way is to refer to their address (Le., 0 - 7FH). The

other way, is with reference to bytes ,gQHto 2Ft!. Thus, bits OH to 7H can also be referred to as bits20.0 to 20.7, and bits 8H to FH are the same as 21.0 to 21.7, and so on. Each of the 16 bytes in thissegment can also be 'addressed as a byte.

'"

,

INTERNAL

FFISFRs

DIRECTADDRESSINGONLY

I807F

IDIRECT AND INDIRECT

ADDRESSINGI

00

:I-'

26 Microcontrollers and ApplicationsA

RegisterBank

0

I~"""

08070605

0403020100

ByteAddresses

,

7f

302F

20IF

1811

10Of

fntff'nalRAM

Fig. 2.6: Internal RAM Area

7F

00

General.Purpose

Area

BtAddress

A.re

Register<'

Bank3

RegisterBank

2

RegiierBank

1

R7R6

R5

R4R3R2

R)

I RO

.--

InsArchitectureof MCS 8051 27

SCRATCH PAD AREA

30Hthrough 7FH are availableto the use.L.a~..9atC!J18M.However,if the s~ck pointer hasbeeninitializedto this area, enough bytes should be left aside to prevent SP data destruction. - -~ -- - ~~. - c- - - .-~ ..._= ,

REGISTER STRUCTURE OF THE 8051

Reg1sters are used to store opcodes, operands and addresses of memory or I/O devicestemporarily. The register structure of the 8051 can be treated as a coJJectionof 8- and 16-bit registersand 8-bit memory locations. These registers and memory locations can be made to operate usingthe software instructions that are incorporated as part of the design. The registers in the 8051 can.beclassifiedas follows: .' .

(1) Byte addressable registers

(2) Byte and bit addressable registers

(3) General purpose registers

(4) Special function registers

(5) 8-bit registers

(6) 16-bit registers

(7) RAM independent registers

(8) RAM dependent registers (part of RAM)

GENERAL PURPOSE REGISTERS

As discussed earlier, the 8051 has an internal RAM of 128 bytes, out of which 32 bytes are keptaside as general purpose registers (GPRs) ranging from 0 to 1FH (32 bytes). GPRs are organized as

four banks of 8 registers (RO- R7) each. That is, each register bank contains ~ight 1-byte registersROthrough R7. GPRs are addressed as RO.. ..R7 orOOH 1FH.ln order to access them as RO R7,a particular bank should be chosen in software using 04 and 03 bits of Program Status Word (PSW).The device defaults to register bank 0 after reset.

8051 SPECIAL FUNCTION REGISTERS

The 8051 has several special function registers (SFRs) designated as ACC, B, OPTR, PSW, IP,IE, TCON, SCON, PCON, Po' Pl' P2, P3, SBUF etc. These are useful in accessing I/O ports, timers/counters, serial port, power controlling etc. SFRs can only be accessed by direct addressing. Sixteenaddresses in SFR space are both byte- and bit-addressable. The bit-addressable SFRs are thosewhose address ends in OH or 8H. The SFRs can be accessed by their names or by their addressesranging from 80H to FFH. Some of the addresses from 80H to FFH are not defined. Attempting to usesuch addresses may cause unpredictable results. Fig. 2.7 gives a brief look at the special functionregister (SFR) space. Special function registers can be further grouped as follows:

(1) . Math registers (A and B)

(2) Interrupt registers (IP and IE)

(3) Timer/counter registers (TLO, TL1, THO and TH1)

(4) Timer control registers (TMOO and TCON)

(5) Serial data registers (SCON, SBUF and PCON)

(6) Program status word (PSW)

...

I ,.J "'...


(7) Stack pointer (SP)

(8) Program counter (PC)

(9) Data pointer (DPH and DPL)

(10) Ports (PO, P1, P2 and P3)8 BYTES

FF

F7

EFI

E7

OF

07

CF

C7

8F

87

AF

A7

9F

97

8F

87

81T ADDRESSABLE

Fig. 2.7: SFR memory map

Math Registers (A and B)

The accumulator A is used for arithmetic and logical operations. It is used as destination for alladdition and subt(action operations. For logical operations this can be used as a source or destination.

There are some specific operations like clear, complement, rotate and swap for which the operandsmust reside in A register only.

The B register is used for multiplication and division along with the accumulator. It can be usedas a scratch pad where data may be stored.

Interrupt Registers (IP and IE)

Interruptscan be e~ableQor Qisa~d uodJ~!J?r2gr~mcontrolby a~ering controlbits in theinterruptenableregist~r\fE) andinterruptpriorityregistet(IP). - --- f

jI

---

........... -

FB

!." FO

E8

EO

08

DO

C8

CO

88

80

AS

AD

98

90

88

80

.8

A

A

PSI/V

IP

P3 .IE

P2

SCaN SBUF

P1

TCON TMOD TLO TU THO TH1

PO SP DPL OPH PCON'"

,.....-

s Architecture of MCS 8051 29

Timer/Counter Registers (TLO, TL1, THO and TH1)

The8051hastwo 16-bit upcounters, namedTOandT1.The countersaredivided intotwo8-bitregisterscalledthe timer low (TLO,TL1)and high (THO,TH1) bytes.

Timer Control Registers (TMOD and TCON)

All counter pction is controJJ.~dby bit states in TMOD (timer mode control register), TCON(timer/countercontrol register) and certainprogrammslructR5ns.... - ~

'1 .Serial Data Registers (SCON, SBUF and PCON) ,

The 8051 communicates with other devices by sending and receiving data bits serially using a~~!ia' data communication circuit. Register SBUF (sefia:raata b,uffer}'is ~~ed fo~h<?ldd~ta.,~l)F is ..

Ehy-sicPll¥-1WQJ~gJsters.On!.is ~rife only~and is ~~~d _tohold data to_Detransmitted out of the 8051.viaTXD(transmitdata).The.2!her1§~..pdonlyand bo.ldsreceiveddat'!from external source~'yJ.9RXD,{receive data). B°.th rT1lJtuallyexclusive regtster,s use addresS99F-J.Regi~r.§qON (serial control)controls data communication. Register PCON (power control) controls data ~at~. .J

" -0, -,-- - - "Program Status Word (PSW)

~ITagi§3~which indicates some condition produced by the execution of an instructionor controls,certain operations of the 8051: Certain 8051 instructions cheCKthese flags to determinewhich of twQ.?ilternative actions should be done in ex_ecutingthe instrLJction~. Fig. 2.8 shows an 8-bitflag register know'h as PSW (prograrl] status word) in the 8051 . PSW is a bit addressable regISter. Abriefexplanationof PSW is as follows: '

PF (Parity FlagJPF is set to 1 if the accumulator contains an odd number of 1s. Otherwise it is cleared.

CY (Carry Flag)

An additioncauses.CYflag to'be set if there is a carry out of the !X1$1?and a subtractioncausesitto beset if a borrow is needed. Other instructionsalso affect this flag. - ~-

~ "_.,' .-

AC(AuxiliaryCarryFlag) .

AF is WJ1.1b.~ a carry 9ut of bi.L3during_an addition or ~ borrow bi.bit 3 du~~ s~btraction.1his flag is used exclusively for BCD arithmetic.- - -- M_'-M---...--OV (Overflow Flag)

OF is set if an ov.2!1lpY'lQga!ts, i.e., a resu.l! i~ 91}t 01r:ange. Mor_especifically, for additiQn this. flag is set when there is a c~lry.l!1!~ the~nd ~o carry out of the MSB or_viceversa. ForsiThfraction, it is set when the MSB needs a bo!!QY'I.and t~ere is no borrow-1rom the MSB, or ~igeversa. The overflow flag will be set if signe-d arithmetic is too large to fit in the destination register oramemorylocatIOn.- -- - - - "- - M- - '~

\

'.

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I Cy I AC I Fa I RSj I RSa I Ov I I p I

PSW.7 ~ t t t t t t lCarry flag receives carry outfrom bit 7 of .A.LUoperands

PSvv.6

Aux:ilr.af)'carry flag receivescarr! out from bit 3of additionoperands.

PSVV.5

General purpose status flag

PSVV.4

Registerbankselectf)it 1

Fig. 2.8: 8051 program status word

PS'WO

Parity of accumi.llator setby hardw'are to 1 if It cootainsan odd number of 1s; other.viseit is reset m O.

PSW.1

User-definal~eflag

PS'W.2

Ovemowflagset byarithmeiicoperations

PSW~

Registerbankselect bit 0

L .. .""rco' , ," , """-',,,.. -.-I ,.. .. -

U)0

~n'"'"0(')0,.:J-+-"'"0

(!)"'"(IIQ:J0...»

-0-0(')Q~0:JV>


BankSelection

Twobits RS1 and RSOof PSW are used for RAM bankselection as shown in Table.2.1.

Table. 2.1: RAM bank selection.Stack Pointer (SP)

A stack is a section of memory arranged in last-in-first-out (LIFO) manner. It~~et as..ideto. storead and data while a sub ro J.§!!Jj$e~tin9: The mem-9IY~ b'(tew~~

mostrecentl store IScalle stack.,Tile stack pointer (SP)~an8-bt re9iste~ that points.- /To the top of stacR. Reset initializes the stack pointer to location 07H. Itis incremented once to start-from location 08~{ which is register ROQ!..r~mistE2~p~r}k1. =f - r . - ~--- r-~

When data is stored on !be staQk the SP vallJe is iocremented by one. When data is retrieve!Lo v' .n.te.~tb'y..Q!I§.In orderto save and retrJ.ID!edata PUSH/CALLandPOP/REi"instructions are used respectively. -

Data Pointer (DPTR -DPH and DPL)

Data pointer is a 16-bit register. It is op"er -bit re ist~ namely £reJ-l ;:)ng DPL. of

QPTRis used for addressing tb.eoff-chip ROtv!~"'iJth MOVC and MOVX instructionsr~. SinceDPTRis a 16-b!!..r~_g~W",64KBof '3°M/f3L\M~ ~ addre~<!i°QQ°.tt- t5>FFFFH). " . ~ ~ . .

Program Counter (PC)

The program counter (PC) ~ps track of the e<sec~tionof ~. It is a 16-blt registe~ th.?.tcontainsJhememory(ROM)addressofthe instructioncurrentlybeing~xecut~. Duril1gthe execu1io[1-- ~. . ~ _. -, '- - re' .~ ~ r . . ,-

9fthecurrent:ipstructlonlthecontentsof. e add~essa! ~g.areUQd~~ to c~porJ.D ~tothe.addressof the next instruction to be.executed. It is customary to say that the PC points to'the.--: -- ,..-' /instructionthat is to be f~ch~d from the memq!)'.When 8051 js powered up, the Pc. is loadedwithOOOOH.Therefore the first instruction byteof a program must reside in ROM location OOOOH., . ~ -

Ports (PO, P1, P2 and P3)

Ports PO...P1, P2 and P3 are 8-bit registers. These are byte addressable as well as bitaddressable.

~

RS1 (PSW.4) RSO lPSW.3) Bank0 0 00 1 11 0 21 1 3

,&..

~ -I..

,., "


SUMMARY

Table~2.2 gives the summary of special function registers.

Note: * = byte addressable as well as bit addressable

Table.2.2: Summaryof special functionregisters

-.:. - . -... --=-~

Special Register name Address Purposefunction

*A EOH The accumulator A is used for arithmetic and logicalMath (Accumulator) - operations. It holds operands in specific operations like clear,

complement, rotate and swap.*B FOH The B register is used for multiplication and division along with

the accumulator. It can be used as a scratch pad where datamay be stored.

*IP B8H Interrupts can be enabled or disabled under program conJrolbyInterrupt (Interrupt priority) l!I!§fing ce interrupti enable register (IE) and

*IE A8H interrupt priorityregister (IP).(Interrupt enable)

TLO 8AH The 8051 has two 16bit up counters, named TO and T1. The(Timer/Counter 0 counters are divided into two 8-bit registers called the timer low

lowbyte) (TLO,TL1) and high (THO,TH1) bytes.Timer/ TL1 8BH

Counter (Timer/Counter 1lowbyte)

THO 8CH(Timer/Counter 0

high byte)TH1 8DH

(Timer/Counter 1high byte)

TMOD 89H All counter action is controlled by bit states in TMOD (timerTimer (Timer mode) mode control register), TCON (timer/counter control register)control *TCON 88H and certain program instructions.

(Timer control)*SCON 98H Register SCON controls data communication.

(Serial control) --

Serial SBUF 99H Register SBUF is used to hold data.data (Serial data

buffer)PCON 87H Register PCON controls data rates.

(Power control)Flags *PSW DOH PSW consists of PF, CY, AC and OV flags.

(Program status Two bits RS1 and RSO of PSW are used for RAM bankword) selection

Stack SP 81H The stack pointer register points to the top of stack.(Stack pointer)

DPL 82H Data pointer is a 16-bit register. It is operated as two 8-bitData (Data pointer low registers, namely DPH and DPL. DPTR is used for addressing

pointer byte) the off-chip ROM and RAMwith MOVC and MOVXinstructions -

DPH 83H respectively. Since DPTR is a 16-bit register, 64KB of(Data pointer ROM/RAMcan be addressed (OOOOHto FFFFH).

high byte)*PO 80H Ports PO, P1, P2 and P3 are 8-bit registers. These are byte

Port *P1 90H addressable as wellas bit addressable.*P2 AOH*P3 BOH

:II


IMPORTANTPOINTS

.. Important features of 8051 microcontroller

(1) 8-bit CPU

(2) 8-bit registers: A, B, RO- R7

(3) 16-bit program counter (PC) and data pointer (OPTR)

(4) 8-bit program status word (PSW), stack pointer (SP)

(5) Internal ROM of 4KB

(6) Internal RAM of 128 bytes

(7) Four flags: PF, CY, AC and OV

(8) 32 I/O pins arranged as four 8-bit ports: PO- P3

(9) Two 16-bit timer/counters: TOand T1

(10) Two external and three internal interrupt sources and reset (6 interrupts)

(11) 1 serial port

The flag register in the 8051 is called Program Status Word (PSW). The size of the flag registerin the 8051 is 8 bits. 01 (PSW.1) and 05 (PSW.5) are user-definable. RAM bank selection is done asfollows: .

I'- RAM address space

I'- A stack is a section of memory arranged in last-in-first-out (LIFO) manner. Reset initializes thestack pointer to location 07H.

I'- The program counter (PC) keeps track of the execution of a program. When 8051 is poweredup, the PC is loaded with OODOH.

REVIEW QUESTIONS

Objective Type

1. The 8051 is a(n) -bit microcontroller.2. The 8051 has on-chiptimer(s).

3. The 8051 family has pins for I/O.

4. The flag register in the 8051 is called -5. The size of the flag register in the 8051 is

6. On power-up, the 8051 uses RAMlocation7. On power-up, the 8051 uses bank. .8. On power-up, the 8051 uses RAM locations

bits.

- as the first location of the stack.

for registers RO- R7.

for registers RO - R7.

.. .J

RAM Address Description00 - 1FH Reqister Banks 0-320 - 2FH Bit addressable RAM30 -7FH Scratch Pad RAM

l

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1(.I .,

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34

Answers

1. 8

4. PSW

7. 0

2.2

5.8

8. 0 to 7

I

Microcontrollers and Applications I

3. 326. 08

Descriptive Type

1. Listthe features of 8051 microcontroller. (5)

2. Write a brief note on 8051 memoryorganization. (5)

3. Explainthe registerstructureofthe8051 i (5)4. Explain the program status word (PSW) of the 8051 (5)5. Explainthe role of program counter (PC), stackpointer (SP)and data pointer (DPTR) in 8051.

(6)

(9)6. Draw the block diagram of 8051 microcontroller and explain.

-

IS

INTRODUCTION TO ADVANCEDMICROCONTROLLERS

OVERVIEWOF MCS 96 MICROCONTROLLERFAMILY

Intel MCS 96 microcontroller family of products is popular for 16-bit e edded microcontrollers.They are found in a variety of embedded applications. The MCS 96 family shares a common corearchitecture which is register base? The register architecture eliminat~s the aCGumulatpr bottleneckand enables fast context switching. All devices have bit, byte, word 'and 32-bit operations. The high-performance regist~r to register architecture is well suited for complex real-time control applicationssuchas hard disk drives, modems, printers, pattern recognition and motor control. --

FEATU R ES

.:. On-chip memory

.:. Register-to-regis~er arGhitecture ,..-

.:. Threeoperandinstructions.-

.:. Buscontrollerfeatures,programmablewait-stategenerationand8- or 16-bitbuswidths, ,. ,

.:. Flat addressability of large register files f- -. .

.:. Three distinct product lines:. Event Processor Array..--

. HighSpeedInput/Output~

. Motor Control ~

BEN E FITS

.:. Lowcost

.:. More compact code than accumulator-based architecture

.:. Minimum of 232 registers can be directly addressed at any time

.:. Efficientusage of wide variety of memoryand peripheral devices

MCS96 MICROCONTROLLERFAMILYPRODUCT LINES

The MCS 96 microcontroller product family has the following three distinct product lines:

(1) High Speed Input/Output (HSIO) Family

(2) Event Processor Array (EPA) Family

(3) MotorControl Family

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36 Microcontrollers and Applicatiom

HIGH SPEED INPUT/OUTPUT (HSIO) FAMILY

The HSIO Family consists of devices that have the High Speed Input/Output sub-system.

Key Features

.:. Up to 20 MHz operation .:. Fast register to register architecture

.:. Up to 1000 bytes register RAM .:. Upto 32K internalOTPROM

.:. Dynamicallyconfigurable8-or 16-bitbuswidth .:. HOLD/HLDA bus protocol

.:. 8-Channel high speed I/O (HSIO) subsystem .:. 16-bit timer'

.:. 16-bit counter .:. Up to 3 dedicated PWM generators

.:. Full duplex serial port .:. 16-Bit watchdog timer

.:. Eightchannel 8- or 1a-bitAID converter .:. Five8-bit I/O ports

.:. IDLEand POWERDOWN modes

.:. Peripheraltransaction server (PTS)on KCand KD

8XC196KB

The 8xC196KB is the first memberof the CHMOSMCS96 controllerfamily. It is available in8Kbyte ROM and 8K byte OTPROM versions. All versions feature'232 bytes of register RAM. The8xC196KB uses the High-Speed Input/Output (HSIO) structurefor event control. The HSIO has upto 4 input and 6 output,lines and uses either of two 16-bit timer/counters as a time base. Additionalfeatures include a hardware-generated pulsewidth modulator (PWM),a full-duplex serial I/O (SIO)port, a watchdog timer and an 8-channel 10-bit resolution analog to digital (AID) converter. The8xC196KB has 48 input/output (I/O) lines which are shared with the peripherals.

8XC196KC

The 8xC196KC is the next step up in the CHMOS 196family. It is available in 16K byte ROMand 16K byte OTPROM versions. All versions feature 488 bytes of register RAM. The 8xC196KCis offered in a 20 MHz version, allowing 25% increase in performance. The 8xC196KC has all theperipherals as the 8xC196KB with the following enhancements:(1) Three hardware PWM generators

(2) AID converter has both 8- and 10-bit conversion modes with programmable sample andconversion times.

(3) Peripheral transaction server (PTS) acts as a microcoded interrupt handler which greatlyreducesCPU overhead during interrupt servicing.

8xC196KD

,

The 8xC196KD has all the features of the 8xC196KC, but has extended the on chip memory.The 8xC196KD is available in 32K byte ROM and 32K byte OTPROM versions. Both versions feature1000 bytes of Register RAM. With the availability of 32K of memory, program development in highlevel languages becomes much more practical. The 8xC196KD is also offered in a 20 MHz version.

EVENT PROCESSOR ARRAY (EPA)FAMILY

\The most recent products form the EPA Family.This family of devices has the advanced

peripheralswhich include a flexible input/outputsystemand EPA(event processor array).

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15 Introduction to Advanced Microcontrollers 37

Key Features

.:. Up to 50 MHz operation

.:. Fast register to register architecture

.:. Upto 512 bytes of internal RAM

.:. Up to 1M byte of external addressing

.:. Enhancedbus controllerNU)

.:. Chipselect unit (NP,NU)

.:. Up to 10 channel event processor array

.:. Two16-bittimer/counterswith prescalarandquadraturecounting mode

.:. Fullduplexserial port with independentbaudrate generat~r

.:. Fullduplex synchronousserial port

.:. Slave port for direct interprocessor communication

.:. 16-bitwatchdogtimer. . .:. Upto 8 channel 8- or 1O-bitAID converter

.:. IDLEand POWERDOWNmodes .:. PeripheralTransactionServer

.:. 3 PWMoutputs (NP,NU)

.:. 3.3 volt operation (NP only)

.:. Up to 1000 bytes of register RAM

.:. Up to 32K of internal OTPROM

.:. Dynamicallyconfigurable 8- or 16-bitbus width

.:. Dynamicallymultiplexed/demultiplexedbus(NP,

.:. HOlD/HlDA bus protocol

8XC196NT

The 8xC196NT has 1M byte external addressability. Four of the AID inputs are replaced withthe extended address port (EPORT). The four EPORT pins can be used as additional addresslines (A16 - A19) or standard low speed lIas or.a combination of both. The 8xC196NT has 20 MHzoperation.

8XC196NP

The 8xC196NP offers a dynamically selectable multiplexed/demultiplexed bus. Other keyfeaturesof the 8xC196NPare the chip select unit, 1M byteaddressing,3 PWM outputs and25 MHzoperationat5 volts.

8XL196NP

The 8xCl 196NP is functionally identical with the 8xC196NP, but offers low power operation (3volts at 1"3MHz).

80C196NU

The 80C196NU doubles the performance of the 8xC196NP,operating at 50 MHz (5V). The80C196NUalsofeaturesa 32-bit accumulatorimplantedin hardwareto increasethe performanceofmultiply/accumulateinstructions.The 80C196NUis pin compatiblewith the 8xC196NP.This feature,alongwith its clock doubling circuitry, enables the 80C196NU to provide a high performance in-socketupgrade to 8xC196NP designs. Other key features include 1M byte addressing, 3 PWMoutputs,chip select unit and both 40 and 50 MHz (5V)versions.

...

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38 Microcontrollers and ApplicationsI

MOTORCONTROLFAMILY

The motor control family is c.omprisedof devicesthat support motor control applications.Thisfamily also uses the EPAsystem for I/O control. .

Key Features

.:. Register RAM file .:. High performance CPU

.:. On-chip ROM/OTPROM .:. Sophisticated three-phase PWM waveform generator

.:. Fast, flexible interrupts .:. Peripheral transaction server (PTS)

.:. Event processor array (EPA) .:. Two 16-bit timer/counter

.:. 16-bitwatchdogtimer .:. AID converter

.:. Frequency generator module (MD only) .:. Serial I/O (MH only)

8XC196MCIMH '-

The 8xC196MC/MH are members of the MCS 96 motor control family. This device has a peripheralset which is optimized for 3-phase AC induction and DC brushless motor control as well as powerII

inverterapplications. Some of the specific features are listed below:

(1) Waveform generator (WFG): WFG is used to generate 3-phase PWM. The WFG generatesthree complementary non-overlapping PWM pulses. The WFG features programmablefrequency,duty cycle and dead times.

(2) PWM generators: There are two PWM generators. These have a common programmablefrequency and separately programmable duty cycles and 8-bit resolution.

(3) Advanced event processor array (EPA) structure: Advanced EPA structure is used for eventmonitoring and control.

(4) PeripheralTransactionServer (PTS):PTSsupports microcodedinterruptprocessing requiringless CPU intervention.

I-~""

(5) Register RAM

(6) Factory programmed ROM

(7) ROM(8) OTPROM

(9) AID converter(10) I/O lines

(11) Inputonly lines

(12) Capture/comparemodules(13) Compareonly modules

(14) TwochannelUART

8xC196MC

488 bytes

16K bytes16K bytes

16K bytes13channels

4013

44

Notavailable

8xC196MH

744 bytes

32K bytes

32K bytes32K bytes8 channels

44

82

4

Available

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"'.,., ~ ,~ -~ :::~ _1

Ins

Introduction to Advanced Microcontrollers 39

8XC196MDis

)r

The 8xC196MD has all of the 8xC196MC features with the following enhancements:

.:. A frequency generator allows generating a programmable frequency square wave, which findsuse in infrared remote control communications.

.:. Twoadditional capture I compare and two compare only modules are added to the event processorarray, giving additional event capture and generation capabilities.

.:. Eightadditionailia pins, two input only and one analog/digital input pin are added. The 8xC196MDmaintains pin-for-pin compatibility with the 8xC196MC device, allowing easy upgrades of existingdesigns. \

MCS-251MICROCONTROLLERFAMILY

OVERVIEW

MCS 251 architecture is the next generation of Intel MCS 51 architecture. It increases systemperformance by a factor of five using existing MCS 51 microcontroller code. By rewriting codeusing the MCS 251 architecture instructions, designers can increase performance up to 15 times.The following list gives an overview of MCS-251 microcontroller family:

.:. Binarycode compatible with MCS 51 architecture

.:. 5 to 15 times increase in performance compared to MCS 51 microcontroller at the same clockspeed

.:. 3-stage pipeline CPU architecture

.:. 2 clocks(1 state)~perinstruction

.:. 16-bit internal code bus

. 2 byteslstate code fetch.:. 8-BitALU

. High speed a-bit source and 16-bit destination bus

. 40 bytes general purpose register file Accessible as sixteen a-bit, sixteen 16-bit or ten 32-bitregisters

. Accumulator functionality and data indexing capability

.:. 24-bitlinearcodeand data addressing

.:. 64KB stack space

.:. New instructions and addressing modes

. 8, 16 and 32-bit data transfer, arithmetic and logical instructions

. Supports register, immediate, direct, indirect, displacement, relative and bit addressing

.:. Supports64 interruptsources

. 1TRAP instru~tioninterrupt (highest priority)

. 1 non-maskableinterrupt (2ndhighestpriority)

. 62 maskable interruptsources

. 4 Interruptprioritylevels

Micro Controller

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