MICAS Department of Electrical Engineering (ESAT) Logic style 1. Standard CMOS logic 2. Pseudo NMOS...
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MICAS Department of Electrical Engineering (ESAT) Logic style 1. Standard CMOS logic 2. Pseudo NMOS logic 3. MCML (MOS Current Mode Logic--differential version of CSL) 4. CSL (CMOS Current Steering Logic) AID–EMC: Low emission Digital Circuit Design
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MICAS Department of Electrical Engineering (ESAT) CSL – Static Characteristic Design Parameter: R= Vdd=2.5v I=20uA
Transcript of MICAS Department of Electrical Engineering (ESAT) Logic style 1. Standard CMOS logic 2. Pseudo NMOS...
MICASDepartment of Electrical Engineering (ESAT)
Logic style
1. Standard CMOS logic2. Pseudo NMOS logic3. MCML (MOS Current Mode Logic--differential version of CSL)
4. CSL (CMOS Current Steering Logic)
AID–EMC: Low emission Digital Circuit Design
MICASDepartment of Electrical Engineering (ESAT)
Comparison---Maximum di/dt of an Inverter
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1 2 3 4logic style
di/d
t(am
p/s)
Standard CMOSPseudo NMOSCSLMCML
Why CSL ?
Target : Mixed-Mode Automotive Electronics Design
Key aspect : di/dt + Power + Area + Speed
Current Steering Logic
MICASDepartment of Electrical Engineering (ESAT)
CSL – Static CharacteristicStatic Characteristic
0
0.5
1
1.5
2
2.5
0 5 10 15 20 25
R
Vol
tage
(v)
VOH VOL VIL VIH
Design Parameter:
R=
Vdd=2.5vI=20uA
MICASDepartment of Electrical Engineering (ESAT)
CSL – Noise Margin
Noise Margin vs. R
0
0.2
0.4
0.6
0.8
1
1.2
0 5 10 15 20 25
R
Noi
se M
argi
n(v)
NMHNML
Vdd=2.5vI=20uA
MICASDepartment of Electrical Engineering (ESAT)
CSL – Dynamic Characteristic
Propagation delay vs. R
0
1E-10
2E-10
3E-10
4E-10
5E-10
6E-10
0 5 10 15 20
R
tp(s
)tp
Vdd=2.5vI=20uA
MICASDepartment of Electrical Engineering (ESAT)
Vdd=3.3vI=10uAR=6
Cd
The Effect of Decoupling Capacitance
1p
10p,100p,1n,10n
There is a Trade off !
MICASDepartment of Electrical Engineering (ESAT)
Comparison of 16-bit RCA
Note: Vdd=1.5v The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I.
Solution:
power consumption management
• power down strategies, • sleeping transistors,• …
Power vs. Frequency (16-bit RCA)
0.00E+00
1.00E-04
2.00E-04
3.00E-04
4.00E-04
5.00E-04
6.00E-04
7.00E-04
8.00E-04
9.00E-04
0 50 100 150 200 250 300
Frequency(Mhz)
Pow
er(W
att)
CMOS
CSL
MICASDepartment of Electrical Engineering (ESAT)
Spectrum Analysis of di/dt
105
106
107
108
109
1010
70
80
90
100
110
120
130
140
150Power Spectral Analysis of the CMOS 16-bit RCA
Frequency (Hz)
Pow
er
105
106
107
108
109
1010
40
50
60
70
80
90
100
110
120Power Spectral Analysis of The Current Steering 16-bit RCA
Frequency (Hz)
Pow
er
GABARIT ?
30db decrease
