Annual report 2017MICAS - Electrical EngineeringKU Leuven

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Cover: the variety of MICAS: 1 A 120GHz in-band full-duplex PMF transceiver with tunable electrical-balance duplexer 2 A 40nm CMOS near-threshold processor with in-situ timing error detection and correction 3 MEMS technology for a fully flexible and stretchable silicon substrate for silicon implants

v.u. : Wim Dehaene, Kasteelpark Arenberg 10, 3001 Leuven, Belgium

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Annual report 2017MICAS - Electrical EngineeringKU Leuven

Dept. Electrical Engineering - MICAS Kasteelpark Arenberg 10 - box 2443

3001 Leuven, Belgium tel +32 16 321077

www.esat.kuleuven.be/micas

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Table of contents

MICAS : MICroelectronics And Sensors Annual Report 2017

1. Analog circuits & power management 12

1.1 Design of Soft-Charging fully integrated capacitive converters 1.2 Mains facing AC/DC power conversion with efficient standby mode1.3 Load Stacking with Dynamic Voltage Scaling towards highly efficient energy

storage1.4 Wideband CMOS line driver for high-speed communication1.5 Optical receivers in nanoscale CMOS with Schottky diodes1.6 Very high resolution front-ends for HEP experiments1.7 Automatic test generation for analog/mixed-signal integrated circuits1.8 Efficient methods for testing of analog and mixed-signal ICs1.9 Sub-ppm design for testability for analog and mixed-signal ICs1.10 Wavelength-locked ring-based CMOS-SiPh optical transmitters1.11 Transient EMI immunity of Integrated Circuits

2. RF, mm-wave & THz circuit 26

2.1 A low-noise variable-gain amplifier and a wideband high-IF receiver for cognitive radio

2.2 Active phased array for 5G mobile communication2.3 A wideband class-AB power amplifier with 29 to 57GHz AM-PM compensation

in 0.9V 28nm CMOS2.4 Broadband power amplifier design for 5G nanocells2.5 Power detector for PAs operating at mm-wave frequencies2.6 A 28nm coupled-RTWO-based subharmonic receiver for 5G E-band backhaul links2.7 An F-band phase shifter for automatic tuning in an FSK receiver2.8 A 120GHz in-band full-duplex PMF transceiver with tunable electricalbalance duplexer2.9 A low-latency 120 GHz galvanically isolated link operating from -40 to +200C2.10 A 140GHz DWG communication link with automatic tuning2.11 Data communication through THz ribbon waveguides2.12 A 0.53 THz steerable phased-array in 40 nm CMOS technology2.13 Terahertz CMOS receivers

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3. Mixed-signal design & data converters 42

3.1 High-speed high-resolution hybrid CMOS ADCs for wireline/wireless communication systems3.2 Power-efficient Delta-Sigma modulators with high bandwidth3.3 Design of low-power high-speed hybrid ADCs3.4 Design of wide-band DACs for 5G applications3.5 Advanced architectures for time-based analog-to-digital converters3.6 Impact of electrical and optical 3D integration technologies on high bandwidth systems3.7 High speed clock and data recovery in standard CMOS3.8 High-performance analog-to-digital converters for 3D-stacked CMOS image

sensors3.9 Drift-resilient BBPLL-based sensor interfaces3.10 Design of digital-based high-performance sensor interfaces3.11 Configurable non-linear mixed signal interface for resource efficient sensory analytics3.12 Real-time on-chip RTN parameter extraction3.13 Advanced mixed mode design in thin-film technologies

4. Digital circuits & machine learning 58

4.1 Always-on embedded deep learning4.2 Extraction an processing of 360° depth images for increased awareness on drones4.3 Machine intelligent computing with non-volatile memory4.4 In memory computing with SRAM 4.5 Hardware acceleration of deep learning algorithms for keyword spotting4.6 Ultra-low power keyword and speaker identification through hierarchical machine learning4.7 Streaming processing for energy-efficient dense optical flow4.8 Voltage domain stacked SRAM in 22nm FDSOI4.9 Margin elimination through timing error detection in near-threshold digital processors4.10 Energy efficient digital circuits through sub-threshold operation4.11 Hardware-aware machine learning4.12 Hardware aware probabilistic models for resource efficient embedded classification4.13 Ultra-low power self-adaptive sense-and-compress through embedded instincts4.14 Resource-efficient circuit adaptation through machine-learning based “instincts”

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5. Biomedical systems 74

5.1 Ultrasound waves based body area networks5.2 Implantable sensor network for monitoring the bladder wall5.3 Highly compliant and stretchable interconnects for medical implants5.4 A foldable electrode array for 3D recording and stimulation of subcortical brain cavities5.5 Electronic design for high bandwidth neural interfacing5.6 Multimodal integration of EEG and fNIRS 5.7 C.O.T.S. based bionic eye lens glasses and I3T50 digital eye lens controller5.8 Micro-electronics for micro-organisms 5.9 An 8x8 integrated potentiostat array for bio-electrochemical system5.10 Time-based biomedical sensor readout for low-voltage supply and small-

scale CMOS technology5.11 Bio-optoelectronics for Optogenetics 5.12 Lippmann-based optical spectrometer

6. MEMS, sensors & nanotechnology 88

6.1 Nonlinearity and drift in MEMS pressure sensors6.2 Piezoelectric materials and piezoelectric ultrasound transducers6.3 MEMS technology for flexible and stretchable silicon implants6.4 Active matrix driving for LED walls6.5 Micromachined horn antennas and lenses for high gain Thz tranceivers6.6 CMOS circuits for dielectric fiber sensors

7. Educational reseach & projects 96

7.1 Developing STEM-integrating learning materials7.2 Process evaluation in integrated STEM7.3 Transfer of concepts in secondary education7.4 The role of teachers in the implementation of integrated STEM education7.5 Learning of physics and mathematics concepts in an integrated STEM

curriculum

8. Awards and prizes in 2017 104

9. Infrastructure 110

9.1 Computer and software infrastructure9.2 IC-Lab HF: broadband, optical, mm-wave and THz measurement lab9.3 IC-Lab LF: the Low Frequency measurement lab9.4 MICAS in the Leuven Nanocenter (LeNa)9.5 Lithography and MEMS fabrication9.6 Technology Lab: Chip Bonding Facilities9.7 Technology Lab: Dicing and Grinding Facilities9.8 Technology Lab: Chip Repair Facilities9.9 Valorization management9.10 Administrative staff ESAT-MICAS

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10. Doctoral theses in 2017 122

11. Spin-offs 126

11.1 Ansem11.2 ICsense11.3 Zenso11.4 MinDCet11.5 MAGICS Instruments11.6 HAMMER-IMS11.7 Tusk IC

12. Emeriti 132

Willy Sansen

13. Bibliography 136

13.1 Articles in internationally reviewed scientific journals13.2 Books, internationally recognised scientific publisher; as editor13.3 Book chapters, internationally recognised scientific publisher13.4 Papers at international conferences and symposia, published in full in

proceedings13.5 IC-p (Papers at international professionally oriented conferences and

symposia, published in full in proceedings)13.6 Meeting abstracts, presented at international conferences and symposia,

published or not published in proceedings or journals13.7 IMa-p (Meeting abstracts, presented at international professionally oriented

conferences and symposia, published or not published in proceedings or journals)

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PrefaceYour favorite yearbook landed on your desk again: the report presenting last year’s research of the MICAS team of KU Leuven. The presented projects cover the whole spectrum from ‘potentially great ideas, but still a long way to go’ all the way to ‘next time you blink your eyes, you’ll almost find me in a product’ and everything in between. The MICAS research pipeline contains a nice mix of research at all levels of technology readiness.

In this report, you will find numerous pictures of designed and fabricated chips. We are strong believers of hardware validation. MICAS is all about chips! Validation of ideas in silicon or other technologies is one of the cornerstones of our research. Another cornerstone is the partners we interact with. We are funded by local, national and European funding organizations like VLAIO, FWO and the European Commission. Also our industrial cooperation was again very intensive in 2017. It is impossible to sum up all the partners that supported us. We would like to take this opportunity to thank you all for the cooperation. Funding is of course essential, but external collaborations above all ensure that we address relevant topics and aim to solve the micro- and nanoelectronic problems of tomorrow. Without your support there would not be much to talk about in this report.

2017 has brought several highlights to MICAS. In 2017 our extensive equipment collection was expanded with a chip-repair FIB and a chip grinder. This allows FIB operations from the back of the chips, especially useful for flipped chips. This equipment is operational by now and proves to be very useful in a variety of projects. When it comes to human resources, we

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now have a full-time valorization manager on board: David Maes. It is his task to streamline industrial valorization of the MICAS research results. Moreover, MICAS is proud to launch its 9th spin-off company: Tusk IC. You can read more about this emerging mmWave design house further in the booklet.

Also in 2017, MICAS co-organized ESSCIRC/ESSDERC in Leuven. The feedback from the attendants was extremely positive. There were many interesting papers and keynotes, discussions and the gala dinner at Autoworld in Brussels was definitely memorable. We also enjoyed the evening open-door event we had at the MICAS IC measurement lab. It was nice to show to all of you the grounds on which we operate daily, the trenches from which we conduct our research.

Looking forward to 2018, it will be the year in which Bob Puers will retire after a well filled and successful career. No worries, we already have brought his successor on board: Michael Kraft. Prof. Kraft will work in the field of micro- & nanosystems, microsensors and bioMEMS. Stay tuned for next year’s yearbook to see his projects emerge.

We hope that you enjoy the MICAS yearbook, edition 2017, and stay with us for 2018!

Wim DehaeneOn behalf of the entire MICAS staffFebruary 2018

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MicasTeam

Prof. W. Dehaene Low-power digital, time-based processing

Prof. M. KraftMicro- & nanosystems, microsensors, BioMEMS

Prof. G. GielenCAD, analog, mixed-signal

Prof. B. PuersMEMS, packaging, biomedical

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11Prof. P. ReynaertRF, mm-wave, THz

Prof. F. Tavernier Optical, high-speed, power management

Prof. M. SteyaertRF, power management, analog, mixed-signal

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6 Prof. M. VerhelstProcessors, sensor fusion, machine learning

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1. Analog circuits &power management

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Analog is the bread and butter of the MICAS research group with more than 4 decades of outstanding research in this domain, often boldly pursuing unconvential paths.

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Over the past decade, powering integrated circuits has become increasingly difficult: With load currents ever increasing, resistive IR losses and di/dt-induced voltage margins of the power delivery network (PDN) have increased as well. As a solution, many have proposed moving part of the DC-DC conversion on-chip. Doing so reduces the intake current by the on-chip conversion ratio and thus also significantly reduces PDN losses. However, such converters achieve limited output power due to the limited on-chip capacitance density, making their use infeasible for many applications.

In this work, Stage Outphasing and Multiphase Soft-Charging are proposed. Here, the charge transfers between flying capacitors are split into multiple efficient transfers, thereby increasing the effective capacitance density . Thanks to these techniques, a 3:1 Dickson converter, realized in a 28nm CMOS process, has 30x higher power density at similar efficiencies compared to the state-of-the-art of bulk CMOS.

Nicolas Butzen• Promotor Prof. M. Steyaert michiel.steyaert@kuleuven.be• Research topics Monolithic power management,

switched-capacitor circuits, DC-DC conversion

1.1 Design of Soft-Charging fully integrated capacitive converters

Related publication: N. Butzen and M. Steyaert, “Design of Soft-Charging Switched-Capacitor DC-DC Converters using Stage Outphasing and Multiphase Soft-Charging,” IEEE Journal of Solid-State Circuits, vol. 52(12), pp. 3132-3141, 2017.

Fully Integrated DC-DC Converter in 28nm CMOS using soft-charging.

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Electronic devices spend most of their lifetime doing nothing, in the so-called standby mode. Summing the consumed power of devices in standby during their entire live, gives a total amount of standby energy that is much larger than the energy consumed during activity. All these electronic devices are powered by the mains through a power management circuit which is optimized for the active mode, but that is inefficient in standby mode.

The intention of this research is to improve the standby mode by using a two-converter model. One power converter is used to deliver the high power during activity and the other will be optimized for the standby mode. The main focus of this work is towards a fully integrated standby converter that faces the high AC-mains voltage. To this end, a monolithic AC-DC converter is realized in a 350nm CMOS technology. Based on a switched capacitor approach, the 110Vrms US-mains is down-converted to a lower DC-voltage.

Elly De Pelecijn• Promotor Prof. M. Steyaert michiel.steyaert@kuleuven.be• Research topics Monolithic power management, AC-DC conversion, switched-capacitor circuits

1.2 Mains facing AC/DC power conversion with efficient standby mode

System overview of two-converter model & chip micrograph.

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Dynamic Voltage Scaling (DVS) balances performance and energy consumption and is a widely used technique to improve power efficiency. Although DVS is a powerful technique, from a power management perspective, this is far from ideal as each block requires its own dedicated wide-ranging output converter. Furthermore, all these converters are highly loaded as they have to convert all the power their loads consume, resulting in significant area and energy losses in the power deliver (PD).

Voltage Domain Stacking (VDS) significantly reduces the overhead of the power delivery because, due to charge recycling, only the mismatch current has to be converted. When loads are matched (draw nearly identical current, the converter barely converts power, unlocking system efficiencies close to 100% regardless the efficiency of the converter itself. Combining both VDS and DVS offers opportunities to drastically improve overall system efficiency, this is, however, at the cost of a complex converter.

In this research, a switched capacitor converter that is able to supply two stacked loads with a wide DVS-range has been developed. Seven topologies have been implemented in a single gearbox together with a fully integrated threefold control loop. Measurements demonstrate a peak system efficiency of 98.2% while both load voltages can vary between 0.45V and 0.9V. This is by far the widest reported DVS-range for stacked loads.

Tim Thielemans• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be• Research topics Switched capacitor DC-DC

converters, integrated power management

1.3 Load Stacking with Dynamic Voltage Scaling towards highly efficient energy storage

A switched capacitor DC-DC Converter for stacked loads with wide DVS-range in 40 nm CMOS.

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For reliable high-speed communication over a lossy wired transmission line network, line drivers need to provide sufficient signal power across a wide bandwidth (DC-GHz range). To achieve this, line drivers are typically manufactured in III-V semiconductor technologies which offer higher breakdown voltages compared to standard CMOS. These technologies are more difficult to integrate and thus require extra cost.

This work focuses on the implementation of a wideband high-voltage line driver in standard CMOS technology allowing full analog front end integration for DSL applications. There are several challenges in the design regarding linearity, bandwidth, power and efficiency. To increase the output power, higher than nominal supply voltages are being used which require precautions and circuit techniques to counter reliability risk. With these techniques, a maximum reliable output swing of 10.4Vptp is achieved in 28nm CMOS. To achieve a high throughput across the design bandwidth, high-order DMT modulation schemes are being used implying linearity constraints.

These high-order DMT signals have a large PAPR and thus exhibit voltage peaks. Additional effort is made to further optimize line driver power consumption at back-off by exploiting the signal characteristics of the DMT signal.

Jan Cools• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics F line driver, wideband, stacking,

bulk CMOS

1.4 Wideband CMOS line driver for high-speed communication

A 28nm CMOS line driver on measurement PCB.

Related publication: Gurné T., Strackx M., Tytgat M., Cools J., Reynaert P., “A 20Gbps 1.2GHz Full-Duplex Integrated AFE in 28nm CMOS for Copper Access.” in Proceedings of ESSCIRC, 47, pp. 107-110, Leuven, 2017.

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Optical receivers are an integral part of fiber-optic communication systems. For high performance applications, the receiver is usually implemented with an external (expensive) photodiode. Research has been done towards integrating the PN-photodiode with the receiver in a standard CMOS process. However, in current CMOS technologies, the conversion of light is slow and not efficient. Furthermore, silicon PN-photodiodes can only convert light up to a maximum wavelength of 1100nm, which means a CMOS optical receiver with integrated PN-photodiode for the 1310/1550nm long-haul communication wavelengths cannot be realised.

The focus of this research is to investigate alternative photodetectors for CMOS optical receivers. Schottky diodes are being investigated because of their high opto-electric conversion bandwidth and their ability to convert light wavelengths above 1100nm. However, experimental characterisation is first required, as these devices are not included in the design kit of a standard CMOS process. After a thorough characterisation of these novel photodetectors in various CMOS technologies, a first fully integrated 1310nm optical receiver in 40nm CMOS has been designed and tested, reaching error-free performance for bit rates up to 1Gb/s.

Wouter Diels • Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be Prof. M. Steyaert• Research topics Opto-electronics, photodetectors

1.5 Optical receivers in nanoscale CMOS with Schottky diodes

Related publication: Diels W., Steyaert M., Tavernier F., “Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers.” in Proceedings of European Solid-State Device Research Conference (ESSDERC), 47.

Chip photograph of 2 n-well Schottky photodiodes.

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Radiation detectors play a fundamental role in the field of high-energy physics (HEP). They allow the tracking and the measurement of energies of charged particles resulting from highly-energetic particle collisions (14TeV). This provides physicists with the unique capability of experimentally proving existing, as well as developing completely new, physics theories. A very good example of the former is the recent discovery of the Higgs Boson, for which the 2013 Nobel Prize in physics was granted.

The first part of this research focused on the development of a low-noise and low-power front-end (FE) in 130nm CMOS technology for the readout of triple-GEM detectors [1] used for muon tracking in one of the two major experiments at CERN - the CMS Experiment. As a result, a very complex 0.6cm x 1cm chip comprising 128 FE channels (Fig. 1a) was designed, fabricated and measured. A single FE channel demonstrates very good noise-power-timing performance. It consumes 950μW and achieves a noise slope of 25e-/pF for a 45ns peaking time.

The discovery of the Higgs Boson relied heavily on the very high precision of the Liquid Argon Calorimeter detector (LArCD) in the ATLAS Experiment at CERN. Therefore, very high resolution FEs are essential for new physics discoveries. The second part of this research therefore focuses on understanding the properties of deeply scaled CMOS technologies that fundamentally limit the resolution of FEs, as well as the implementation of an extremely high resolution FE (above 16-bits) for the readout of LArCD in the phase-II upgrade of the ATLAS Experiment. The design is challenging, not only because of the necessary resolution but also because of other aspects such as radiation hardness and required lifetime of more than 20 years.

Mietek Dabrowski• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be Prof. P. Leroux• Research topics High resolution and low-noise front-end electronics, radiation detectors

1.6 Very high resolution front-ends for HEP experiments

a) VFAT3 chip comprising 128 FE channelsb) ATLAS Experiment at CERNc) Architecture of a typical FE

Related publication: [1] “Low-noise and low-power front-end in 130nm CMOS for triple-GEM detectors supporting wide range of detector capacitances with gain and peaking time programmability.”, M. Dabrowski et al., Proceedings of IEEE NSS 2017.

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Anthony Coyette• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Test automation, test signal

generation, test infrastructure generation

1.7 Automatic test generation for analog/mixed-signal integrated circuits

The manufacturing process of ICs is never perfect. As a result, fabricated ICs need to be tested to filter out defective chips before they reach the electronic market. Commonly, the applied tests are designed manually and do not provide perfect test coverages. Therefore, solutions are needed to simultaneously improve test coverages and reduce the time required to design tests.

In this research, we develop algorithms that automatically generate optimal test signals for a given circuit. Besides, we develop generic building blocks that can be automatically added to a given circuit in order to facilitate its testing by increasing the observability and controllability. These two areas of focus are combined into a framework aiming at automatically generating test signals coupled to a hardware test infrastructure which ensures the effective testing of an IC with a high accuracy (sub-ppm).

Automatically generated test signals and building blocks are combined to test integrated circuits.

Related publication: A. Coyette, B. Esen, W. Dobbelaere, R. Vanhooren and G. Gielen, “Automatic Test Signal Generation for Mixed-Signal Integrated Circuits using Circuit Partitioning and Interval Analysis”, IEEE International Test Conference (ITC), 2016.

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Nektar Xama• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Analog and mixed-signal testing,

automatic test generation, latent defect testing

1.8 Efficient methods for testing of analog and mixed-signal ICs

Advancements in the automotive industry are approaching fully autonomous vehicles. As a consequence, the number of integrated circuits within these vehicles will increase even beyond the current number of 400 ICs per vehicle. This autonomy also means that safety must be guaranteed by ensuring that the ICs do not fail in the field. Safety can be compromised by faults caused by hard defects that are introduced during fabrication. These defects change the circuit topology and can catastrophically impact the function of ICs. Latent defects are especially troublesome because their effect is activated after an unknown period of time, which unfortunately can be long after the testing.

A design-for-test method called Topology Modification has been proposed to activate these latent defects in analog ICs. It consists of adding CMOS transistors connecting internal nodes to supply or ground level. By combining a number of these modifications, a trade-off between testing time, area cost and latent defect activation can be achieved.

Related publication: N. Xama, A. Coyette, B. Esen, W. Dobbelaere, R. Vanhooren, and G. Gielen, “Automatic testing of analog ICs for latent defects using topology modification,” proceedings of IEEE European Test Symposium (ETS), 2017.

Topology modification trade-offs when applied to a voltage regulator.

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The large increase of the number of silicon chips inside modern automotive applications has created a strong interest to deliver high-voltage mixed-signal integrated circuits with extremely high quality levels. The digital part of the device under test can be delivered with a very high quality (below parts-per-billion (ppb) undetected failures) thanks to structured automated test methods that use fault models based on the physical defects. Such a structured methodology does not exist yet for the analog part nor for the analog/digital boundary of the device under test. Today, analog blocks are typically tested in an empirical way in accordance with the functional and performance specifications. As a result, the analog tests are long and expensive compared to the digital ones, and there is no quantification of the actual coverage of real physical defects by the applied tests.

This research, therefore, focuses on built-in self-test techniques and fault modeling to improve the testability of mixed-signal and analog circuits. On the one hand, better fault models for analog defects are examined to assess better the actual fault coverage value of the mixed-signal and analog circuits. On the other hand, a defect-oriented design for testability approach is developed to increase fault coverage up to the desired quality levels.

Baris Esen• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Design for testability, analog and mixed-signal test

1.9 Sub-ppm design for testability for analog and mixed-signal ICs

Using visible light as an activation mechanism makes open defects easily detectable.

Related publication: B. Esen, A. Coyette, N. Xama, W. Dobbelaere, R. Vanhooren, G. Gielen, “Non-Intrusive Detection of Defects in Mixed-Signal Integrated Circuits Using Light Activation”, proceeding International Test Conference (ITC) 2017.

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The aggregate I/O bandwidth needs to be increased to multi-terabyte/s at < 1pJ/bit. To do so, optical interconnects have been proposed to replace electrical interconnects. An electro-optic (E/O) modulator is a key component of this optical link. It realizes amplitude modulation of the incoming laser beam with the to-be-transmitted electrical signal. The amplitude of the resulting optical eye is determined by optical modulation amplitude (OMA), which is maximum at an optimum wavelength (λopt).

A micro-ring modulator is considered as a suitable E/O modulator for attaining high-bandwidth-density optical interconnects in CMOS compatible Si technologies. However, due to its resonant behavior, any misalignment between λopt and the incoming laser wavelength (λlas) significantly reduces OMA, inhibiting modulator operation. This misalignment can result from the thermal (80pm/°C), process and laser wavelength variations. Thus, an active control strategy which accurately locks λopt to λlas is of key importance for the success of this technology.

In this work, a low-power CMOS control circuit is proposed which is based on the direct monitoring of OMA at the drop-port of the ring modulator. It feedback controls the modulator temperature to achieve an effective wavelength locking. This is demonstrated for a 4Gbps wirebonded CMOS-Si photonics (SiPh) optical transmitter. The CMOS chip (28nm) contains an OMA monitoring circuit, a dither-based slope quantizer and a modulator driver. The SiPh chip, on the other hand, contains a ring modulator, a heater and a photodiode. The demonstrator showcases wavelength locking with an accuracy of 2.2pm (~0.03°C), a speed of 540pm/s (~6.8°C/s), and a tuning range of 5nm (~62.5°C).

Saurabh Agarwal• Promotor Prof. M. Steyaert michiel.steyaert@kuleuven.be• Research topics Optical interconnects, Si ring modulators, CMOS control circuits,

thermal stabilization.

1.10 Wavelength-locked ring-based CMOS-SiPh optical transmitters

(a) SiPh chip (b) CMOS chip (c) Wirebonded transmitter(d) Wavelength locking measurement setup

Related publication: S. Agarwal et al.,”Highly integrated wavelength-locked Si photonic ring transmitter using direct monitoring of drop-port OMA,” in IEEE European Solid State Circuits Conference (ESSCIRC), Leuven, 2017, pp. 111-114.

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In this research, automotive industry’s one of the biggest safety issues, electromagnetic interference (EMI) phenomenon is being investigated with a focus on transient disturbances. On-board and on-chip solutions for EMI reduction have been carried out for many years now. However, the disturbance waveforms were considered to be continuous sinusoidals and or modulated signals. Over the recent years, automotive industry came to realize that many fault conditions, deterioration and or total loss of functionality cases are being encountered as a result of transient disturbances. These disturbances are quite different by nature compared to the continuous ones. Being much larger in amplitude and much shorter in time, these broadband signals must be treated with a different approach. These disturbances can be considered a transition between continuous ones and electrostatic discharge phenomenon. However, the window between the two is quite large and circuit techniques to cope with such signals must be developed.

For transient immunity of ICs, a new project has been started in collaboration with academy and automotive industry. This project has both IC and system level considerations. First IC goals are to design transient EMI robust circuits utilizing latest transient immunity standards e.g. ISO 7637-2, IEC 62215-3. These circuits are low dropout voltage regulators (LDO), digital to analog converters and analog / digital drivers which are basic building blocks encountered in an automotive sensor interface systems.

As part of the project, a transient tolerant Class-AB analog amplifier has been designed and taped-out in 0.18um CMOS technology. Measurements results prove the usefulness of the circuitry from a EMC point of view and will be contributing to the state of the art, as it is the first transient robust analog amplifier to the best of our knowledge.

Burak Baran• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be Prof. M. Steyaert• Research topics Mixed-signal design, EMI robust

ICs, transient immunity

1.11 Transient EMI immunity of Integrated Circuits

Micrograph of the transient-robust analog amplifier.

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2. RF, mm-wave &THz circuits

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MICAS has always been one the leading institutes to show the usage of CMOS for RF and mm-wave communication, resulting in the mobile age of today.

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Applications such as software-defined and cognitive radios are demanding multi-band and multi-standard operation, which requires the design of highly flexible and integrated circuits. In this work, we have explored the design of variable-gain amplifiers and a high-IF receiver.

Two low-noise variable-gain amplifiers (LNVGA) have been implemented in 130nm CMOS. The first prototype achieved a NF of 4.9dB and gain tuning range of 35dB. It covers the band from 0.4 to 3.3GHz. The second prototype achieved a 3.3dB NF and 45dB gain tuning range. It also covers a broader band than the first one, from 0.2 to 3.3GHz. As a next step, a wideband high-IF receiver using a modified charge-sharing bandpass filter (SC-BPF) has been designed in 40nm CMOS. The modified SC-BPF enhances the Q-factor of the filter with a minimum increment in the area and the power consumption.

Filipe Baumgratz• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be prof. S. Bampi (UFRGS) Prof. M. Steyaert• Research topics RF and analog circuits

2.1 A low-noise variable-gain amplifier and a wideband high-IF receiver for cognitive radio

LNVGA I (bottom left), LNVGA II (top left), and High-IF receiver (right).

Related publication: F.D. Baumgratz, et al, “40 nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-factor,” IEEE TCAS I, Accepted, 2018. F.D. Baumgratz, et al, “A 0.4-3.3GHz Low-Noise Variable Gain Amplifier with 35 dB tuning range, 4.9 dB NF, and 40 dBm IIP2,” AICSP, 2017.

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Next generation mobile technology (5G) is on its way to delivering mobile experience with higher data rates and enhanced link robustness. Millimeter-wave phased arrays offer a path to support multiple users with high data rates by establishing wide band directional links between base stations and user equipment.

To realize these potential use cases, a 5G phased array station must support a large number of precisely controlled beams. Therefore, phase shifter with wide tuning range but also high phase resolution are preferred. To enable effective deployment, they are also required to be compact and efficient, which need a highly efficient, linear power amplifier and with compact antenna array integration.

This work presents a planar active phased array for 5G mobile communication in 40nm bulk CMOS. The design consists of a phase shifter with 360 degree tuning range and 10 degree resolution, a linear PA supporting 64 QAM signals up to 6Gbps with high efficiency, and a scalable planar phased antenna array with broadband performance.

Yang Zhang• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Millimeter-wave CMOS, phased

array, packaging, PA, phase shifter

2.2 Active phased array for 5G mobile communication

Related publication: Zhang Y., Reynaert P., “A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communications in 40nm CMOS.” in Proceedings of RFIC, pp. 1-4, 2017.

Architecture of the designed active phased array for 5G mobile communication.

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A wideband AM-PM compensated class-AB power amplifier suitable for highly integrated 5G phased arrays is designed in 0.9V 28nm CMOS without RF ultra-thick top metal.

Design techniques to realize broadband impedance transformation, power division/combining and phase distortion linearization are discussed. Further, second order effects due to practical layout constrains imposed by deep-scaled technologies are addressed and simple design solutions are proposed.

The designed PA shows a measured S21 -3 dB bandwidth from 29 to 57GHz (65%) with |AM-PM| < 1° up to P1dB. The measured Psat is 15.1dBm over > 56% BW-1dB, with a peak PAE of 24.2%. When a signal with wide modulation bandwidth is applied, the realized PA enables up to 10.1, 8.9, 5.9dBm average POUT while amplifying a 1.5, 3, 6Gb/s 64-QAM respectively at 34GHz. The in-band and out-of-band linearity measured in EVM and ACPR are always better than -2 dB and -30dBc respectively, without any digital pre-distortion.

This research work won the 2017 IEEE RFIC Symposium Best Student Paper Award–3rd Place.

Marco Vigilante• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics 5G, power amplifier, mm-wave

2.3 A wideband class-AB power amplifier with 29 to 57GHz AM-PM compensation in 0.9V 28nm CMOS

28nm CMOS AM-PM linearized wideband PA and measured CW performance.

Related publication: M. Vigilante and P. Reynaert, IEEE JSSC, 2018.M. Vigilante, E. McCune and P. Reynaert, IEEE Solid-State Circuits Magazine, Summer 2017.M. Vigilante and P. Reynaert, IEEE RFIC, 2017.

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The demand for cellular data traffic is growing swiftly. This demand forces 5G standardization towards the high data rates in the order of gigabit per second. As a result, several bands from 1 GHz to 40 GHz is discussed to be used for 5G such as 1.5 GHz, 2.1 GHz, 2.3 GHz, 2.6 GHz, 3.1-4.2 GHz, 4.8-4.99 GHz, 24.25-28.35 GHz. Considering the number of different channels for 5G, it is evident that one transceiver for each band would be cost prohibitive for mobile devices and nanocells that will be used for high speed indoors connectivity.

In this work, we propose a unique distributed power amplifier that has 500 MHz to 31 GHz BW, implemented in 22nm SOI. The distributed power amplifier has an output power above 15dBm with 20dB gain. This results in a gain-bandwidth product of more than 2.5 THz.

Umut Çelik• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics RF, mm-wave circuits

2.4 Broadband power amplifier design for 5G nanocells

Layout of the design.

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Due to increased interests in self driving cars, the demand for sensors in the automotive industry is gaining more traction. One of the main sensors used to detected the surroundings in ADAS(Advanced driver-assistance systems) are radar systems. These systems are able to measure both range and velocity of the target, giving the processing unit valuable information about it’s surrounding. There are various frequency bands in use today for automotive radar; 24GHz, 77Ghz. While 24Ghz is fading out due to it’s limitations in bandwidth, the 77GHz spectrum is very popular nowadays in commercial products due to the higher bandwidth availability that it offers, therefor offering better velocity and range resolution. Current research is even moving towards 140 GHz radar modules that are even more compact and highly sensitive.

mm-Wave power amplifiers are used to drive the antennas of transmitters in radar modules. Efficiency, linearity and output power are important parameters. PA’s are usually designed for a fixed antenna load impedance, however in real life applications this impedance is most definitively not constant and changes depending on the environment. This means that the PA is not operating at the optimum point anymore for which it was designed. Being able to measure the true power that is delivered to the load by the PA, even under antenna load mismatch, is thus very important. When the load impedance changes, and being able to accurately measure these changes, the PA can be biased differently to improve it’s output power, efficiency and linearity.

By detecting both the current and voltage signals that are delivered to the load and using a simple mixer to multiply these two signals, a DC voltage is generated that is proportional to the true power delivered to the load. Thus allowing true power detection for a PA even under antenna load mismatch.

Valdrin Qunaj• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Power amplifiers, power detectors,

mm-wave circuits

2.5 Power detector for PAs operating at mm-wave frequencies

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5th generation mobile networks (5G) will provide 100x higher data rate at 100x higher network efficiency. The spectrum in the low GHz range is already over crowded, therefore mm-Wave wireless communication is going to happen in the near future.

When a multiphase subharmonic mixer is driven with N differential phases, a tone at fRF can be downconverted by a local oscillator running at 2·fRF/N. If we consider a subharmonic direct conversion receiver for E-Band applications and imagine to find a way to generate N = 8 differential phases, the PLL could run at fLO = 2· 80GHz/8 = 20GHz. This would greatly improve the phase noise at the output of the mm-wave PLL key bottleneck for the system performance.

In this research coupled distributed oscillators are adopted to generate 8 differential phases and allow quarter harmonic downconversion in the E-Band. Benefited by the proposed solution, the measured phase noise, tuning range and power consumption of the LO generation and distribution network significantly advance the state-of-the-art. This research was presented at ISSCC 2018.

Marco Vigilante • Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics 5G, downconverter, distributet

oscillators, mm-wave

2.6 A 28nm coupled-RTWO-based subharmonic receiver for 5G E-band backhaul links

Conceptual block diagram of an RTWO based I/Q quarter harmonic receiver (fLO=2fRF/8).

Related publication: M. Vigilante, P. Reynaert, “26.7 A Coupled-RTWO-Based Subharmonic Receiver Front-End for 5G E-Band Backhaul Links in 28nm Bulk CMOS,” IEEE ISSCC 2018.

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The constant demand for higher data rates can be answered by going towards mm-wave frequencies and exploiting the readily available higher absolute bandwidth. As it becomes more challenging to design at mm-wave frequencies, where the available gain is limited by Fmax, less complex modulation schemes tend to be more favorable. Although FSK is not the most bandwidth efficient modulation scheme, low-complexity and low-power modulation and demodulation structures can be implemented. In order to compensate for process voltage and temperature variations, without the need for high power consuming carrier recovery blocks, an automatic tuning loop in the receiver can be implemented. This feedback is provided through an tunable phase shift in the demodulator. The phase shifter is implemented as a transformer-based fourth order network with capacitor bank in 28nm bulk CMOS.

Maxime De Wit• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Polymer microwave fiber, mm-wave,

phase shifter, FSK receiver

2.7 An F-band phase shifter for automatic tuning in an FSK receiver

F-band phase shifter and measurement result (left) system level overview (right).

Related publication: M. De Wit and P. Reynaert, “An F-band active phase shifter in 28nm CMOS,” 2017 IEEE MTT-S International Microwave Symposium (IMS), Honololu, HI, 2017, pp. 965-968.

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To achieve bidirectional communication in a polymer microwave fiber (PMF) link, an orthogonal behaviour between up- and downlink has to be realized. This reduces the self-interference and avoids that both up- and downlink signals become undistinguishable. Typically, time and frequency act as orthogonal signalling dimensions. We investigated the possibility to draw on other orthogonal signalling dimensions, in this case common mode versus differential mode behaviour.

A 120-GHz in-band full-duplex (IBFD) PMF transceiver with tunable electrical-balance duplexer with on-chip antenna is implemented in a 40-nm bulk CMOS technology. The self-interference (SI) cancellation is achieved with a fully-differential transformer-based electrical-balance duplexer, resulting in a SI suppression of 30 dB over a bandwidth of more than 14 GHz. The insertion loss of the duplexer is less than 11 dB from TX to fiber and less than 12 dB from fiber to RX at a frequency of 120 GHz. The balancing network impedance can tolerate load impedances from 45 Ω to 93 Ω and 38 fF to 266 fF at 120 GHz. For IBFD operation, the maximum measured data rate is 6.2 Gbps. The transceiver with integrated antenna occupies an area of 1.8 mm × 1.53 mm and has a DC power consumption of 73 mW in total.

Niels Van Thienen • Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics mm-wave transceivers, plastic

waveguides, flip-chip packaging, In-band full-duplex

2.8 A 120GHz in-band full-duplex PMF transceiver with tunable electrical-balance duplexer

Die micrograph of the transceiver chip with outer dimensions of 1.8 x 1.53 mm2.

Related publication: N. Van Thienen and P. Reynaert, “A 120GHz In-Band Full-Duplex PMF Transceiver with Tunable Electrical-Balance Duplexer in 40nm CMOS”, in IEEE European Solid-State Circuits Conference, ESSCIRC, Leuven, 2017.

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This research focuses on short distance galvanic isolated links using mm-Wave communication. Galvanic isolation is key to control and drive high voltage electronics (e.g. trains, wind turbines, electric vehicles ...). Traditionally opto-isolators are used to ensure high galvanic isolation (>50 kV). However at higher temperatures (> +85°C) the functionality of these opto-isolators reduces drastically, mainly by the conversion from electrical to light.

By using mm-Wave frequencies (30-300 GHz) a small size, low loss, dielectric fiber can be used as a directive channel. Besides acting as a directive channel this dielectric fiber can also serve as a galvanic isolator for short distance communication links. Compared to opto-isolators the conversion from electrical to EM-wave is less affected by temperature. A full transceiver, together with the fiber and antenna, could be integrated in a board-to-board communication module.

A 120 GHz galvanically isolated communication is proposed with an OOK transmitter, 100 mm PTFE fiber as directive dielectric channel and a temperature compensated OOK receiver. Both implementations incorporate an on-chip antenna and are fabricated in 28 nm CMOS. This work achieves an operating range from -40 to +200C and has a latency as low as 1 ns. Moreover the power consumption is drastically lower compared to existing optical-based implementations.

Simon Ooms• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Galvanic isolation, mm-wave, RF, temperature compensation, dielectric fiber

2.9 A low-latency 120 GHz galvanically isolated link operating from -40 to +200C

Die photograph of 120 GHz OOK TX/RX and 3D-printed prototype of a board-to-board isolated link.

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Benefiting from the flat frequency response and low propagation loss at mm-Wave, communications through dielectric waveguide (DWG) channels can achieve multiple Gbps data rate without the need of power hungry baseband equalization techniques.

However, to enable practical applications of dielectric waveguide data link, several issues have to be solved. First, considering the unavoidable evanescent field outside the dielectric core, the propagation is sensitive to environmental interference, and severe attenuation or radiation leakage can be induced due to channel bending or touching. The proposed solution is to design a low loss cladding to protect the core and to increase the working frequency where the field is more confined within the waveguide. Secondly, to enable a robust data link against process, voltage, and temperature (PVT) variations, an automatic built-in tuning for optimal performance is preferred in the transceiver. Thirdly, in the mm-Wave range the available gain of the CMOS transistor decreases rapidly along with noise figure deterioration. Finally, the interconnect from the IC to the DWG is critical to the system performance given the limited available output power. Consequently, reducing the high frequency circuit complexity significantly relaxes the system design, while a low loss IC-DWG transition improves improve the overall link performance.

Considering these challenges, a 28nm CMOS fully packaged dielectric waveguide communication link with automatic tuning loop is designed. This automatic tuning loop significantly improves the system robustness against PVT variations without significant power increase. A cladded PTFE DWG and a broadband IC-DWG interconnect are designed to complete the link. The complete link achieves 10 Gbps over two meter distance with a foam-cladded channel, without error correction or equalization.

Maxime De Wit, Yang Zhang• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics mm-wave CMOS, transceiver,

packaging,dielectric waveguide, communication

2.10 A 140GHz DWG communication link with automatic tuning

Photo of the 140GHz DWG data link measurement.

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With the ever growing need for high speed data links, there is a trend in operating at higher frequencies. Conventional wireline links suffer high losses at these frequencies which is solved by making use of dielectric waveguides. In this research, the goal is to develop a THz ribbon cable, operating at 400GHz. By moving to such a high carrier frequency, the cross section of the dielectric waveguide is reduced to a point where it becomes practical to have multiple closely spaced channels in a ribbon cable configuration, or embedded inside a PCB. The pictures below show the results of a third harmonic OOK transmitter in 28nm CMOS, capable of transmitting 5Gbps at 400GHz. An in-house micro-fabricated coupling structure has been developed to efficiently couple the power from the transmitter into the THz waveguide.

Alexander Standaert• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Dielectric waveguides, THz circuits

2.11 Data communication through THz ribbon waveguides

Harmonic OOK transmitter in 28nm CMOS, capable of transmitting 5Gbps at 400GHz.

39

In Terahertz (THz) applications such as imaging and high data-rate communication, phased-arrays can play important roles because of their beam-forming and beam-steering capability. These applications often require a phased-array transmitter with high radiated power and accurate beam-steering functionality at THz freuqency. Conventionally, THz phased-array are usually implemented using bulky and expensive waveguide components. In recent years, there is a growing interest in designing phased-array using silicon-based technology because it has the advantage of compact pacakge, low-cost in high-volume production and full integration with digital circuits.

A 1×4 phased-array architecture based on subharmonic injection-locked oscillators is designed. The chip is designed and fabricated in 40 nm CMOS technolgy. Combining the radiation from four triple-push oscillators, -11.6 dBm radiated power is achieved at 532 GHz. A scan range of 60 degree is achieved in this phased-array design.

Guo Kaizhe• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics THz Radiator, oscillator, phased

array

2.12 A 0.53 THz steerable phased-array in 40 nm CMOS technology

A 0.53THz Steerable Phased Array in 40 nm CMOS.

40

The THz frequency range is still relatively unexplored frequency range. Whereas Silicon technology is ideally suited for the RF and mm-wave range, and III/V technologies can cover the optical frequency range, the THz gap lacks a good technology platform.

In this project, non-linear circuit techniques are investigated to go beyond the fmax of silicon (CMOS and SOI) technologies. The focus of this research is on THz receivers for communication and sensing. The detection of both amplitude modulation and phase modulation above fmax is being explored both at the circuit and system level. The phase detection is particularly interesting, since it enables development of the wide variety of modulation schemes and sensing applications. Together with a THz transmitter, a complete telecommunication link or sensing application will be developed.

Dragan Simic• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics mm-wave & THz circuits, Imaging

2.13 Terahertz CMOS receivers

Block scheme of the super-heterodyne receiver.

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3. Mixed-signal design& data converters

43

Mixed-signal design requires thorough cross-domain knowledge in order to grasp all opportunities arising from digitally-enhanced analog as well as analog-enhanced digital. The breath of the MICAS research team allows to truly exploit this.

44

High Performance ADCs are highly demanded in wireline/wireless communication systems. However the need for high speed is always accompanied by high power consumption and/or accuracy degradation since since analog devices with high bandwidth are needed or complicated techniques are utilised to achieve high speed.

The first part of this research involved understanding the fundamental speed-limiting factors in SAR ADCs. Based on this understanding, novel circuit techniques were proposed to push the sampling rate and bandwidth of medium resolution single-channel SAR ADCs beyond its architectural limits, while ensuring minimum performance degradation over the whole band of interest. The proposed techniques resulted in a 28nm CMOS prototype, achieving 7b, 1.25GS/s and 5GHz input sampling ability, with only 1.3dB SNDR degradation between low frequencies and Nyquist and a total of only 3.9dB degradation at Nyquist from its nominal quantisation level. The prototype consumes 3.56mW from a 1V supply, resulting in a state-of-the-art Nyquist FoM of 34.4fJ/conv-step.

The second part of this research is to further introduce system and circuit techniques that will also put the resolution in the equation. Novel hybrid solutions are being investigated, targeting both high-speed and high resolution hybrid ADCs, overcoming the traditional “speed vs. resolution” bottleneck, and pursuing FoMs beyond state-of-the-art.

Athanasios Ramkaj• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be Prof. M. Steyaert M. Pelgrom• Research topics High-speed/high-resolution A/D

and D/A converters, high-speed analog/mixed-signal systems

A custom design transceiver with a FPGA board together with a circular polarized patch antenna.

3.1 High-speed high-resolution hybrid CMOS ADCs for wireline/wireless communication systems

Related publication: Athanasios Ramkaj, Maarten Strackx, Michiel Steyaert, Filip Tavernier “A 36.4dB SNDR @5GHz 1.25GS/s 7b 3.56mW Single-Channel SAR ADC in 28nm Bulk CMOS,” in Proceedings of European Solid State Circuits Conference (ESSCIRC), Leuven, Sept 2017.

45

The rapid development of wireless standards requires an ever broader signal bandwidth of the baseband circuits, while maintaining sufficient dynamic range and a good power efficiency. For example, the long-term-evolution advanced (LTE-A) standard aggregates up to five downlink channels, which needs a RF bandwidth of 160 MHz with a large dynamic range. Continuous-time Delta-Sigma modulators are good candidates to be used as baseband ADCs in such wireless receivers.

An ASAR-assisted continuous-time 4-0 MASH Delta-Sigma modulator has been designed and fabricated in 28-nm bulk CMOS. In the first loop, a 4th-order feedforward topology is implemented to achieve a good power efficiency. A 4-bit ASAR quantizer is adopted to replace the power-hungry flash quantizer. The intrinsic quantization error of the ASAR is sampled and fed to the second loop, which consists of a 3-bit ASAR. In order to linearize the mismatch of the main feedback DAC in the first loop, a half-range dithering-based calibration technique is proposed, which does not introduce more excess loop delay. The design overhead of the calibration technique is negligible, in terms of power consumption and area. The modulator operates at 1.7 GHz and achieves a dynamic range larger than 70 dB over an 85-MHz bandwidth.

Hui Liu• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Mixed-signal design, Delta-Sigma modulator

3.2 Power-efficient Delta-Sigma modulators with high bandwidth

Die micrograph of the 85-MHz wideband Delta-Sigma converter in 28-nm CMOS.

Related publication: H. Liu, G. Gielen, X. Xing,”An 85MHz-BW 68.5dB-SNDR ASAR-Assisted CT 4-0 MASH Δ∑Modulator with HalfRange Dithering-Based DAC Calibration in 28nm CMOS”, Proceedings of CICC 2018.

46

The rapid development of modern communication systems presents diverse challenges on the analog-to-digital converters (ADCs). The demand of high bandwidth and low power ADCs to serve as the interface between the analog and the digital world continues to increase. The goal of this research is to develop extremely efficient ADCs for high-speed, moderate resolution applications.

The traditional voltage domain successive-approximation-register (SAR) conversion is accurate but the speed is limited by its loop searching nature. On the other hand, time domain conversion can fully exploit the speed of state-of-the-art CMOS technologies, but it suffers from serious accuracy limitations. In this research, a voltage/time hybrid architecture is being exploited to enhance the speed and power efficiency of traditional voltage domain ADCs while not suffering from the time domain problems. As can be seen in the figure below, the proposed ADC operates in two steps. First, the input signal is processed in the time domain by using a high-speed time-to-digital converter (TDC). Second, the voltage residue produced by the capacitive DAC is amplified and converted to time again for the second TDC. By combining the advantages of different types of ADCs, this hybrid ADC is able to achieve excellent performance.

Yifan Lyu• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be• Research topics Analog, mixed-signal circuits

3.3 Design of low-power high-speed hybrid ADCs

Block diagram of a voltage/time hybrid ADC.

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RA VTC TDC4

8

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Advancements in modern electronics systems such as wide-band re-configurable radios,instrumentation applications and radar systems pushes the linearity and speed requirements of digital to analog converters to the limit. A wide-band linear DAC enables direct RF synthesis, leading to a highly flexible systems where most signal processing can be implemented in the digital domain. Nyquist current steering DACs facilitates wide-band operation with limited linearity while delta-sigma DACs allows higher linearity over limited bandwidth. Hybrid architecture shown below in Figure .1 combines the advantages of both architectures. Dual rate hybrid architecture leads to minimal analog complexity and maximizes the bandwidth and linearity at the same time.

In this work, input data bits are split between a Nyquist path and an oversampling path. The input bits passed through Nyquist path ensures output power and hence the bandwidth. Delta-Sigma modulator in the oversampling path reduces number of bits and thereby minimizes the net number of unit cells needed in the current steering DAC. The oversampling aides in achieving higher SFDR by pushing the truncation error out of the band of interest. Also with the aid of an out of band noise cancelling scheme the achievable SFDR over the bandwidth can be pushed to the limit.

Dileep Sreekumaran• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be• Research topics Wide-band DACs, RF DACs, PLL

3.4 Design of wide-band DACs for 5G applications

Architecture of a hybrid DAC explored in this research.

48

The trend towards smaller transistors coupled with lower supply voltages has made digital circuits faster and more energy efficient, but analog circuits do not enjoy the same benefits: noise and distortion become more significant and many popular analog circuit topologies become unusable. The traditional ADC topologies that are currently in use do not scale well to low voltages.

Time-based ADCs use a completely new approach in an attempt to solve the problem of voltage scaling. Analog information is first transferred to the time domain, where it is processed by purely digital circuits. Since this approach replaces most of the analog circuitry with digital logic, it can be used at much lower voltages and can benefit from transistor scaling just like other digital circuits.

This research focuses on a VCO-based design which uses advanced time-domain sampling techniques combined with digital post-processing to deliver significantly higher speed and resolution than previous time-based designs, while still maintaining reasonably low power consumption. The first prototype chip (shown below) contains 32 time-interleaved ADC channels, achieving 7.2 ENOB at 5 GSPS while consuming just 193 mW. The second prototype will include on-chip digital calibration, and is expected to consume just 25 mW while still achieving the same specs.

The end goal is to develop time-based ADC architectures that can compete with traditional architectures in terms of speed, resolution and power consumption in the latest technology nodes, and yet require only a fraction of the area. Since ring oscillators scale well to smaller technology nodes, the performance of these designs can be expected to further improve in the future.

Maarten Baert• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Analog-to-digital converters, time-based architectures

3.5 Advanced architectures for time-based analog-to-digital converters

Die photo of first prototype chip, showing the 32 time-interleaved ADC channels.

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Today the performance of computers and other electronic systems is, among others, limited by the available interconnect bandwidth, and associated power budget, between the sub-systems of the system, in particular, data transfer between processors and memory, between process units or between memory storage units. These are common features of both portable consumer products, such as smartphones and tablets, as well as high-performance computers and servers.

The emerging high-density 3D integration technologies and the rise of silicon photonics offer a scaling path for this interconnect requirement of future systems. Silicon photonics is currently widely used for long and mid-range communication distances, from several km down to tens of meters. For short-reach, it is still consuming more power than traditional copper interconnects but with the advent of new packaging solution, silicon photonics could enter the short-reach area.

In this work, we investigate how new process nodes as new 3D integration technologies are affecting the performances of short-reach silicon photonics links (cm range) compared to copper interconnects. The optical as the electrical links are modeled and optimized to maximize the bandwidth density and minimize the power consumption. Finally, we validate our model on real test vehicle.

Nicolas Pantano• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics 3D integration, silicon photonics

3.6 Impact of electrical and optical 3D integration technologies on high bandwidth systems

Two-chips communicating through a 7mm copper link on an interposer.

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The increasing broadband internet traffic, cloud computing and huge server farms require large amounts of data to be transferred from one place to another. Limits on data transmission can be a barrier on high speed communications. The serial links over which the data is transmitted can be broadly seen as composed of three blocks, the transmitter, the channel and the receiver. The receiver has the dual function of equalizing the channel loss, and recovering the clock and data from the incoming bit stream.

This research focuses on clock and data recovery for NRZ serial links with data rates of 100 Gb/s in standard CMOS processes. Traditional analog implementations use on-chip passives as a loop filter for clock and data recovery, but our goal is to implement a digitally intensive recovery loop to minimize area and sensitivity to process and temperature variations. The loop filter co-efficents can be easily re-programmed to adjust the loop dynamics. If the data is de-serialized to a higher order, bringing down the clock speeds for the digital blocks, then a fully automated design approach is also possible. This also makes it easy to port the design from present to future technologies with decreasing supply voltages.

Ibrahim Kazi • Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be Prof. P. Reynaert• Research topics High speed serial links, clock and

data recovery, SerDes, digitally intensive circuits

3.7 High speed clock and data recovery in standard CMOS

A clock and data recovery loop.

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CMOS image sensors are omnipresent these days, from mobile phones to tablets, surveillance, autonomous cars and biometrics devices. They are a common part of today’s modern society, and a further development of imagers is undeniably to be expected in even more applications, such as real-time robotics, industry 4.0, ambient-assisted homes, etc. At the same time, consumer and industry demands are increasingly getting larger and more demanding in terms of spatial resolution, frame rate, dynamic range and power, as well as robustness. This poses a challenge for research to continuously innovate and to improve all these imager performances simultaneously.

Generally, a CMOS imager system consists of optics, a pixel array, pixel readout circuitry with the analog-to-digital converters, and a digital processing unit. Besides the pixel size and its noise, the analog readout (including the A/D converters) is typically responsible for the overall performance limitations in CMOS imagers and also largely determines the power consumption, especially for higher specifications. The use of 3D-stacking technology for imagers allows to create the degrees of freedom to enable this. Therefore, the main focus of this research lies in optimizing the readout circuitry in 3D-stacked CMOS image sensor devices for achieving a Figure of Merit (FoM) around 2e-nJ with a readout time per pixel below 2µs/pixel. Alternative analog-to-digital converter structures will be developed to fit these objectives.

Nicolas Callens• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics CMOS image sensors, high-performance ADCs, high-performance readout circuits

3.8 High-performance analog-to-digital converters for 3D-stacked CMOS image sensors

Column-based read-out for CMOS image sensors.

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Highly robust sensor systems are becoming increasingly important in many fields such as automotive. Correct functioning and reliability needs to be ensured over temperatures ranging from -40° C to 175°C for long lifetimes of 10000 or more hours of operation. To avoid expensive recalibration steps due to temperature changes, package stress variations and circuit degradation drift errors, sensor interfaces need to resist drift under process and supply voltage variation conditions.

The research focuses on compensation circuits and techniques to achieve drift resilience for time-based BBPLL resistive sensor interfaces. Figure (a) (top) shows the highly-digital BBPLL-based architecture used, which ensures good scalability and compatibility with deeply-scaled CMOS technology nodes. The simulation results in fig. (a) (bottom) show that the highly-digital approach together with the digital-domain chopping technique reduce the drift error over the targeted wide temperature range. The photograph of the 0.18 µm CMOS implementation is shown in fig. (b).

Jorge Marin• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Mixed-signal systems & data

converters

3.9 Drift-resilient BBPLL-based sensor interfaces

Drift-resilient BBPLL-based sensor read-out interface: architecture and chip photo.

Related publication: Jorge Marin, Elisa Sacco, Johan Vergauwen and Georges Gielen, ‘Analysis and modeling of drift-resilient time-based integrated resistive sensor interfaces’, proceedings IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), 2017.

53

Distributed and connected sensors are becoming increasingly important in the emerging era of the Internet of Things (IoT), as they are the gate between the physical world and the ubiquitous electronics. This is the case in many modern-day applications ranging from smart cars to biomedical monitoring, environmental observations, energy control, etc. Ultra-low power consumption in combination with the desired performance are necessary requirements for these sensors and their readout circuits. This can only be achieved by adopting innovative circuit architectures in combination with advanced technologies.

This research, therefore, focuses on investigating novel digital-based design solutions to implement analog sensor readout circuits, aiming at improving their performance at reduced power consumption, while being robust over a wide span of temperature and stress conditions, and guaranteeing a sufficient lifetime. The digital-oriented solution guarantees the area scalability over technological evolutions of the CMOS technology.

Elisa Sacco• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Sensor Interfaces, mixed-signal design

3.10 Design of digital-based high-performance sensor interfaces

Evolution in sensor interface architectures from voltage-based to time-based solutions.

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Electronic devices, such as smartphones, medical devices or sensor nodes, typically observe sensory signals with an ADC, which produces a linearly quantized digital version of the analog stimulus. In contrast, changes in light, sound, weight or numerosity among others, are processed logarithmically by human senses. By non-linearly quantizing the signal, a more efficient encoding can be achieved. More specifically, the encoding can exploit the varying sensitivity of the receiving algorithm to different signal regions, such as e.g. putting more/less attention and resolution around zero-crossings, or around peaks. If we can bring such property also to electronic devices, this not only makes the conversion itself more energy-efficient, but it also saves significant power in the digital back-end by representing sensory data with less bits, while still containing the necessary information.

The proposed non-linear ADC is designed in 90nm CMOS, and can operate upto 33kS/s to encode a sensor signal with as low as 5b, yet while maintaining up to 9.5 ENOB within a region of interest. The converter’s flexibility, operating modes and an example application are shown below. Here, the non-linear interface is used to create an inverse-tangent-hyperbolic transfer-curve to compensate the tangent-hyperbolic non-linearity of efficient open-loop amplification.

Komail Badami, JC Pena Ramos• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Digitally assisted data converters, context aware computing,

low power design, resource efficient analog to information

3.11 Configurable non-linear mixed signal interface for resource efficient sensory analytics

Input-output curves of the non-linear ADC (top), with example application (bottom) and die photo.

Related publication: Badami K., Ramos J-C., Lauwereins S., Verhelst M., “Mixed-Signal Programmable Non-Linear Interface for Resource-Efficient Multi-Sensor Analytics” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2018 IEEE International.

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Logarithmic

Configurability and operation modes [left]

Chip micrograph

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Random telegraph noise (RTN) is a stochastic effect impacting the reliability of CMOS integrated circuits. It is discrete in time, and is caused by defects in the transistor dielectric, trapping and releasing charge carriers from the channel. Like mismatch, it has a stronger impact on small transistors. In order to characterize it well, it is necessary to measure many devices. Transistor arrays are a valuable solution to provide a large enough sample size; yet extracting RTN from each transistor remains a time-demanding and tedious task.

To facilitate the RTN parameter extraction, a novel real-time, on-chip method has been developed. The circuit enables the automatic extraction of mean RTN time constants from a large array of small-area transistors. The on-chip data processing provides a simplified measurement infrastructure, reduces the measurement time by parallelization, reduces the data post-processing effort and extends the measurement frequency band. The methodology has been demonstrated on a prototype chip fabricated in a 28-nm High-K Metal Gate (HK/MG) CMOS technology. The 1.17 mm2 chip includes two arrays of 18,144 transistors each, analog circuitry for sensing and digitizing the RTN signals, and a digital signal processing block. The experimental results agree with the expectations.

Marko Simicic• Promotor Prof. G. Gielen georges.gielen@kuleuven.be Prof. G. Groeseneken• Research topics Reliability, device characterization and simulation

3.12 Real-time on-chip RTN parameter extraction

Circuit implementation of the on-chip RTN characterization method and the chip microphotograph.

ARRAY

I/O

Vref

VG_on

VG_off

VG_on

VG_off

VD_on VD_off

VD_on VD_off

VSVB

Sense

Force

Force Sense

Vref,CM A-1

outin

HPF

HPF

IDACBiasing Readout

Nrtn

Drtn

DigitalprocessingI/O

Vg,ana Vg,dig OutDig

TΩ resistor

Related publication: M. Simicic, et al. “A fully-integrated method for RTN parameter extraction.” proceedings IEEE Symposium on VLSI Technology, 2017.

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Thin-film electronics is very different from standard silicon technology. It can be produced cheaply and allows for making fully flexible systems. However, the mobility of the semiconductor is lower and channels are several micrometres long. Furthermore, only n-type devices are available. These challenges require a quite different design approach compared to CMOS technology.

In this project, we work on several thin-film applications, amongst which are large area imagers and digital blocks. The focus in imaging is on large-area X-ray sensors and fingerprint detection. To enhance the signal to noise ratio for medical X-ray systems, an active a-IGZO pixel matrix was developed and characterised this year. To make flexible fingerprint sensors, a thermal absorption readout architecture was defined and a proof-of-concept imager layout was made. Finally, this year, the first digitally relevant thin-film memory matrices on foil have been designed and published. An overview of said Laser Programmable ROM (LPROM) can be found in the figure below.

Florian De Roose• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be Prof. J. Genoe• Research topics Mixed mode thin-film design,

large area imaging, SRAM on foil, LPROM on foil

3.13 Advanced mixed mode design in thin-film technologies

Architecture, programmed memory and memory matrix micrograph for 128bit LPROM.

Related publication: F. De Roose et al., “A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil,” in IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 3095-3103, Nov. 2017.

57

58

4. Digital circuits & machine learning

59

Digital design at MICAS spans from transistor-level memory design, over custom near-threshold standard cell libraries, to architecture level design on configurable data paths, processors and embedded machine learning.

60

Convolutional Neural Networks (CNN) have come up as top-performing classification algorithms. However, as these algorithms are very computation and memory intensive, they are typically executed on powerful GPU’s, which cannot be deployed on wearable embedded platforms. Hence, CNN-based applications are currently only possible through wireless connections with the cloud. In this work, we design energy-efficient processors for CNNs, enabling advanced pattern recognition in battery constrained systems.

In 2017, we developed an always-on Mixed-Signal Binary Neural Network processor that can be used as a visual wake-up sensor for wearable devices. The chip performs image classification of moderate complexity (86% on CIFAR-10) and employs near-memory data processing to achieve a classification energy of 3.8uJ, a 40X improvement over IBM’s TrueNorth neuromorphic chip. We accomplish this using (1) the BinaryNet CNN algorithm with weights and activations constrained to +1/-1, which drastically simplifies multiplications (XNOR) and allows integrating all memory on-chip; (2) an energy-efficient mixed-signal switched-capacitor (SC) neuron that addresses BinaryNet’s challenge of wide vector summation; (3) architectural parallelism, parameter reuse, and locality.

Bert Moons• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Deep Learning, processor architectures

4.1 Always-on embedded deep learning

MSBNN - A mixed-signal Binary Neural Network Processor in 28nm CMOS.

Related publication: Bankman D., Yang L., Moons B., Verhelst M., Murmann B., “An Always-On 3.8uJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with all Memory on Chip in 28nm CMOS” ISSCC, San Francisco, USA, 2018.

61

Overview

To give Unmanned Aerial Vehicles (UAVs) more awareness of their surroundings, multiple overlapping high-resolution cameras are mounted on it. This allows to fuse the images of these cameras together into 360° frames with both color and depth. Real-time embedded processing of these 360° color and depth maps makes the UAV more aware of its surroundings. Some example applications include person tracking, automated cinematography, traffic monitoring, automatically mapping building, and more.

However, the fusion and processing of the multiple high resolution cameras requires embedded processing at extremely high data rates, for which there currently does not exists a single optimal hardware platform. FPGAs, GPUs and ASIPs all have their benefits and drawbacks, and need be optimally combined into a single platform capable of performing the complete processing at low power and cost. This work pursues the development of such flexible platform for extremely high rate streaming image processing on drones.

Koen Goetschalckx• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Neural networks, computer vision,

digital accelerators

4.2 Extraction an processing of 360° depth images for increased awareness on drones

62

Now conventional scaling tends to stagnate, economic drive must come from improvements at the system level. Neuromorphic computing provides these improvements by developing brain inspired computing fabrics, dedicated for AI workloads, which anticipate the explosion of sensory data we are currently witnessing. One attractive class of algorithms are sparse coding algorithms which learn how to represent high dimensional data in a compact way.

In this work, synaptic device features are exploited in brain-inspired sparse coding algorithms for efficient unsupervised feature extraction. These algorithms are robust to device variations and frequently use circuit-integratable learning rules such as winner-take-all. Storing the sparse coding dictionary in OxRRAM arrays allows to compute representations in the memory without expensive external memory fetches. These arguments motivate the development of a neuromorphic architecture based on synaptic devices and dedicated peripheral circuitry. Benefitting from the non-volatility and intrinsic functionality of OxRRAM devices, sparse codes can be computed at low power which enables embedded feature extraction.

Jonas Doevenspeck• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Neuromorphic computing, cortical

learning, OxRRAM

4.3 Machine intelligent computing with non-volatile memory

63

Deep neural networks (DNNs) have attracted wide attention as they outperform existing inference/recognition techniques. Energy efficient solution is needed as these technique are embed in battery-powered and autonomous platforms. Binary neural network reduces memory requirement while keeps same accuracy as floating point for some applications (like hand written digits). Moreover, it can also help in increasing the throughput. In this work we implemented in memory computing with SRAM which will perform multiplication within the cell. Multiplication within the SRAM gives opportunity to do parallel computing and also reduce energy consumption. Figure shows the energy consumption vs no. of parallel read. Energy/bit improves with increase in parallel reads however, it will increase overhead area and also leakage.

Mohit Kumar Gupta• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Digital circuits, machine learning, In memory computing

4.4 In memory computing with SRAM

Prediction based data compression.

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With the ubiquitous importance of speech recognition for different applications in mobile devices, the need for embedded execution has increased because of privacy, real time and power consumption issues. One example of these speech recognition tasks is Keyword Spotting (KWS), where the objective is to detect specific words spoken by the user. Usually this kind of application acts as a simple user interface or frontend layer that activates a larger speech recognition system. However, the KWS system must be always active, constantly listening to the environment, and hence low power design for this kind of applications is critical.

In this project, we have developed an always-on keyword spotting system based on LSTMs. The accelerator is part of an ASIC for speech recognition (specifically Speaker Verification and Keyword Spotting) and taped out at 65nm. Approximate computing techniques are applied with the objective of reducing the power consumption while maintaining high accuracy and reliability.

The project further targets the development of a smart sensing platform for embedded devices capable of learning from data on the fly. Such embedded learning capabilities would enable the device to customize to its own user at run-time (e.g. a speech interface which starts to adapt to its user progressively).

Sebastian Giraldo• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Machine learning, computer

architecture, digital design

4.5 Hardware acceleration of deep learning algorithms for keyword spotting

Microarchitecture of LSTM Accelerator for Keyword Spotting.

65

Natural speech has become one of the most important interfacing methods to consumer electronics. However, so far, always-listening reactive devices are limited to wall-powered devices such as Google Home and Amazon Echo. Currently, these devices constantly check for keyword utterances with high quality microphone arrays and then process the speech in the cloud to extract the identity and meaning of the speaker. Yet such a setup is not feasible in battery powered devices since the microphone array, the local processing and the communication with the cloud are to power hungry.

This project overcomes these challenges for a keyword recognition and speaker identification sensor node, by integrating hierarchical activation of different machine-learning techniques and a low-power analog microphone front-end on a single chip. A 65nm ASIC was designed, capable of detecting if a keyword is spoken by the specific owner of a device. To minimize its overall power consumption, the chip has an always-on ultra-low power sound detector. Upon sound detection, a Long Short-term Memory (LSTM) accelerator is activated listening for one of multiple configured keywords. After keyword detection, a Gaussian Mixture Model (GMM) accelerator is activated to verify the identity of the person. Such a fine grain hierarchical activation scheme allows for 100x in overall energy consumption, enabling always-on operation within a <50 microWatt overall system power budget.

Steven Lauwereins, Komail Badami, Sebastian Giraldo• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Context-aware machine learning,

adaptive mixed-signal circuits, resource-aware classifier

4.6 Ultra-low power keyword and speaker identification through hierarchical machine learning

Acoustic ASIC for ultra-low power keyword recognition and speaker identification.

Pow

er c

onsu

mpt

ion

100µW

10µW

1µW

Information

Sounddetection

Keywordrecognition

SpeakerIdenti�cation

66

Advances in computer vision create opportunities for visual navigation: To increase safety and efficiency, robots, cars and drones become aware of their environment and start navigating more and more autonomously. For novel applications like small flying robots (micro UAV’s), this poses stringent requirements to real-time, low-power and adaptive image processing. Since computer vision tasks are typically executed on energy-consuming GPU’s or on dedicated hardware with a fixed functionality, traditional platforms are unsuitable for small form-factor, energy-scarce devices.

This research developed a programmable streaming architecture to efficiently perform various computer vision tasks. Exploiting massive task parallelism, the design is capable of real-time video throughputs at low power consumption. In 2018, a prototype will be taped out in a 22nm FDSOI technology to demonstrate the benefits of streaming hardware architectures.

The continuation of this research aims to broaden the streaming processing application range and will explore its application in other domains such as wireline communications.

Sander Smets• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be Prof T. Goedemé• Research topics Processor design, digital

accelerator design, computer vision, optical flow

4.7 Streaming processing for energy-efficient dense optical flow

Streaming architecture concept with programmable elements and configurable interconnections.

67

As scaling continues, the supply voltage of the core digital blocks on a chip tends to decrease. Especially in battery operated low performance applications, aggressive voltage scaling saves siginificant amounts of energy. However, since power delivery typically happens on higher voltages to reduce losses, an on-chip power management unit is needed. These power management units are typically implemented in switchcap DC-DC converters with an efficiency of around 70% and consume a significant chip area.Alternatively, logic blocks could be stacked in the voltage domain. To compensate for current imbalances between top and bottom blocks, only a small regulator is required. It is recommended to minimise the current imbalance between top and bottom blocks at design time. This relaxes the specifications for the regulator, which increases its efficiency.

For instance, a multi-bank SRAM is an ideal candidate to be used in a stacked topology. When the bits of a word are split equally over top and bottom banks, the behavior and thus current consumption of each bank is almost equal. Alternatively, when the bits of a word reside in one bank only, extra voltage scaling can be applied based on the mode of the SRAM (read vs hold or write). Since all banks are mutually exclusive in read mode, the stack supply voltage can be held fixed and internal nodes supply voltages shift based on the SRAM mode. This work implements a 1-10 MHz SRAM using two banks in a voltage domain stacked topology. To demonstrate the impact of this ultra efficient SRAM in the complete system energy budget, it will be used in a biometric measurement platform, currently in development at IMEC.

Bob Vanhoof• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics SRAM design, ultra low energy design

4.8 Voltage domain stacked SRAM in 22nm FDSOI

Layout of the supply of conventional and voltage domain stacked SRAM banks en periphery.

68

The demand for an ubiquotous sensatory environment was never higher. In the mean time, real-time operating conditions of digital integrated circuits play a key role in state-of-the-art systems. The energy overhead resulting from margining for worst case conditions is now a major energy contributor. In situ performance monitoring can eliminate these margins, fully leveraging the energy gains possible through ultra-low voltage operation.

This research enables in situ performance monitoring at ultra-low voltages. Through sparse replacement of flip-flops with error detection and correction flip-flops, real-time timing information about the system is provided. A transition detector flags late data arrival, while a soft-edge flip-flop guarantees error-free operation. As such, near point-of-failure operation is possible. As a benefit from this technique, monitoring overhead is reduced to a minimum, improving overall energy consumption.

An ARM Cortex M0 32-bit microcontroller system was equipped with this system and was implemented in 40nm CMOS. The system operates autonomously in a dynamic voltage scaling loop, tuning the supply voltage to operate near the point-of-first-failure. Measurement results demonstrate a 5-30MHz operating range consuming 11-18pJ/cycle down to 290mV. This is a 75% energy reduction compared to slow-slow corner margined operation. The architecture profits optimally from ultra-low voltage operation since it can overcome intra-die process margins, voltage, temperature and aging effects without post-fabrication calibration.

Hans Reyserhove• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Weak inversion logic, standard cell

design, ultra-low power, better-than-worst-case design

4.9 Margin elimination through timing error detection in near-threshold digital processors

Chip micrograph and system overview of the microcontroller system implemented in 40nm CMOS.

Related publication: Reyserhove H., Dehaene W., “Design Margin Elimination in a Near-Threshold Timing Error Masking-Aware 32-bit ARM Cortex M0 in 40nm CMOS”, IEEE European Solid-State Circuits Conference (ESSCIRC), Leuven, Belgium, 2017.

69

With the ever increasing amount of ‘smart’ devices the era of the Internet of Things is knocking at our doorstep. New generations of these devices are smaller, aim for a longer battery life and yet demand more processing power. In the past years, dynamic voltage and frequency scaling has been explored to overcome these opposing requirements in microprocessors and digital circuits. This exploration has shown us that each processor has its own minimum energy point (MEP) where the available energy is used with the highest efficiency. However, at this moment most practical applications do not exploit the MEP for several reasons. First, the MEP is found at ultra-low supply voltages in the near or even sub-threshold regime making the circuit sensitive to PVT variations. Second, real life applications have binding performance constraints that simply do not meet the performance achieved in the MEP. Last, modern applications often experience strongly varying workload conditions that force the processor to operate at different frequencies and thus outside the MEP. This research provides techniques that enable applications to benefit maximally from the MEP. To that end, the static minimum energy point is converted into a dynamic point that follows the desired performance. This effectively creates a minimum energy point at each frequency. Further, the large and inefficient design margins required as a safeguard against the strong PVT variations at low voltage are minimized. This is done by exploring a novel timing-error detection technique, current sense completion detection (CSCD).Both the dynamic MEP and the CSCD technique have been implemented in a proof of concept processor. The used processor is the Zscale open source processor of the RISC-V project. The Zscale implements the RISCV-IM32 architecture making it comparable with the well-known ARM Cortex-M0.

Roel Uytterhoeven• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Energy efficient digital circuits,

sub-threshold, voltage scaling, timing-error detection

4.10 Energy efficient digital circuits through sub-threshold operation

Zscale implementation in 28nm FDSOI with CSCD to prevent timing-errors.

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The information provided by multi-sensory technologies enables the development of highly complex artificial intelligence systems. Embedded sensory applications, such as activity recognition and robot navigation particularly, benefit from these systems but their always-on functionality is often hindered by the device’s limited resources (e.g. computational power, energy, area, memory, etc). This research targets this shortcoming with the development of “hardware-aware” machine learning algorithms that possess a thorough knowledge of the hardware devices they run in and utilize this information to trade-off hardware-resources and inference quality towards meeting user’s performance demands.

The study has currently focused on bringing hardware awareness to Probabilistic Graphical models, as they facilitate sensory fusion, allow to encode different properties of the same sensory stream and are capable of dealing with missing data. The aforementioned are suitable properties for the embedded sensing applications of interest. We have so far realized Bayesian Network based systems that dynamically tune the quality with which sensory features are extracted in order to optimally trade-off classification accuracy for power consumption. This can enable embedded devices meet user’s performance needs while keeping their always-on functionality feasible.

Laura Isabel Galindez Olascoaga• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Hardware-aware machine learning, probabilistic graphical models

4.11 Hardware-aware machine learning

Related publication: Galindez Olascoaga L., Badami K., Pamula V., Lauwereins S., Meert W., Verhelst M., “Exploiting System Configurability towards Dynamic Accuracy-Power Trade-offs in Sensor Front-ends.” in ASILOMARSSC, pp. 1027-1031, Pacific Grove: CA, 2016.

A Bayesian Network based controller allows to tune the noise allowed in the extracted features.

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Many portable devices such as smart watches and smart phones are inherently equipped with a bunch of sensors, e.g. accelerometers, gyroscopes, microphones, etc. Continuously sensing and measuring the environment then allows one to use these sensory inputs for trending new applications, including Human Activity Recognition, Ambient Assisted Living and Voice Activity Detection. The need to constantly collect and process high quality sensory information strongly dominates the hardware device’s power consumption, however, and typically drains the device’s battery at a much higher rate then desired.

To serve the aforementioned applications, the most common pipeline consists of three main steps. First, several sensors are used to collect the necessary information; Second, the sensory information is converted into useful features; Third, a machine learning algorithm is used to specifically train a model that allows us to perform the task of interest. The aim of our work is to explore different ways to reduce the hardware cost each of these steps comes with, without sacrificing the accuracy of the model.

From the machine learning perspective, we mainly focus on probabilistic models, more specifically Bayesian Networks, as they can be mapped into an arithmetic network after which evaluation of the model on an embedded device becomes straightforward. Instead of constructing one big network, however, we propose to use a hierarchy of networks where each of these smaller networks has a different cost to evaluate the model as well as to compute the required features. This then allows us to, given the context and environment, dynamically pick the most applicable model. To obtain this hierarchy of networks, we mostly rely on expert knowledge as well as extend the learning algorithms to also take into account the hardware cost.

Jonas Vlasselaer• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Machine learning,

probabilistic modeling and reasoning, knowledge compilation

4.12 Hardware aware probabilistic models for resource efficient embedded classification

From raw sensor measurements and expert knowledge towards resource efficient Arithmetic Networks.

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The push for miniaturization of IoT system demands smaller batteries and hence more power efficient sensor systems. This work focuses on sub-μW sense-and-compress systems, that enable an agent to record data for a long time, while consuming minimal energy. This is achieved through flexible hardware and low power on-chip intelligence. The flexible settings (which include sample frequency, compression type and compression harshness) of the agent are optimized off-line using an Evolutionary Algorithm that runs a power-performance model of the complete mote using previously gathered representative data for the mote. Online, the mote adapts itself by detecting the type of environment and deploys the best pre-calculated settings for this environment.

A chip was fabricated in 65nm CMOS to prove this basic principle. Fig.1 shows the system overview. Data is sampled by an external sensor, and depending on the statistics of the signal, different sample and compression settings are used. The chip can sense and compress data with 539nW and 45nW for a sample speed of 10kS/s and 100S/s respectively. A complete system including State-of-the-art Flash memory consumes 90nW to capture human activity accelerometer data at 172Hz with a PRD of 4.1%. This enables very low power capturing of data, which can later be reconstructed and used.

Jaro De Roose• Promotor Marian Verhelst marian.verhelst@kuleuven.be• Research topics Scalable and flexible hardware,

low power online learning, low power digital design

4.13 Ultra-low power self-adaptive sense-and-compress through embedded instincts

System overview of a low power, flexible sense-and-compress chip.

Related publication: M. Andraud, G. Berkol, J. De Roose, S. Gannavarapu, H. Xin, E. Cantatore, P. Harpe, M. Verhelst, P. Baltus, “Exploring the unknown through successive generations of low power and low resource versatile agents”, DATE, 2017.

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The development of novel applications, such as the internet-of-things, initialized an increased focus on reducing power consumption for very resource-scarce devices, so that the circuit always meets system specifications with minimal power consumption. Yet, the optimal circuit settings depend on current operating conditions, system state, etc. All this pushes for the use of advanced adaptation techniques, where the circuit finds its optimal operating point itself directly in the field. To implement energy-efficient adaptation algorithms, we propose to use embedded machine-learning, able to learn the relationships between system specifications, performances, power consumption, and the circuit tuning variables (currents, voltages, etc.), which are usually very complex. The developed technique combines an off-line optimizer, with an on-line circuit adaptation module. The latter monitors the on-line circumstances and configures the circuit using the set off-line pre-optimized configurations This work is applied in the context of the FET-Open project PHOENIX, with the objective to explore unknown environments with extremely small-sized nodes.

Martin Andraud• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Machine-learning, resource-

constrained circuits, analog and mixed-signal circuit adaptation

4.14 Resource-efficient circuit adaptation through machine-learning based “instincts”

Illustration of off-line and on-line adaptation methodologies based on pre-optimization.

CIRCUIT (MODEL)

Tuning Knob (TK)

setting

OPTIMIZER

P

PDC

= Pareto front of best TK(a)

DC power(PDC )

Perfor-mances

(P) PDC_spec

Pspec

FRONTEND

SENSOR

T. KNOB

Copx

TKx

ON CHIP

(b)

Operating Conditions

Cop

= optimal TK for the circuit Off-line adaptation:

On-line adaptation:- measure Cop- Apply best TK- If combined withoff-line: pre-trainedLUT to find Cop TK

LUTCop1 TK1

TKn

… …Copn

Related publication: Andraud M., Berkol G., De Roose J., Gannavarapu S., Xin H., Cantatore E., Harpe P., Verhelst M., Baltus P., “Exploring the unknown through low power and low resource versatile agents.” in Proceedings of DATE, 2017.

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5. Biomedical systems

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Biomedical implants form a long term flagship in MICAS’ research applications, merging low power design, micro fabrication and 3D packaging and interconnects. Recently, focus is on flexibility for comfortable monitoring.

76

A new medical revolution is ahead, due to the development of tiny sensing and actuation devices that aid in the diagnosis and treatment of major diseases. To control these devices, a reliable communication protocol is needed. This is however challenging with current RF technology, as RF waves do not propagate deep into human tissue and pose health risks. Ultrasound waves counteract these effects, as shown by long distance underwater communication and medical imaging applications. This work targets to demonstrate the feasibility of ultra-sonic communication in human body.

To characterise the human body, static measurements on gelatine phantoms were conducted in cooperation with the Biomedical Dept. KU Leuven (fig. b). Multiple channel transfer functions are extracted (fig. c). Future plans target to develop an optimal communication protocol on first static and subsequently dynamic ultrasound channels. Further, a hardware implementation is envisioned to perform real in-vivo experiments.

Thomas Bos• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be Prof. M. Verhelst• Research topics Ultrasound channel modelling,

low power digital communication

5.1 Ultrasound waves based body area networks

(a) Principle of ultrasound based Body Area Network; (b) Acoustic measurement through gelatine phantom; (c) Extracted channel transferfunction

77

Traditional methods of assessing bladder function are based on intraluminal pressure measurements through a catheter, urine flow and volume measurements, and in some cases electromyography (EMG) of the sphincter muscle. These methods are quite limited in their scope, as they provide only a global measurement and no localized bladder information. To obtain a better understanding of the fundamental bladder mechanics, two new methods for assessing bladder functionality are explored.

Firstly, a system was designed to measure in-vivo acceleration and EMG of the smooth muscle bladder of rats. A real-time wireless readout allows comparison to conventional catheter pressure measurements.

Secondly, a fully implantable wireless system was developed that monitors bladder wall accelerations and pressure. A flexible printed circuit board has been designed for this application, featuring multiple commercially available accelerometers and pressure sensors, along with a wireless communication and power board. The battery-powered system is implanted in pigs and gathers data autonomously for several weeks.

Tristan Weydts• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Implantable systems, sensor

networks, urology

5.2 Implantable sensor network for monitoring the bladder wall

Left: wireless communication board. Right: sensor board on flexible substrate.

Related publication: Weydts, T., Brancato, L., Soebadi, M.A., De Ridder, D., Puers, R., In-Vivo Implantable Sensor System for Measuring Bladder Wall Movements. Proceedings of Eurosensors 2017, 1, 566.

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Because of their high compliance, extendable wires can passively follow the deformation of soft organs and tissues, without hindering their natural movement.

Highly stretchable interconnects have been realized by embedding nickel-plated carbon fibre bundles first in a thin polyurethane tube and then in a soft, elastic, horseshoe shaped polydimethylsiloxane matrix. This multi-layer insulation was designed to protect the conductor from the corrosive body fluids, and to prevent the leakage of electrical current and metal ions into the body.

Carbon fibers are immune to fatigue, making them an ideal candidate for applications where intensive cyclic loading is required. The interconnects were able to survive more than 160,000 cycles to 150% elongation without any damage and with a minimal resistance increase of 0.08 Ω/cm. The use of a bundle of thin nickel-plated CF as conducting elements reduces the stress in the interconnect, resulting in lower stiffness and higher stretchability. Patterning the polymeric matrix in a meander shape, along with the conductors, allowed to fabricate extremely compliant interconnects. The proposed devices can follow the extensive deformations of biological tissues in response to an extremely low tensile stress.

Luigi Brancato• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Medical Implants,

biocompatibility, packaging, soft and

stretchable polymers

5.3 Highly compliant and stretchable interconnects for medical implants

Stretchable interconnect packaging and tensile testing on two devices embedded in PDMS and PDMS/PUR.

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The occurence of abnormal brain cavities is often accompagnied by various symptoms such as chronic pain or reduced motor function. Although several treatment options have been developed over the years, such as medication or Deep Brain Stimulation (DBS) of the affected regions of the brain, these methods are only effective in a limited number conditions.

In this project, a new approach was explored in which clinical symptoms could potentially be alleviated by direct stimulation of the cavity wall. For this purpose a custom, unfoldable, electrode was designed for implantation into subcortical brain cavities. After implantation, using a dedicated cannula-based technique, the electrode unfolds forming an electrical contact with the cavity wall, allowing stimulation as well as recording.

An in vivo experiment is conducted to validate the correct operation of the electrode and its usability in the treatment of brain cavity related clinical symptoms such as central post-stroke pain.

Dries Kil• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Microfabrication, neural

engineering, medical implants, signal processing

5.4 A foldable electrode array for 3D recording and stimulation of subcortical brain cavities

Overview of the neural probe before and after assembly.

Related publication: Kil D., De Vloo P., Nuttin B., Puers B. (2017). A foldable neural electrode for 3D stimulation of Deep Brain Cavities. Procedia Engineering: Vol. 168. Eurosensors. Budapest, 4-7 September 2016.

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Simultaneous electrophysiological of millions of neurons using implantable devices remains one of dream goals of brain/computer interfacing. Achieving this requires development of integrated circuit techniques with a very high level of scalability. This means that components typically used with electrophysiological amplifiers such as on-chip AC coupling capacitors and filters with low time constants cannot be used due to their very high area consumption. For these reasons a protoype CMOS integrated circuit was developed based on an array of near-threshold low noise amplifiers multiplexed using switchable buffer amplifiers that are read out using an external ADC. High pass filtering and offset removal is realized digitally and broadcast with a DAC to every amplifier. The amplifier noise is < 3.5 µV rms in the action potential band.

The prototype chip was fabricated using ON Semi 350 nm process, yielding 256 recording channels on a 1.5 x 4 mm² die, and has passed basic electrical tests. Future work will involve interconnecting with polyimide-based neural probes followed by implantation and testing in animals.

Marko Bakula• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Implantable electronics, chip

design, flexible electrodes, high density interconnects

5.5 Electronic design for high bandwidth neural interfacing

Left: Pixel amplifier schematic diagram Top right: System block diagram Bottom right: Chip imag

Related publication: Neural Interface development at ESAT-MICAS: Resorbable microneedles Nerf Seminar, Date: 15-6-2017.

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Research on low power, portable EEG recording devices have recently gained huge momentum. These devices are already being used for continuous monitoring of brain activity for both therapeutic and neuroscientific research. Near Infrared Spectroscopy (NIRS), a brain imaging technique of growing interest, however, lags far behind when ambulatory monitoring is concerned. It has been recently shown that EEG combined with functional-NIRS (fNIRS) has far greater prospect in decoding brain activity. EEG measures post synaptic potentials associated with neural activation while fNIRS measures local haemodynamic changes associated to the same. These two modalities complement each other in their ability to resolve information about the spatial and temporal characteristics of neural activity. The goal of this project is to design and manufacture a low-power integrated solution for state-of-the-art multi-parameter brain activity monitoring, by means of combining EEG and fNIRS analog front-ends (AFE), a digital interface and (sensor) controller functionality. This chip is a test-chip for a new fNIRS architecture and only includes fNIRS read-outs.

The fNIRS channel is an optical sensing channel based on reflective fNIRs working principle for clinical, ambulatory and fitness applications. It contains all functionality necessary to implement a multi-channel fNIRs with SpO2 applications. This includes:• Low power fNIRS amplifier (integrator) with ambient light compensation.• Current DAC for large input offset dynamic range compatible.• Digital low-pass filter for DC offset compensation.• High resolution dual-slope ADC for data conversion.• Comparator and counter are included.

Qiuyang Lin• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be Prof. C. Van Hoof• Research topics Analog biomedical circuits, optical input EEG fNIRS

5.6 Multimodal integration of EEG and fNIRS

System level architecture.

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Cataract disease can be solved by minimal surgery, replacing the biological lens by e.g. a PMMA/Silicon/acrylic lens. Research about miniature focal adjustable Liquid Crystal (LC) based lenses and required electronics circuitry could lead to next generation active eye lens devices.

Initial efforts were focused on how to equip an eye lens implant with minimal electronic circuitry to detect ciliary muscle movement and control the LC based lens. For such an implantable lens system, the digital controller part was implemented and evaluated in an ultra-low power Lattice ICE40UL1K16 FPGA (1.48mm x 1.48mm µBGA).An I3T50 CMOS ASIC (Fig. 1. left) was developed to evaluate functionality, size and power and compared with a Commercial Off-The-Shelf or C.O.T.S. solution.

Recently, electronic glasses (Fig. 1. right) are under development to power the implantable eye controller electronics and communicate over the same 13.56MHz inductive link. The system is build up around a Royer power oscillator controlled by a PIC 16F1773 Microchip microcontroller. Output power, frequency, modulation and demodulation is controlled by the microcontroller using a handful small C.O.T.S components.

Current research is focused on the analog part of the I3T50 CMOS ASIC and improvements of the electronic glasses.

Patrick Pelgrims• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Implantable biomedical systems

5.7 C.O.T.S. based bionic eye lens glasses and I3T50 digital eye lens controller

I3T50 CMOS digital Eye lens controller chip and Bionic Eye electronic glasses system.

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Electricity is a fantastic driver to stimulate novel bio-electrochemical processes. Micro-organisms, like geobacter sulfurreducens, extract the otherwise lost energy from carbon-rich organic wastewater streams. The controllable electrical settings of these bio-electrochemical systems (BES) determine the process efficiency. Unfortunately, the relationship between the most beneficial electrical settings and the specific microbial community together with the environment conditions is not well understood. This results in suboptimal production and prolonged startup times.

Performing experiments to improve our understanding is both expensive because of the measurement devices required to control a BES and time consuming because of the inherent slow dynamics of the micro-organisms.

This PhD project investigates two research paths to increase our knowledge to improve the efficiency of a BES. The first path involves the modification of the existing extremum seeking control algorithms to find the BES’ optimal electrical settings with a minimal amount of measurements, and this under dynamically varying environments. The second path develops an affordable parallel, highly-programmable sense and actuation platform for BES to extract a dataset suitable for machine learning, as well as to stimulate a BES with unconventional stimulation waveforms.

Tom Molderez• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be Prof. K. Rabaey (CMET, UGent)• Research topics Control Theory, bio-electrochemical sensors

5.8 Micro-electronics for micro-organisms

A 6-channel sense and measurement PCB for extremum seeking control.

Related publication: T. R. Molderez, B. de Wit, K. Rabaey and M. Verhelst, “Successive parabolic interpolation as extremum seeking control for microbial fuel & electrolysis cells,” IECON 2017 - 43rd Annual Conference of the IEEE IES, Beijing, China, 2017.

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Bio-electrochemical systems supply electricity to certain populations of micro-organisms, which are as such stimulated to produce energy and valuable chemicals. Achieving high efficiency for such systems needs adaptive electrical stimuli at run-time to change the surrounding conditions of the microorganisms. However, commercial potentiostats are bulky, expensive instruments with which it is time-consuming to run experiments on bio-electrical cells. To explore the optimal control of bio-electrochemical systems in an efficient way, this work focuses on integrating a large array of potentiostats on one single chip.

64 potentiostats are integrated in a core area of 1.35x1.35 mm2 in 180 nm technology. Each potentiostat unit can stimulate current in a wide range of 50 fA – 1 µA and measure the anode voltage with maximum 3.3 V swing. The 8x8 array is monitored by multiplexing to an off-chip ADC/DAC. Post-processing of the chip in our own cleanroom will be needed to pattern the electrodes on top of each unit to create the interface to the micro-organisms.

Peishuo Li• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Bio-electrochemical system,

analog and mixed signal circuits, control theory

5.9 An 8x8 integrated potentiostat array for bio-electrochemical system

Chip layout of the 64 potentiostat array.

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There is a need for several emerging applications in personal healthcare to add more digital signal processing capabilities and memory storage. While digital integrated circuits and memory benefit from technology scaling in terms of power and area, this isn’t the case for the analog readout electronics. Current state-of-the-art circuit techniques don’t result in a significantly reduced area in scaled technologies, and due to the reduced supply voltage, the analog front-end (AFE) readout chip faces significant challenges in combining a large dynamic range with a small size and a low power consumption.

The research has been looking into a time-domain-based readout AFE architecture which avoids the need for intensive traditional analog circuits, such as high-gain amplifiers and on-chip passives, while leveraging the benefit of technology scaling – low area and low power digital. The feasibility of this architecture has been demonstrated through a prototype of an ECG readout for ambulatory applications. The new ECG readout chip is only 0.015mm2. implemented in TSMC 40nm CMOS. It can handle up to 40mVpp AC signal and up to 300mV DC-electrode offset while consuming only 3.3μW from a 0.6V supply.

Rachit Mohan• Promotor Prof. G. Gielen georges.gielen@kuleuven.be Prof. C. Van Hoof

Analog front-end for low area time-based biomedical readout.

Related publication: Mohan, et al. “0.6V, 0.015mm2, time-based biomedical readout in 40nm CMOS”, Proceedings International Solid-State Circuits Conference (ISSCC) 2016.

5.10 Time-based biomedical sensor readout for low-voltage supply and small-scale CMOS technology

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The research includes a collection of novel electrode-optrode arrays for in vivo and in vitro optogenetic applications. In order to fabricate these tools we have integrated state-of-the-art titanium nitride electrode fabrication with silicon nitride waveguide technology. Both technologies are part of imec’s CMOS compatible technology portfolio for neuronal biosensors and telecommunications, and are highly reproducible, reliable and scalable. In all the presented tools, these waveguides are used to channel light of two different wavelengths (470 nm and 590 nm) into the optrode array site. The light from external sources (light emitting diodes or lasers) is coupled into these waveguides and subsequently out-coupled orthogonally at the array site by means of optical grating couplers. The in vitro device is composed of an array of 8 by 8 titanium nitride electrodes and 8 by 8 optrodes. Each electrode has a corresponding optrode close to it in order to register the response of optically stimulated cells. The optical outputs are approximately 6 by 20 µm2 thereby capable of single-cell stimulation; the electrodes have a diameter of 60 µm. Both arrays have a pitch of 100 by 100 µm2. For in vivo applications, several devices were designed. Some comprise only of optrodes and others have optrodes and electrodes. The optical-only devices are 60 µm wide and the electro-optical 100 µm. All of them contain 24 electrodes and/or 12 optical outputs (6 of each color). Additionally, the electrodes are 15 by 15 µm2, while the optical outputs have the same size as their in vitro counterpart. For each type of probe there are three different lengths: 3, 5 and 10 µm with electrode/optrode pitches of 400, 100 and 100 µm respectively. Each option is available with thicknesses of 50 and 30 µm.

Louis Hoffman• Promotor Prof. G. Gielen georges.gielen@kuleuven.be Prof. B. Puers• Research topics Neuro-engineering,

opto-electronics

5.11 Bio-optoelectronics for Optogenetics

Compact opto-electrical neural stimulation system.

Related publication: Hoffman, et al,”Bio-optoelectronics for Optogenetics”,Proceedings IEEE International Electron Devices Meeting (IEDM), 2015.

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One of the interesting projects we did lately was the fabrication of a novel type of waveguide spectrometer in collaboration with Micos GmbH. It is a nice example of the recent gain in capabilities for rapid prototyping of micro- and nanosystems at MICAS.

For this project, silicon oxynitride - silicon oxide planar waveguides were grown on a silica substrate. Then, 50 nm diameter gold nanosamplers were deposited on the waveguides using e-beam lithography in our cleanroom in the KULeuven Nanocentre.

The customized 2D pattern of nano-samples enhances the the throughput and increases the number of sample points with respect to the state of the art in which only linear waveguides are used. this lead to an increased spectral bandwith of these chip-scale spectrometers that have no moving parts.

The waveguide spectrometer shows a nominal bandwidth of 256 nm at central wavelength of 633 nm thanks to the nanodisks that provide a 0.25 µm sampling interval.

Frederik Ceyssens• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Micro- and nanoscale

fabrication, MEMS, neuroelectronic implants

5.12 Lippmann-based optical spectrometer

Related publication: M.Madi, F. Ceyssens et al. “A Lippmann-based waveguide spectrometer with enhanced throughput and bandwidth for space & commercial applications. Accepted for publication in Optics Express.

Prinicple of Lippmann-based planar waveguide spectrometer.

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6. MEMS, sensors & nanotechnology

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Consequent to our continuous drive, MICAS’ MEMS research forms a cornerstone in the Leuven Nanocenter, a facility enabling growth of the nano-biosensor work in Leuven, augmenting multidisciplinary research through cooperation and cross-fertilisation with several other groups.

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A rigorous study has been performed on the sensitivity, non-linearity, offset and resonance frequency of piezoresistive MEMS pressure sensors (see Figure (a)). To this end, an automated pressure-temperature measurement setup was developed with a pressure accuracy of 0.01 %FS (0 to 6 bar abs) and a temperature accuracy of 0.1 °C (-40 to 120°C) (see Figure (b)). Wheatstone bridge measurements were linked with analytical models and non-linear finite element models in Comsol Multiphysics taking into account thermal effects (thin film stress, packaging stress, …). As an example, round diaphragms displayed a lower sensitivity and a higher nonlinearity compared to their square counterparts (see Figure (c)). Currently, the models are employed to explore new pressure sensor schemes with improved drift, linearity and temperature dependence.

Grim Keulemans• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Microfabrication, pressure sensing,

nonlinearity, finite element modeling

6.1 Nonlinearity and drift in MEMS pressure sensors

(a) Piezoresistive MEMS pressure sensor; (b) Measurement setup; (c) Typical sensor output

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In the last decades, ultrasound has found ever-expanding industrial and biomedical application such as non-destructive evaluation, ultrasonic actuation and communication, medical imaging, etc. at frequencies from tens of kHz to hundreds of MHz. The piezoelectric effect is the most promising technique to excite ultrasound, since it avoids high biasing voltage, complex fabrication process, and high cost.

We, at KU Leuven-MICAS, have provided all facilities to grow AlN and PZT, two high-end piezoelectric thin films. Researches have been carried out on developing, controlling, and formulating the mechanical and piezoelectric parameters of these materials. AlN due to its stability and bi-compatibility is a good candidate to be used in underwater ultrasound and bio-imaging application. A wide variety of piezoelectric micromachined ultrasound transducers (pMUT), such as low and high frequency, wide bandwidth, and low power array pMUTs have been designed and fabricated. Furthermore, macro-sized ultrasound transducers based on additive manufacturing of silicon-carbide (SiC) has been manufactured, to be utilized in underwater fully omnidirectional ultrasound communication.

Sina Sadeghpour• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Microelectromechanical systems,

piezoelectric materials, ultrasound transducers

6.2 Piezoelectric materials and piezoelectric ultrasound transducers

Photo of (a) a wide-bandwidth pMUT array and (b) the omnidirectional ultrasound transducer.

Related publication: Sadeghpour, S., Pobedinskas, P., Haenen, K., & Puers, R. (2017). “A Piezoelectric Micromachined Ultrasound Transducers (pMUT) Array, for Wide Bandwidth Underwater Communication Applications”. In MDPI Proceedings (Vol. 1, No. 4, p. 364).

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At present, the trend toward electronic implants is only starting, and considerable R&D effort is still required to increase functionality of these systems. A key aspects herein is the proper symbiosis between the implant and the body. Both biological, mechanical and chemical. More formally known as biocompatibility. A viable route is the use of naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today’s electronic world. With bulk monocrystalline silicon (100) as the preferred base material in almost all devices. However, one fundamental challenge therefore is the brittle and rigid nature of state-of-the-art CMOS.

Therefore the scope of this research is to investigate how CMOS-technology-enabled flexible and stretchable electronics can be developed. With MEMS-techniques as the main enabler. Offering the potential to build advanced implantable systems. With minimal negative tissue impact.

Currently a flexible and stretchable silicon platform has been developed with the aid of deep reactive ion etching. Rigid silicon islands are mechanically interconnected through micormachined silicon springs. The islands can contain advanced CMOS-based electronics and MEMS. Metal tracks on top of the springs distribute the electrical signals over the different islands. As such creating a distributed network. Fixation of this network onto biological tissue compatible with in vivo dynamic movements, is an additional challenge that is addressed in this research.

Bram Lips• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Microfabrication, sensor network,

mechanics

6.3 MEMS technology for flexible and stretchable silicon implants

Micro and macro view of a fully flexible and stretchable silicon substrate made with DRIE.

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LED walls have been gaining more interest in the last years. The ever increasing demands on resolution and power consumption come at a significant cost. The current state-of-the-art in LED walls use direct addressing for driving every LED separately. Increasing the resolution results in a huge fanout and requires a large amount of silicon driver ICs. Therefore, high resolution LED walls are very expensive.

To lower the cost of these LED walls, this project studies the implementation of active matrix (AM) driving for LED walls. The driving principle is already used in (AM)OLED displays. In contrast to AMOLED displays, LED walls use separate LEDs (components), which require much more current, instead of an OLED layer. These larger currents lead to a larger voltage drop on the supply lines. To lower the power consumption, the thin-film transistor (TFT) is driven in the linear regime. Hence the drop on the supply lines affects the current through the TFT, and thus the LED emission. In this work, a compensation principle is implemented for low-power AMLED walls.

Lynn Verschueren• Promotor Prof. W. Dehaene

wim.dehaene@kuleuven.be• Research topics Large area electronics, LED display design,

driving and calibration

6.4 Active matrix driving for LED walls

Microscope picture of AMLED backplane (backside). Inset bottom left: zoom-in on TFTs from frontside.

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This research proposes a novel packaging solution which integrates micro-machined 3D horn antennas and lenses with millimeter-wave and THz tranceivers. This packaging solution is shown to be a valid competitor to existing technologies like metallic split-block waveguides and low temperature cofired ceramics. Different fabrication methods based on two-photon lithography were developed to fabricated the 3D horn antennas and lenses. Measured prototypes show a 12 dB increase in the antenna gain when using the packaged solution. The fabrication processes are not limited to horn antennas or lenses alone and can be used to form a wide range of mm-sized components.

Alexander Standaert• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Dielectric waveguides, THz circuits

6.5 Micromachined horn antennas and lenses for high gain Thz tranceivers

Related publication: Standaert et al 2018 J. Micromech. Microeng. https://doi.org/10.1088/1361-6439/aaa74b.

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Technology scaling has advanced the RF-CMOS circuits in the mm-wave frequency range (30-300 GHz). This scaling has paved the way on one hand for high speed communication applications and on the other hand for sensing applications. At these high frequencies the free-space path loss becomes significant. To increases the reach of mm-wave transmitters and receivers, a PTFE dielectric fiber is used to guide the mm-wave signal at low loss.

These dielectric fibers allow for new sensing applications. The fiber can itself react to the environment and change the propagation of the mm-wave. At these frequencies part of the wave still propagates outside the fiber. A change at the outside of the fiber can be sensed by measuring the effect is has on the propagation of the mm-wave. On the other hand the fiber can be used to guide the mm-wave at low loss to and from a sample under test to perform a sensing operation. By placing the chips in a safe environment, mm-wave sensing in harsh environments is possible because PTFE fibers can be used at high temperatures, are not effected by the usual organic acids and solvents, and are insensitive to EMI.

To test these sensing applications a 120 GHz 28nm CMOS differential phase detector in combination with two dielectric fibers for differential sensing is proposed. By using one reference channel and one sensing channel, accurate environmental changes (temperature, humidity, ..) can be sensed.

Bart Philippe• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics RF front ends, mm-wave, dielectric fiber, sensing

6.6 CMOS circuits for dielectric fiber sensors

28nm CMOS, 120 GHz differential phase detector.

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7. Educational reseach& projects

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MICAS staff members believe that passion for engineering and science is something we need to pass on to our kids from a young age. That is why MICAS is leading projects that bring STEM to schools in such a way that youngsters can engage with engineering in the regular educational curriculum.

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To address the increasing need for competent STEM workers, a new approach in education is required, that reveals the links between the STEM disciplines (Science, Technology, Engineering and Mathematics). Such a new approach requires new learning materials. Research within the scope of the project STEM@school has identified requirements for integrated STEM learning materials as well as learning goals to be achieved by the pupils.

Based on these requirements and case study based research, a collaboration between secondary school teachers and university researchers resulted in an online support tool ‘CODEM for iSTEM’: Collaborative Online Development of Educational Materials for integrated STEM. Following this tool, teachers collaboratively gather STEM learning concepts that connect multiple STEM disciplines. Then, in an iterative process, they embed these concepts in a tempting challenge for the pupils. As validation, the tool CODEM for iSTEM was implemented in teacher training and showd to encourage a more critical and reflective approach towards curriculum development.

Jolien De Meester• Promotor Prof. W. Dehaene

wim.dehaene@kuleuven.be• Research topics STEM integration, secondary

school, method, learning materials, teachers

7.1 Developing STEM-integrating learning materials

Example page of CODEM for iSTEM.

Related publication: De Meester J., Langie G., De Cock M., Dehaene W., “Method for the Development of STEM-integrating Learning Materials.” ESERA 2017, Dublin, 2017.

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Integrated STEM education is inseparable from STEM professions. While this awareness is just gaining interest in secondary education, it is already a long-term incentive at university level within engineering. Projects in which students need to integrate and actively make connections between different courses, in order to build prototypes are initiated each semester. This idea is translated to a secondary school level and unrolled.

Although the university has a lot of experience with these projects, assessors are still struggling how to evaluate the process student go through while finishing the project. For secondary school teachers, this teaching approach is new, so they are also looking for an assessment method. In this research the needs of both groups are jointly addressed by creating an assessment which is suitable for both. Of course, some adaptations and personifications are necessary.

These assessment methods are unrolled in the previous mentioned groups. Questionnaires and interviews regarding the gained experience from students and teachers were carried out. It seems to be that the majority of the students asks for more transparency with regards to the evaluation criteria. Teachers confirm that this transparency is a good thing, because they see students adapting their behavior based on the criteria. Furthermore, teachers feel their assessment is more objective, because their holding to these criteria.

Leen Goovaerts• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Integrated STEM, secondary

education, university level, process evaluation

7.2 Process evaluation in integrated STEM

Example of a transfer question (left) and the corresponding concept question (right).

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Nowadays, STEM-education is gaining interest in Flanders’ secondary schools. Teachers develop projects in which they integrate Science, Technology, Engineering and Mathematics. The purpose of research for teaching approaches and development of ‘integrated STEM education’ is to make youngsters recognize the relevance of mathematical equations and scientific models for everyday problem solving in general, and for engineering in particular. Pupils contributing to these kind of integrated STEM-projects, gain more than theoretical knowledge. Pupils learn how to set up and perform research, how to follow a design cycle, what’s the relevance of their theoretical knowledge and so on. Thus they obtain 21st century skills and competences as defined by the EU.

One of these 21st century skills is transfer. Transfer is defined in literature as knowledge which can not only be accessed again in the context in which it was learned but also in new contexts. Of course, many gradations of transfer are possible. Near transfer is defined as transfer to another context with many similarities, whereas far transfer is a transfer to a context with only some leases to connect. In this research we examined the far transfer skills of pupils in secondary school. More precisely, we, Jolien De Meester and I, compared the transfer skills of pupils following the regular curriculum with pupils following the STEM@school curriculum. In this setting, we examined the transfer ability of the pupils concerning the slope, area under the curve and series and parallel circuits, by the use of teaching learning interviews.

Leen Goovaerts, Jolien De Meester• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Integrated STEM, secondary

education, transfer of concepts

7.3 Transfer of concepts in secondary education

Example of a transfer question (left) and the corresponding concept question (right).

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Integrated STEM education is an instructional approach in which students participate in engineering design and research and experience meaningful learning through integration and application of mathematics, technology and science. Integrated STEM education has the potential to improve both students’ achievement in and motivation for STEM domains. However, to optimally profit from its possible benefits, integrated STEM should be taught effectively. Therefore, it is necessary to investigate how teachers’ attitudes and school context are related to their classroom practices and how these practices affect students’ learning outcomes.

In this research, instruments were developed to measure both teachers’ attitudes towards and instructional practices in integrated STEM. Instead of using an overall measure for integrated STEM, these instruments examine teachers’ attitudes and practices on five specific dimensions: integration of STEM content, problem-centered learning, inquiry-based learning, design-based learning, and cooperative learning. That way, a more in-depth and nuanced insight into the relationship between teachers’ attitudes, their classroom practices and students’ learning outcomes can be provided.

Results of the research show that for each STEM dimension, teachers’ attitudes are positively linked with instructional practices Moreover, different aspects of school context influence instructional practices either directly or indirectly. Especially, management context (i.e., the support given by principals and school administrators) and social context (i.e., the collaboration between teachers from different STEM-disciplines) are important for the successful implementation of integrated STEM education.

Lieve Thibaut• Promotor Prof. W. Dehaene

wim.dehaene@kuleuven.be Prof. F. Depaepe• Research topics Integrated STEM education,

teachers’ attitudes, classroom practices

7.4 The role of teachers in the implementation of integrated STEM education

Overview of the relationship between teachers’ attitudes, school context and instructional practices

Related publication: Thibaut, L., Knipprath, H., Dehaene, W., & Depaepe, F. (2018). The influence of teachers’ attitudes and school context on instructional practices in integrated STEM education. Teaching and Teacher Education, 71, 190-205.

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The first part of this research is focused on designing learning and teaching materials for an integrated STEM-curriculum (Science, Technology, Engineering, Mathematics) for students aged 14 to 15 in Flemish secondary education in the STEM@school project. Students are challenged to design a museum security system using geometrical optics and to design and program a car driving autonomously through a green wave using 1D-kinematics.

The second part concerns with assessment of student performance in physics and mathematics. Four tests have been designed and are being administered to test for conceptual understanding of 1D-kinematics, representational flexibility, conceptual understanding of vectors and the link between physics and mathematics. The goal is to compare students in the STEM-curriculum and students in the regular curriculum.

Stijn Ceuppens• Promotor Prof. W. Dehaene

wim.dehaene@kuleuven.be Prof. M. De Cock• Research topics Educational research & projects

7.5 Learning of physics and mathematics concepts in an integrated STEM curriculum

Mathematical solution in GeoGebra and 3D-model for the optics-based museum security system.

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8. Awards and prizes in 2017

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Awards and Prizes in 2017Prof. Marian Verhelst wins the prize of the Royal Academy of Science and Arts for promising researchers under 40. This prestigious prize is annually awarded to one upcoming researcher in the field of applied sciences. [see photo 1]

Nicolas Butzen (promotor: Prof. Michiel Steyaert) received at ISSCC17 the ISSCC Distinguished Technical Paper Award 2016 for his paper “A 94.6%-Efficiency Fully Integrated Switched-Capacitor DC-DC Converter in Baseline 40nm CMOS Using Scalable Parasitic Charge Redistribution”. [see photo 2]

The STEM@School project (promotor: Prof. W. Dehaene) won the Best Research & Practice Project Award at the international conference EAPRIL 2017. This prize is awarded annually to practitioner researchers who made the largest contribution to educational practice. [photo 3a & 3b]

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Michiel Steyaert was listed “in the top 50 tech pioneers” list of De Tijd. multimedia.tijd.be/techpioniers/ This list portrays 50 Belgians who are working towards a future you cannot even imagine yet.

Bert Moons (promotor: Prof. Marian Verhelst) and Nicolas Butzen (promotor: Prof. Michiel Steyaert) were awarded the 2nd and 3rd place in the 2017 IEEE SSCS Benelux Chapter Chip Design Contest for their work embedded processors for deep neural networks, resp. fully-integrated switched-capacitor DC-DC Convertion. [see photo 4]

Bert Moons (promotor: Prof. Marian Verhelst) received an IEEE SSCS Travel Grant Award (STGA) to attend ISSCC2017. [see photo 5]

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Marco Vigilante (promotor: Prof. Patrick Reynaert) wins the IEEE Solid-State Circuits Society Predoctoral Achievement Award 2016-2017. [photo 6]

Nektar Xama (promotor: Prof. Georges Gielen) won the Best Paper award of the 22nd IEEE European Test Symposium with the paper entitled “Automatic Testing of Analog ICs for Latent Defects using Topology Modification”.

Marco Vigilante (promotor: Prof. Patrick Reynaert) wins the 2017 IEEE RFIC Symposium Best Student Paper Award–3rd Place. [photo 7] Hans Reyserhove (promotor: Prof. Wim Dehaene), Nicolas Butzen (promotor: Prof. Michiel Steyaert), Bert Moons (promotor: Prof. Marian Verhelst) and Komail Badami (promotor: Prof. Marian Verhelst) win the IEEE Solid-State Circuits Society Predoctoral Achievement Award 2017-2018.

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Nicolas Butzen (promotor: Prof. Michiel Steyaert) will receive at ISSCC18 the Jan Van Vessem Award for Outstanding European Paper 2017, for the paper entitled “A 1.1W/mm2-Power-Density 82%-Efficiency Fully Integrated 3:1 Switched-Capacitor DC-DC Converter in Baseline 28nm CMOS Using Stage Outphasing and Multiphase Soft-Charging.

Tim Thielemans and Ely De Pelecijn (promotor: Prof. Michiel Steyaert) won the 2nd and 3rd prize in the IEEE R8 student paper contest 2017. [photo 8]

Bert Moons (promotor: Prof. Marian Verhelst) won with his master student Matthijs Van Keirsbilck the Imec master thesis prize for “Design, implementation, and analysis of a deep convolutional-recurrent neural network for speech recognition through audiovisual sensor fusion”.

Dries Kil and Luigi Brancato (promotor: Prof. Robert Puers) won the best poster award at the ‘28th Micromechanics and Microsystems Europe Workshop’ in Uppsala, Zweden, with “Dextran as a fast resorbable and mechanically stiff coating for flexible neural probes”.

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9. Infrastructure

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MICAS continually invests substantially in its measurement infrastructure. In our new measurement lab, we are able to measure everything from DC to THz frequencies.

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At MICAS a Local Area Network (LAN) is provided with 1 Gbit/s performance to all available servers and workstations. A central file server with 2 TB hard disk cabinets and RAID 10 architecture hosts all the design and EDA software as well as the user accounts. The total storage capacity at ESAT exceeds 400 TB.

Performant Dual Xeon 8/10 core CPU numbercrunchers with up to 256GB RAM provide the processing power to tackle even the most demanding simulation runs.

EDA tools from vendors such as Cadence, Mentor Graphics, Synopsys, Keysight, Ansys, a.o. are used for simulation, layout and verification. Other tools such as Comsol Multiphysics and Coventorware are used to support the design of MEMS. Linux CentOS 6/7 (fully compatible with the popular RedHat OS) is used as our preferred operating system.

9.1 Computer and software

infrastructure

W. DehaeneB. Geeraerts

View of the 19” racks in our computerroom, stacked with different servers.

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(top) High speed data across plastic waveguide demo setup.(bottom left) IC-Lab HF. (bottom right) Network Analyzer setup.

IC-Lab HF contains wideband measurement equipment such as signal analyzers, arbitrary waveform generators, oscilloscopes and vector network analyzers. An extensive list of high performance instruments is available to ensure the best possible measurement accuracy. Also it provides means to test the latest communication standards such as 5G, LTE Advanced, WiMAX, and WLAN.

Recent activities include the measurement of transmitters/receivers, oscillators, AD/DA converters, THz antennas, high speed optical receivers and high speed data communication across plastic waveguides.

Instrumentation facilities include:• Vector network analysis up to 325 GHz• Spectrum analysis up to 1.1 THz• Signal generation up to 1.1 THz• Power measurements up to 2 THz• Probe Station and mmW-probes up to 1.1 GHz• Parbert System: 16 bit data Generator/ 12 bit Analyzer up to 27 Gb/s• Arbitrary Waveform Generators up to 50 GS/s• Real-Time Oscilloscopes up to 60 GHz• Phase Noise measurements up to 18 GHz• Various Horn Antennas for wireless chip measurements and antenna characterization• E-Band Communication Test Equipment• Various high-speed optical transmitters

9.2 IC-Lab HF: broadband, optical, mm-wave and THz measurement lab

M. SteyaertP. ReynaertF. Daenen

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(left) IC-Lab LF. (right) Low Frequency measurement setup.

IC-Lab LF contains specialized equipment in the range from DC to several GHz. The main focus of this lab is on low noise, high resolution signal generation and power source analysis.

Recent activities include power analysis & EMI performance of integrated power converters and power control circuits.

Instrumentation facilities include:• Accurate inductor measurement system• AC Source Analyzer up to 750VA• Power Analyzers up to 600VA• Precision Source Measure Units• Ultra low distortion signal sources < 0.001% THD• High Magnification Digital Microscope up to 2500x• Laser Cutter for chip repair• High performance thermal imaging camera with 3um/pixel resolution• Thermostream for fast precision temperature testing

9.3 IC-Lab LF: the Low Frequency

measurement lab

M. Steyaert, P. Reynaert,F. Daenen, R. Vanlaer

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Micas has a well-equipped clean room facility for R&D and small-scale production of microsystems, MEMS and lab-on-chip devices. Through our recent investments in equipment for i.a. ALD and advanced e-beam direct writing, prototyping of nanoscale devices is now also possible.

Since 2015 the facility has been updated significantly, and is relocated in the new KULeuven Nanocenter.

Next to our own research in medical devices, sensors and actuators the cleanroom is also used by other research groups interested in developing devices or setting up experiments at the micro- and nanometer scale.

Third-party users include several local and international companies and research centers, and research groups from KULeuven’s physics, bio-engineering and chemistry departments. To limit costs and increase flexibility, third party users can be allowed to operate the equipment themselves after training.

The Sentech Atomic Layer Deposition System

B. Puers F. CeyssensM. De CoomanT. Brockhans

M. Kraft9.4 MICAS in the Leuven

Nanocenter (LeNa)

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The lithographic equipment available allows for creating patterns on silicon wafers and other flat substrates with high resolution. Notable available tools include:

• Raith e-beam system for direct writing of patterns with a resolution down to 10 nm.• LW405 laser direct-write equipment for mask making with 700 nm resolution• Nanoscribe GT 2-photon lithography system for direct writing of 3D structures with a voxel size of 200 x 200 x 600 nm• Contact lithography systems (EVG, Karl Suss) for wafer-level patterning with a 1 micrometer resolution• EVG nanoimprint lithography for wafer-level patterning down to 50 nm resolution.• EVG Spray coater for enabling lithographic processing on uneven substrates

There is also a range of inspection equipment available, including a SEM, a Dektak profile meter, a Femtotools micro force probe and diverse tools for optical characterization by microscopy, reflectometry and ellipsometry. The cleanroom is equipped with all infrastructural requirements to facilitate research under clean, controlled and safe conditions, and is compliant with ISO class 6.

9.5 Lithography and MEMS

fabrication

B. Puers F. CeyssensM. De CoomanM. Kraft

The Micas lithography room.

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The MICAS Technology Lab provides in-house facilities to bond, flip-chip and package chips and sensors.

Several Aluminum and Gold bonders are available to package chips in a package or directly on a PCB. The latest bonder is a thermosonic high-speed, ball-and-stitch gold wire bonder, supporting complex wire bonding, ball/stud bumping and complex IC attach without leaving a tail.

Flip Chip packaging is possible by bumping Au studs onto a chip, combined with an accurate flip-chip bonding device to place the pre-bumped sample directly on a PCB. Compared to traditional bonding this process allows very low-impedance connections between the chip and the measurement board which results in increased performance.

9.6 Technology Lab: Chip Bonding Facilities

P. Reynaert, M. Steyaert, N. Gaethofs, R. Vanlaer,

F. Daenen

Thermosonic high-speed, ball-and-stitch wire bonder

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The MICAS Technology Lab provides in-house facilities to perform high precision sample preparation.

With an accurate dicing saw, individual chips can be separated from each other on the wafer.The dicing process is accomplished by mechanically sawing the scribe lines on the wafer.A second dicing machine is available and optimized for cutting glass material with high precision.

A specialized cnc controlled grinding machine is able to perform decapsulation, silicon thinning, polishing and cleaning of integrated circuits. This machine is often used for sample preparation prior to backside circuit editing with the focused ion beam system. Typically the bulk silicon at the back of the die is removed until a remaining thickness of around 50 to 100um is left.

9.7 Technology Lab: Dicing and

Grinding Facilities

M. Steyaert, P. Reynaert, N. Gaethofs, R. Vanlaer,

F. Daenen

Dicing and Grinding machine

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The MICAS Technology Lab provides services for state of the art circuit modification and chip repair.

An Nd-YAG laser is available for top metal silicon surgery. The laser light is focused through a microscope in order to selectively remove certain parts from an IC. The laser emits green light (532nm) which can be used for cutting metal lines and trimming resistors. An attenuator and variable aperture lens are used to control the energy level of the laser for precise operation.

For advanced chip modification, a specialized Focused Ion Beam System (FIB) is available. Several materials can be removed and deposited with nanometer accuracy so that circuits can be modified without the need for re-processing. A unique feature of the system is the increased working distance so that electrical components around the chip won’t hinder the repair operation. Therefore the FIB is able to make modifications not only on single dies or on chip packages but even on dies directly mounted onto a PCB.

9.8 Technology Lab: Chip Repair

Facilities

M. Steyaert, P. Reynaert, F. Daenen

Dual Beam System optimized for chip repair. FIB was used to fine tune a microstrip line.

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MICAS has a long-standing tradition of research valorization through research projects with the industry and through spin-off creation. Our research pipeline, consisting of long-term fundamental research, strategic basic research and applied industrial research, is targeted on creating maximum leverage and economic impact for the research.Our model of research valorization towards the industry is based on a continuous interaction with current and potential partners and on a profound knowledge of their research needs. Finding a good match between those needs and what MICAS can offer leads to the definition of a research collaboration. That collaboration can take the form of a purely bilateral contract, a participation in a project with co-funding by regional or European agencies, or any other form through which MICAS research results can enable significant innovation in the product pipeline of the partner.In 2017, 32 different research projects (excluding PhD and postdoc scholarships) have been running at MICAS. Almost exactly 1/3 of the total funding budget was in long-term fundamental research projects, 1/3 in strategic basic research projects and another 1/3 in applied industrial research projects.In 2017, David Maes joined the MICAS team to give a boost to our research valorization activities. David operates as valorization manager, and is responsible for setting up collaboration projects with the industry, forming the bridge between our research and the industrial needs. He also stimulates and guides all other forms of research valorization at MICAS.

9.9 Valorization

management

D. Maes

Researchers of NXP Semiconductors, assisted by MICAS research assistant Maxime De Wit, successfully perform a demo of a 120 GHz polymer microwave fiber link in the MICAS IC-Lab, interfacing a dedicated MICAS chip with a FPGA board provided by NXP.

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D. VermettenC. MertensA-M. Ruijmen

Micas wouldn’t be running as smoothly as it does, if it didn’t have the excellent support of the Micas secretariat by Danielle Vermetten (administrative support) and the Financial Services by Chris Mertens and Anne-Marie Ruijmen. They all have been with Micas for many years and definitely cannot be missed.

9.10 Administrative

staff ESAT-MICAS

Annemarie: finances Danielle: secretariat Chris: finances

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10. Doctoral theses in 2017

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Raf Appeltans; Embedded STT-MRAM Cell Design in and beyond 10 nm finFET Nodes; Promotor Wim Dehaene; 2017. [photo 1]

Chao-Yang Chen; Understanding and Improving Reliability of Oxide-based Resistive RAM for Embedded Application and Storage Class Memory; Promotor Guido Groeseneken; 2017.

Anthony Coyette; Automatic Defect-Oriented Test Generation for Analog and Mixed-Signal Integrated Circuits; Promotor Georges Gielen; 2017. [photo 2]

Jan Doise; Implementation of Block Copolymer Based Directed Self-assembly for Advanced Lithography; Promotor Guido Groeseneken; 2017.

Bram Faes; Design of highly controllable and low jitter CMOS circuits for wide-band and radiation applications.; Promotor Paul Leroux; 2017. [photo 3]

Pavlo Fesenko; Single Crystalline Organic Thin Films by Stencil Lithography: Growth and Characterization; Promotor Paul Heremans; 2017.

Yanxiang Huang; Cross-Layer Optimization for Power-Efficient and Robust Digital Circuits and Systems; Promotor Wim Dehaene; 2017. [photo 4]

Paramartha Indirayanti; Design Techniques for Power Efficient Millimeter Wave Transmitters in Nanoscale CMOS; Promotor Patrick Reynaert, Wim Dehaene; 2017. [photo 5]

Ioannis Karageorgos; Impact of Interconnect Advanced Patterning Options on Circuit Design; Promotor Wim Dehaene; 2017. [photo 6]

1

2 3 4 5

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Iman Khajenasiri; Design and Implementation of UWB Transceivers for Internet of Things Applications; Promotor Georges Gielen; 2017. [photo 7]

Shailesh Kulkarni; Design Techniques for CMOS Broadband Circuits Towards 5G Wireless Communication; Promotor Patrick Reynaert; 2017. [photo 8]

Ha Le Thai; High-Speed and Low-Noise Readout Circuitry for CMOS Image Sensors; Promotor Georges Gielen; 2017. [photo 9]

Weiming Qiu; Interface Layers for Efficient Organic and Perovskite Solar Cells; Promotor Ludo Froyen,Paul Heremans; 2017.

Mai Osama Mohamed Ibrahim Sallam; Plasmonic Waveguides and Nano-Antennas for Optical Communications; Promotor Guy Vandenbosch; 2017.

Athanasios Sarafianos; Fully-Integrated Wide Input Range and Two-Quadrant Switched-Capacitor DC-DC Converters; Promotor Michiel Steyaert; 2017. [photo 10]

Wouter Steyaert; THz Electronics Design in Nanometer CMOS; Promotor Patrick Reynaert; 2017. [photo 11]

Devin Verreck; Quantum Mechanical Transport Towards the Optimization of Heterostructure Tunnel Field-effect Transistors; Promotor Guido Groeseneken; 2017.

Marco Vigilante; mm-Wave Building Blocks for Future 5G Transceivers in Deep-scaled CMOS; Promotor Patrick Reynaert; 2017. [photo 12]

6 7 8

9 11 10 12

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11. Spin-offs

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The state-of-the-art research at MICAS has resulted in 6 successful spinoff companies over the last 15 years.

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11.1 AnsemAnSem was founded in 1998 as a spin-off from the MICAS research group of the KU Leuven. AnSem is a fabless analog ASIC design service company, designing and delivering state-of-the-art analog, RF and mixed-signal integrated circuits to customers worldwide. It takes control over the complete ASIC development and supply flow, being a true one-stop-shop for its customers. AnSem is ISO 9001 certified, and is predominantly active in the healthcare, communications, industrial and aerospace & defense markets.

More information: www.ansem.com

11.2 ICsenseICsense was founded in 2004 as a spin-off from the MICAS group of KU Leuven and is ISO9001 / ISO13485 certified. It is a one-stop-shop IC design and ASIC supplier active in the automotive, aerospace, medical, industrial and consumer markets. ICsense’s core expertise is in analog, mixed-signal, sensor and MEMS interfacing, high-voltage and radiation-hard IC design. With a team of close to 50 mixed-signal designers on site, ICsense has the largest fab-independent IC design group in Europe.

More information: www.icsense.com

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11.3 ZensoZenso NV was founded in 2007 as a MICAS spin-off, designing and producing electronic circuits and systems. Zenso NV is active in the medical sector, as well as in the industrial, automotive and consumer sectors. Zenso is ISO9001 and ISO13485 for medical design certified. The core services it offers are centered around: feasibility studies, electronic system and PCB design, software development, system integration, prototyping & series production, test & validation, CE testing (safety, immunity, emission, radio) and technical writing.

More information: www.zenso.be

11.4 MinDCetMinDCet was founded in 2011, as a spin-off from the MICAS research group. MinDCet is an ISO9001 certified, fabless, mixed-signal IC design company, developing Power Management ICs. MinDCet develops highly/fully integrated and discrete DC-DC converters, motor drivers, high-speed GaN and laser drivers, control systems, class-D amplifiers, power and battery management. Currently, MinDCet is active in the following markets: automotive, industrial, aerospace & space, biomedical, high-reliability & harsh environments.

More information: www.mindcet.com

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11.6 HAMMER-IMSHammer-IMS is a high-tech company in the field of industrial sensing. It is a spin-off company of research laboratory ESAT - MICAS of KU Leuven University. The company, founded in 2016, is based in Hasselt, Belgium. Hammer-IMS supplies contactless measurement systems for measuring thickness, weight and anomalies of semi-finished products in production lines. Hammer-IMS applies its disruptive M-Ray technology in its products and solutions. This technology combines millimeter waves (=high-frequency electromagnetic waves) with innovative algorithms to a powerful alternative for today’s nuclear and radioactive measuring equipment.

More information: www.hammer-ims.com

11.5 MAGICS InstrumentsMAGICS Instruments is a spin-off company of MICAS since 2015, specializing in the design of radiation-hardened, integrated circuits. They deliver customized state-of-the-art, radiation-tolerant electronics to their customers and they provide radiation qualification services on ASICs or commercial-off-the-shelf components. As such, they identify potential risks and improve reliability. The MAGICS Instruments technology is qualified under extreme radiation conditions. MAGICS Instruments is currently active in the following markets: space industry and high-energy particle physics.

More information: www.magicsinc.com

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11.7 TuskTusk IC was founded in 2018 as a spin-off from the MICAS research group. Tusk IC offers extensive research and industry experience in the field of millimeter wave IC design in silicon technologies. They provide state-of-the-art IC design services and high-frequency measurements for millimeter wave circuits in CMOS and SiGe BiCMOS, from 10GHz to 600GHz and beyond.From 5G to car radar for autonomous vehicles, wireless VR to contactless sensing: the millimeter wave spectrum will enable a wide range of revolutionary applications. Tusk IC is where these millimeter waves meet silicon.

More information: www.tusk-ic.com

12. Emeriti

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Willy Sansen is the founder of MICAS, established in 1984. He has been retired as an emeritus professor since October 2008. His activities are the following. Firstly Willy Sansen is active within the KU Leuven itself as a member of the reflection group of the emeriti forum and as a chair of doctoral committees. Secondly, Willy Sansen is probably best known for his courses and consulting. In 2017 he has been teaching analog design, as a follow up of his book “Analog Design Essentials” all over the world, in companies and in universities. The content of his courses is continuously updated, after each major conference. In addition Willy Sansen is a member of several IEEE conferences and meetings. As a past president of the IEEE Solid-State Circuits Society, he is a member of its ADCOM. He has played an instrumental role in the inclusion of the ESSCIRC/ESSDERC conferences in the IEEE and is still Chairman of the their Technical Program Steering Board. Last but not least Willy Sansen is a member of Technical Advisory Boards of several companies and of Boards of Directors.

Willy Sansen

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13. Bibliography

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138

13.1 Articles in internationally reviewed scientific journals

Agarwal Kumar, T.; Soree, B.; Radu, I.; Raghavan, P.; Iannaccone, G.; Fiori, G.; Heyns, M.; Dehaene, W.; Material-device-circuit co-optimization of 2D material based FETs for ultra-scaled technology nodes; Scientific Reports; vol. 7; pp. 5016; 2017.

Agarwal, T.; Sorée, B.; Radu, I.; Raghavan, P.; Iannaccone, G.; Fiori, G.; Dehaene, W.; Heyns, M.; Material-device-circuit co-optimization of 2D material based FETs for ultra-scaled technology nodes; Scientific Reports; vol. 7; pp. 1-7; 2017.

Appeltans, R.; Raghavan, P.; Kar, G.; Furnemont, A.; Van der Perre, L.; Dehaene, W.; A smaller, faster and more energy-efficient complementary STT-MRAM cell uses three transistors and a ground grid: more is actually less; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; vol. 25; issue 4; pp. 1204-1214; 2017.

Brancato, L.; Weydts, T.; Oosterlinck, W.; Herijgers, P.; Puers, B.; Packaging of implantable accelerometers to monitor epicardial and endocardial wall motion; Biomedical Microdevices; vol. 19; art.nr. 52; 2017.

Butzen, N.; Steyaert, M.; Design of Soft-Charging Switched-Capacitor DC–DC Converters Using Stage Outphasing and Multiphase Soft-Charging; IEEE Journal of Solid-State Circuits; vol. 52; issue 12; pp. 3132-3141; 2017.

Butzen, N.; Steyaert, M.; MIMO Switched-Capacitor DC–DC Converters Using Only Parasitic Capacitances Through Scalable Parasitic Charge Redistribution; IEEE Journal of Solid-State Circuits; vol. 52; issue 7; pp. 1814-1824; 2017.

Catthoor, F.; Groeseneken, G.; Will chips of the future learn how to feel pain and cure themselves?; IEEE Design and Test of Computers; vol. 34; issue 5; pp. 80-87; 2017.

Ceyssens, F.; Deprez, M.; Turner, N.; Kil, D.; van Kuyck, K.; Welkenhuysen, M.; Nuttin, B.; Badylak, S.; Puers, B.; Extracellular matrix proteins as temporary coating for thin-film neural implants; Journal of Neural Engineering; vol. 14; art.nr. 014001; 2017.

De Clercq, N.; Theunis, R.; Reynaert, P.; Leroux, P.; Dehaene, W.; High-speed Single Cable Synchronization System for Data-converters; Analog Integrated Circuits and Signal Processing; vol. 90; issue 2; pp. 283-290; 2017.

de Jamblinne de Meux, A.; Pourtois, G.; Genoe, J.; Heremans, P.; Effects of hole self-trapping by polarons on transport and negative bias illumination stress in amorphous-IGZO; Journal of Applied Physics; vol. 123; issue 16; art.nr. 161513; pp. 161513-161513; 2017.

de Jamblinne de Meux, A.; Pourtois, G.; Genoe, J.; Heremans, P.; Origin of the apparent delocalization of the conduction band in high mobility amorphous semiconductors; Journal of Physics - Condensed Matter; vol. 29; issue 25; art.nr. 10.1088/1361-648X/aa608c; pp. 255702; 2017.

de Jamblinne de Meux, A.; Bhoolokam, A.; Pourtois, G.; Genoe, J.; Heremans, P.; Oxygen vacancies effects in a-IGZO: Formation mechanisms, hysteresis, and negative bias stress effects; Physica Status Solidi A, Applications and Materials Research; vol. 214; issue 6; art.nr. 1600889; 2017.

de la Hucha Arce, F.; Moonen, M.; Verhelst, M.; Bertrand, A.; Adaptive Quantization for Multichannel Wiener Filter-Based Speech Enhancement in Wireless Acoustic Sensor Networks; Wireless Communications & Mobile Computing; vol. 2017; art.nr. 3173196; pp. 1-15; 2017.

De Roose, F.; Myny, K.; Ameys, M.; van der Steen, J.; Maas, J.; de Riet, J.; Genoe, J.; Dehaene, W.; A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil; IEEE Journal of Solid-State Circuits; vol. 52; issue 11; pp. 3095-3103; 2017.

Decrop, D.; Pardon, G.; Brancato, L.; Kil, D.; Shafagh, R.; Kokalj, T.; Haraldsson, T.; Puers, B.; van der Wijngaart, W.; Lammertyn, J.; Single-step imprinting of femtoliter microwell arrays allows digital bioassays with attomolar limit of detection; ACS Applied Materials and Interfaces; art.nr. acsami.6b15415; 2017.

Dias Baumgratz, F.; Li, H.; Tavernier, F.; Bampi, S.; Saavedra, C.; A 0.4-3.3 GHz Low-Noise Variable Gain Amplifier with 35 dB tuning range, 4.9 dB NF, and 40 dBm IIP2; Analog Integrated Circuits and Signal Processing; vol. 94; issue 1; pp. 9-17; 2017.

Faes, B.; Reynaert, P.; Leroux, P.; Highly Tunable Triangular Wave UWB Baseband Pulse Generator with Amplitude Stabilization in 40 nm CMOS; IEEE Transactions on Circuits and Systems 2, Express Briefs; vol. 64; issue 5; pp. 505-509; 2017.

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Fesenko, P.; Flauraud, V.; Xie, S.; Kang, E.; Uemura, T.; Brugger, J.; Genoe, J.; Heremans, P.; Rolin, C.; Growth Of Organic Semiconductor Thin Films with Multi-Micron Domain Size and Fabrication of Organic Transistors Using a Stencil Nanosieve; ACS Applied Materials and Interfaces; vol. 9; issue 28; art.nr. 10.1021/acsami.7b06584; pp. 23314-23318; 2017.

Florent, K.; Lavizzari, S.; Di Piazza, L.; Popovici, M.; Groeseneken, G.; Van Houdt, J.; Reliability study of ferroelectric Al:HfO2 thin films for DRAM and NAND applications; IEEE Transactions on Electron Devices; vol. 64; issue 10; pp. 4091-4098; 2017.

Florent, K.; Lavizzari, S.; Popovici, M.; Di Piazza, L.; Celano, U.; Groeseneken, G.; Van Houdt, J.; Understanding ferroelectric Al:HfO2 thin films with Si-based electrodes for 3D applications; Journal of Applied Physics; vol. 121; issue 20; pp. 204103; 2017.

Gao, R.; Ji, Z.; Manut, A.; Zhang, J.; Franco, J.; Hatta, S.; Zhang, W.; Kaczer, B.; Linten, D.; Groeseneken, G.; NBTI-generated defects in nanoscaled devices: fast characterization methodology and modeling; IEEE Transactions on Electron Devices; vol. 64; issue 10; pp. 4011; 2017.

Gao, R.; Manut, A.; Ji, Z.; Ma, J.; Duan, M.; Zhang, J.; Franco, J.; Hatta, S.; Zhang, W.; Kaczer, B.; Vigar, D.; Linten, D.; Groeseneken, G.; Reliable time exponents for long term prediction of negative bias temperature instability by extrapolation; IEEE Transactions on Electron Devices; vol. 64; issue 4; pp. 1467-1473; 2017.

Gaur, A.; Balaji, Y.; Lin, D.; Adelmann, C.; Van Houdt, J.; Heyns, M.; Mocuta, D.; Radu, I.; Demonstration of 2e12 cm(-2) eV(-1) 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5 nm EOT; Microelectronic Engineering; vol. 178; pp. 145-149; 2017.

Hu, J.; Stoffels, S.; Zhao, M.; Tallarico, A.; Rossetto, I.; Meneghini, M.; Kang, X.; Bakeroot, B.; Kaczer, B.; Decoutere, S.; Groeseneken, G.; Time-dependent breakdown mechanisms and reliability improvement in edge terminated AlGaN/GaN Schottky diodes under HTRB tests; IEEE Electron Device Letters; vol. 38; issue 3; pp. 371-374; 2017.

Janneck, R.; Pilet, N.; Bommanaboyena, S.; Watts, B.; Heremans, P.; Genoe, J.; Rolin, C.; Highly Crystalline C8-BTBT Thin-Film Transistors by Lateral Homo-Epitaxial Growth on Printed Templates; Advanced Materials; vol. 29; issue 44; art.nr. 1703864; 2017.

Kadashchuk, A.; Tong, F.; Janneck, R.; Fishchuk, I.; Mityashin, A.; Pavlica, E.; Koehler, A.; Heremans, P.; Rolin, C.; Bratina, G.; Genoe, J.; Role of transport band edge variation on delocalized charge transport in high-mobility crystalline organic semiconductors; Physical Review B; vol. 96; issue 12; art.nr. 125202; 2017.

Keulemans, G.; Ceyssens, F.; Puers, R.; An ionic liquid based strain sensor for large displacement measurement; Biomedical Microdevices; vol. 19; issue 1; art.nr. 10.1007/s10544-016-0141-4; pp. 1-9; 2017.

Kocaay, D.; Roussel, P.; Croes, K.; Ciofi, I.; Saad, Y.; De Wolf, I.; LER and spacing variability on BEOL TDDB using E-field mapping: Impact of field acceleration; Microelectronics Reliability; vol. 76-77; pp. 131-135; 2017.

Kumar Das, U.; Garcia Bardon, M.; Jang, D.; Eneman, G.; Schuddinck, P.; Yakimets, D.; Raghavan, P.; Groeseneken, G.; Limitations on lateral nanowire scaling beyond 7nm node; IEEE Electron Device Letters; vol. 38; issue 1; pp. 9-11; 2017.

Le-Thai, H.; Chapinal, G.; Geurts, T.; Gielen, G.; A 0.18-μm CMOS Image Sensor With PhaseDelay-Counting and Oversampling Dual-Slope Integrating Column ADCs Achieving 1e− rms Noise at 3.8-μs Conversion Time; IEEE Journal of Solid-State Circuits; vol. 53; issue 2; pp. 515-526; 2017.

Li, X.; Van Hove, M.; Zhao, M.; Geens, K.; Lempinen, V.; Sormunen, J.; Groeseneken, G.; Decoutere, S.; 200 V enhancement-mode p-GaN HEMTs fabricated on 200 mm GaN-on-SOI with trench isolation for monolithic integration; IEEE Electron Device Letters; vol. 38; issue 7; pp. 918-921; 2017.

Li, Y.; Chen, C.; Willems, K.; Kerman, S.; Lagae, L.; Groeseneken, G.; Stakenborg, T.; Van Dorpe, P.; Probing local potentials inside metallic nanopores with SERS and bipolar electrochemistry; Advanced Optical Materials; vol. 5; issue 15; pp. 1600907; 2017.

Lopez, C.; Putzeys, J.; Raducanu, B.; Ballini, M.; Wang, S.; Andrei, A.; Rochus, V.; Vandebriel, R.; Severi, S.; Van Hoof, C.; Musa, S.; Van Helleputte, N.; Yazicioglu, R.; Mitra, S.; A Neural Probe With Up to 966 Electrodes and Up to 384 Configurable Channels in 0.13 mu m SOI CMOS; IEEE Transactions on Biomedical Circuits and Systems; vol. 11; issue 3; pp. 510-522; 2017.

Lyu, Y.; Ramkaj, A.; Tavernier, F.; High-gain and power-efficient dynamic amplifier for pipelined SAR ADCs; Electronics Letters; vol. 53; issue 23; pp. 1510-1511; 2017.

Mercuri, M.; Liu, Y.; Lorato, I.; Torfs, T.; Bourdoux, A.; Van Hoof, C.; Frequency-tracking CW Doppler radar solving small-angle approximation and null point issues in non-contact vital signs monitoring; IEEE Transactions on Biomedical Circuits and Systems; vol. 11; issue 3; pp. 671-680; 2017.

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Miclotte, A.; Grommen, B.; Lauwereins, S.; Cadenas de Llano Perula, M.; Alqerban, A.; Verdonck, A.; Fieuws, S.; Jacobs, R.; Willems, G.; The effect of headgear on upper third molars: a retrospective longitudinal study; European Journal of Orthodontics; vol. 39; issue 4; pp. 426-432; 2017.

Mohan, R.; Zaliasl, S.; Gielen, G.; Van Hoof, C.; Yazicioglu, R.; Van Helleputte, N.; A 0.6-V, 0.015-mm2, time-based ECG readout for ambulatory applications in 40-nm CMOS; IEEE Journal of Solid-State Circuits; vol. 298; issue 308; pp. 52-1; 2017.

Moons, B.; Verhelst, M.; An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS; IEEE Journal of Solid-State Circuits; vol. 52; issue 4; pp. 903-914; 2017.

Murillo Mange, Y.; Van den Bergh, B.; Beysens, J.; Bertrand, A.; Dehaene, W.; Patrinos, P.; Tuytelaars, T.; Sabariego, R.; Verhelst, M.; Wambacq, P.; Pollin, S.; Multidisciplinary Learning through Implementation of the DVB-S2 Standard; IEEE Communications Magazine; vol. 55; issue 5; pp. 124-130; 2017.

Nag, M.; De Roose, F.; Myny, K.; Steudel, S.; Genoe, J.; Groeseneken, G.; Heremans, P.; Characteristics improvement of top-gate self-aligned amorphous indium gallium zinc oxide thin-film transistors using a dual-gate control; Journal of the Society for Information Display; vol. 25; issue 6; pp. 349-355; 2017.

Pamula, V.; Valero-Sarmiento, J.; Yan, L.; Bozkurt, A.; Van Hoof, C.; Van Helleputte, N.; Firat Yazicioglu, R.; Verhelst, M.; A 172 $\ mu$W Compressively Sampled Photoplethysmographic (PPG) readout ASIC with Heart Rate Estimation Directly from Compressively Sampled Data; IEEE Transactions on Biomedical Circuits and Systems; vol. 11; issue 3; pp. 487-496; 2017.

Peña Ramos, J.; Verhelst, M.; Split-Delta Background Calibration for SAR ADCs; IEEE Transactions on Circuits and Systems 2, Express Briefs; vol. 64; issue 2; pp. 221-225; 2017.

Politou, M.; Wu, X.; Asselberghs, I.; Contino, A.; Soree, B.; Radu, I.; Huyghebaert, C.; Tokei, Z.; De Gendt, S.; Heyns, M.; Evaluation of multilayer graphene for advanced interconnects; Microelectronic Engineering; vol. 167; pp. 1-5; 2017.

Prinzie, J.; Christiansen, J.; Moreira, P.; Steyaert, M.; Leroux, P.; Comparison of a 65 nm CMOS Ring- and LC-oscillator Based PLL in terms of TID and SEU sensitivity; IEEE Transactions on Nuclear Science; vol. 64; issue 1; art.nr. 10.1109/TNS.2016.2616919; pp. 245-252; 2017.

Pulinthanathu Sree, S.; Dendooven, J.; Geerts, L.; Ramachandran, R.; Javon, E.; Ceyssens, F.; Breynaert, E.; Kirschhock, C.; Puers, B.; Altantzis, T.; Van Tendeloo, G.; Bals, S.; Detavernier, C.; Martens, J.; 3D porous nanostructured platinum prepared using atomic layer deposition; Journal of Materials Chemistry A; vol. 5; issue 36; pp. 19007-19016; 2017.

Qiu, W.; Bastos, J.; Dasgupta, S.; Merckx, T.; Cardinaletti, I.; Jenart, M.; Nielsen, C.; Gehlhaar, R.; Poortmans, J.; Heremans, P.; McCulloch, I.; Cheyns, D.; Highly efficient perovskite solar cells with crosslinked PCBM interlayers; Journal of Materials Chemistry A; vol. 5; issue 6; pp. 2466-2472; 2017.

Qiu, W.; Ray, A.; Jaysankar, M.; Merckx, T.; Bastos, J.; Poortmans, J.; Heremans, P.; An Interdiffusion Method for Highly Performing Cesium/Formamidinium Double Cation Perovskites; Advanced Functional Materials; vol. 27; issue 28; pp. 1700920-1700928; 2017.

Raducanu, B.; Yazicioglu, R.; Lopez, C.; Ballini, M.; Putzeys, J.; Wang, S.; Andrei, A.; Rochus, V.; Welkenhuysen, M.; Helleputte, N.; Musa, S.; Puers, B.; Kloosterman, F.; Hoof, C.; Fiáth, R.; Ulbert, I.; Mitra, S.; Time Multiplexed Active Neural Probe with 1356 Parallel Recording Sites; Sensors; vol. 17; issue 10; art.nr. E2388; 2017.

Reyserhove, H.; Dehaene, W.; A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs; IEEE Journal of Solid-State Circuits; vol. 52; issue 7; pp. 1904-1914; 2017.

Rolin, C.; Kang, E.; Lee, J.; Borghs, G.; Heremans, P.; Genoe, J.; Charge carrier mobility in thin films of organic semiconductors by the gated van der Pauw method; Nature Communications; vol. 8; art.nr. 10.1038/ncomms14975; pp. 14975; 2017.

Schiavone, G.; Lamichhane, B.; Van Hoof, C.; The double layer methodology and the validation of eigenbehavior techniques applied to lifestyle modeling; BioMed Research International; vol. 2017; pp. 4593956; 2017.

Standaert, A.; Rousstia, M.; Sinaga, S.; Reynaert, P.; Permittivity Measurements in Millimeter Range of PTFE foams; IEEE Microwave and Wireless Components Letters; vol. PP; issue 99; pp. 0-0; 2017.

Steudel, S.; van der Steen, J.; Nag, M.; Ke, T.; Smout, S.; Bel, T.; van Diesen, K.; de Haas, G.; Maas, J.; de Riet, J.; Rovers, M.; Verbeek, R.; Huang, Y.; Chiang, S.; Ameys, M.; De Roose, F.; Dehaene, W.; Genoe, J.; Heremans, P.; Gelinck, G.; Kronemeijer, A.; Power saving through state retention in IGZO-TFT AMOLED displays for wearable applications; Journal of the Society for Information Display; vol. 25; issue 4; pp. 222-228; 2017.

141

Vais, A.; Franco, J.; Martens, K.; Lin, D.; Sioncke, S.; Putcha, V.; Nyns, L.; Maes, J.; Xie, Q.; Givens, M.; Tang, F.; Jiang, X.; Mocuta, A.; Collaert, N.; Thean, A.; De Meyer, K.; A new quality metric for III-V/high-k MOS gate stacks based on the frequency dispersion of accumulation capacitance and the CET; IEEE Electron Device Letters; vol. 38; issue 3; pp. 318-321; 2017.

Vais, A.; Franco, J.; Lin, D.; Putcha, V.; Sioncke, S.; Mocuta, A.; Collaert, N.; Thean, A.; De Meyer, K.; On the distribution of oxide defect levels in Al2O3 and HfO2 high-k dielectrics deposited on InGaAs Metal-Oxide-Semiconductor devices studied by capacitance-voltage hysteresis; Journal of Applied Physics; vol. 121; issue 14; pp. 144504; 2017.

Van Damme, T.; Gardeitchik, T.; Mohamed, M.; Guerrero-Castillo, S.; Freisinger, P.; Guillemyn, B.; Kariminejad, A.; Dalloyaux, D.; van Kraaij, S.; Lefeber, D.; Syx, D.; Steyaert, W.; De Rycke, R.; Hoischen, A.; Kamsteeg, E.; Wong, S.; van Scherpenzeel, M.; Jamali, P.; Brandt, U.; Nijtmans, L.; Korenke, G.; Chung, B.; Mak, C.; Hausser, I.; Kornak, U.; Fischer-Zirnsak, B.; Strom, T.; Meitinger, T.; Alanay, Y.; Utine, G.; Leung, P.; Ghaderi-Sohi, S.; Coucke, P.; Symoens, S.; De Paepe, A.; Thiel, C.; Haack, T.; Malfait, F.; Morava, E.; Wevers, R.; Callewaert, B.; Mutations in ATP6V1E1 or ATP6V1A Cause Autosomal-Recessive Cutis Laxa; American Journal of Human Genetics; vol. 100; art.nr. S0002-9297(16)30534-1; pp. 1-12; 2017, 2016.

Verhelst, M.; Moons, B.; Embedded Deep Neural Network Processing: Algorithmic and Processor Techniques Bring Deep Learning to IoT and Edge Devices; IEEE Solid-State Circuits Magazine; vol. 9; issue 4; pp. 55-65; 2017.

Vermeulen, B.; Wu, J.; Swerts, J.; Couet, S.; Radu, I.; Groeseneken, G.; Detavernier, C.; Jochum, J.; Van Bael, M.; Temst, K.; Shukla, A.; Miwa, S.; Suzuki, Y.; Martens, K.; Perpendicular magnetic anisotropy of CoFeB\ Ta bilayers on ALD HfO2; AIP Advances; vol. 7; issue 5; art.nr. 055933; 2017.

Vershilovskaya, I.; Stefani, S.; Verstappen, P.; Ngo, T.; Scheblykin, I.; Dehaene, W.; Maes, W.; Kruk, M.; Spectral-luminescent properties of meso-tetraarylporphyrins revisited: the role of aryl type, substitution pattern and macrocycle core protonation; Macroheterocycles; vol. 10; issue 2; pp. 1-11; 2017.

Vigilante, M.; Reynaert, P.; On the Design of Wideband Transformer-Based Fourth Order Matching Networks forE-Band Receivers in 28-nm CMOS; IEEE Journal of Solid-State Circuits; vol. 52; issue 8; pp. 2071-2082; 2017.

Vigilante, M.; McCune, E.; Reynaert, P.; To EVM or Two EVMs?: An Answer to the Question; IEEE Solid-State Circuits Magazine; vol. 9; issue 3; pp. 36-39; 2017.

Wieringa, F.; Broers, N.; Kooman, J.; Van Der Sande, F.; Van Hoof, C.; Wearable sensors: Can they benefit patients with chronic kidney disease?; Expert Review of Medical Devices; vol. 14; issue 7; pp. 505-519; 2017.

Wu, X.; Asselberghs, I.; Politou, M.; Contino, A.; Radu, I.; Huyghebaert, C.; Tokei, Z.; Soree, B.; De Gendt, S.; De Feyter, S.; Heyns, M.; Doping of graphene for the application in nano-interconnect; Microelectronic Engineering; vol. 167; pp. 42-46; 2017.

Xu, J.; Mitra, S.; Van Hoof, C.; Yazicioglu, F.; Makinwa, K.; Active electrodes for wearable EEG acquisition: review and design methodology; IEEE Reviews in Biomedical Engineering; vol. 10; pp. 1-11; 2017.

Zhao, C.; Wood, G.; Pu, S.; Kraft, M.; A mode-localized MEMS electrical potential sensor based on three electrically coupled resonators; JOURNAL OF SENSORS AND SENSOR SYSTEMS; vol. 6; issue 1; pp. 1-8; 2017.

Zhao, D.; Reynaert, P.; 21.3 dBm 18.5 GHz-BW 8-way E-band power amplifier in 28 nm high performance mobile CMOS; Electronics Letters; vol. 53; issue 19; pp. 1310-1312; 2017.

13.2 Books, internationally recognised scientific publisher; as editor

(2017). Nanoelectronics. (Puers, B., Ed., Baldi, L., Ed., Van de Voorde, M., Ed., van Nooten, S., Ed.). Germany: Wiley-VCH.

(2017). Nanoelectronics. (Puers, B., Ed., Baldi, L., Ed., Van de Voorde, M., Ed., van Nooten, S., Ed.). Germany: Wiley-VCH.

142

13.3 Book chapters, internationally recognised scientific publisher

Ceyssens, F.; Puers, B.; Integrated Sensors and Actuators: Their Nano-Enabled Evolution into the Twenty-First Century; vol. 1; 2017.

Mohan, R.; Zaliasl, S.; Van Hoof, C.; Van Helleputte, N.; Time-based biomedical readout in ultra-low-voltage small-scale CMOS technology; 2017.

Pamula, V.; Van Hoof, C.; Verhelst, M.; An ultra-low power, robust photoplethysmographic readout exploiting compressive sampling, articfact reduction and sensor fusion; 2017.

Pamula, V.; Van Hoof, C.; Verhelst, M.; An ultra-low power, robust photoplethysmographic readout exploiting compressive sampling, artifact reduction and sensor fusion; 2017.

Reynaert, P.; Steyaert, W.; Vigilante, M.; RF CMOS; 2017.

Stanzione, S.; van Liempd, C.; Van Hoof, C.; An ultra-low-power electrostatic energy harvester interface; 2017.

Van Helleputte, N.; Xu, J.; Ha, H.; Van Wegberg, R.; Song, S.; Stanzione, S.; Zaliasl, S.; van den Hoven, R.; Qiu, W.; Xin, H.; Van Hoof, C.; Konijnenburg, M.; Advances in biomedial sensor systems for wearable health; 2017.

13.4 Papers at international conferences and symposia, published in full in proceedings

Agarwal Kumar, T.; Szabo, A.; Garcia Bardon, M.; Soree, B.; Radu, I.; Raghavan, P.; Luisier, M.; Dehaene, W.; Heyns, M.; Benchmarking of monolithic 3D integrated MX2 FETs with Si FinFETs; IEEE International Electron Devices Meeting - IEDM; pp. 131-134; IEEE International Electron Devices Meeting - IEDM; San Francisco, CA USA; 2017-12-02; 2017.

Agarwal Kumar, T.; Soree, B.; Radu, I.; Raghavan, P.; Fiori, G.; Heyns, M.; Dehaene, W.; Material selection and device design guidelines for two-dimensional materials based TFETs; 47th European Solid-State Device Research Conference - ESSDERC; pp. 54-57; 47th European Solid-State Device Research Conference - ESSDERC; Leuven Belgium; 2017-09-11; 2017.

Agarwal, S.; Ingels, M.; Pantouvaki, M.; Steyaert, M.; Absil, P.; Van Campenhout, J.; Highly integrated wavelength-locked Si photonic ring transmitter using direct monitoring of drop-port OMA; 43rd European Solid-State Circuits Conference - ESSCIRC; pp. 111-114; 43rd European Solid-State Circuits Conference - ESSCIRC; Leuven Belgium; 2017-09-11; 2017.

Andraud, M.; Berkol, G.; De Roose, J.; Gannavarapu, S.; Xin, H.; Cantatore, E.; Harpe, P.; Verhelst, M.; Baltus, P.; Exploring the unknown through low power and low resource versatile agents; Proceedings of Design Automation and Test conference 2017; pp. 290-293; Design Automation and Test in Europe (DATE); Lausanne; 27-31 March 2017; 2017.

Appeltans, R.; Weckx, P.; Raghavan, P.; Kim, R.; Kar, G.; Furnemont, A.; Van der Perre, L.; Dehaene, W.; The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7; Design-Process-Technology Co-optimization for Manufacturability XI; pp. 101480G; Design-Process-Technology Co-optimization for Manufacturability XI; San Jose, CA USA; 2017-02-26; 2017.

Ballini, M.; Bae, J.; Marrocco, N.; Verplancke, R.; Schaubroeck, D.; Cuypers, D.; Cauwe, M.; O’Callaghan, J.; Fahmy, A.; Maghari, N.; Bashirullah, R.; Van Hoof, C.; Van Helleputte, N.; Op de Beeck, M.; Braeken, D.; Mitra, S.; Intraneural active probe for bidirectional peripheral nerve interface; Symposium on VLSI Circuits; pp. c50-c51; Symposium on VLSI Circuits; Kyoto Japan; 2017-06-05; 2017.

Bao, J.; Markovic, T.; Ocket, I.; Kil, D.; Brancato, L.; Puers, B.; Nauwelaers, B.; Investigation of thermal effect caused by different input power of biosensor using a novel microwave and optical sensing system for biological liquids; Proceedings of the IEEE International Microwave Bio Conference 2017; pp. 1-4; 2017 First IEEE MTT-S International Microwave Bio Conference (IMBIOC); Goteborg, Sweden; 15-17 May 2017; 2017.

Bao, X.; Ocket, I.; Kil, D.; Bao, J.; Puers, B.; Nauwelaers, B.; Liquid Measurements at Microliter volumes using 1-Port Coplanar Interdigital Capacitor; 2017 First IEEE MTT-S International Microwave Bio Conference (IMBIOC 2017); pp. 18-20; 2017 First IEEE MTT-S International Microwave Bio Conference (IMBIOC 2017); Gothenburg, Sweden; 15-17 May 2017; 2017.

143

Bizindavyi, J.; Verhulst, A.; Smets, Q.; Verreck, D.; Collaert, N.; Mocuta, A.; Soree, B.; Groeseneken, G.; Calibration of the high-doping induced ballistic band-tails tunneling current in In0.53Ga0.47As Esaki diodes; Fifth Berkeley Symposium on Energy Efficient Electronic Systems and Steep Transistors Workshop; Fifth Berkeley Symposium on Energy Efficient Electronic Systems and Steep Transistors Workshop; Berkeley, CA USA; 2017-10-19; 2017.

Bos, T.; Badami, K.; Dehaene, W.; Verhelst, M.; An 8-11 Bit 320kS/S Resolution Scalable Noise Shaping SAR ADC; 2017 15th IEEE International New Circuits and Systems Conference; vol. 15; pp. 209-212; IEEE International New Circuits and Systems Conference; Strasbourg, France; 26-28 June 2017; 2017.

Boschke, R.; Chen, S.; Scholz, M.; Hellings, G.; Linten, D.; Witters, L.; Collaert, N.; Groeseneken, G.; ESD ballasting of Ge Finfet ggNMOS devices; International Reliability Physics Symposium - IRPS; pp. 3F-3.1-3F-3.6; International Reliability Physics Symposium - IRPS; Monterey, CA USA; 2017-04-02; 2017.

Brancato, L.; Weydts, T.; Soebadi, M.; De Ridder, D.; Puers, B.; Submucosal Exploration of EMG and Physiological Parameters in the Bladder Wall; Proceedings; vol. 1; issue 4; pp. 1-5; Eurosensors; Paris; 3-6 September 2017; 2017.

Brancato, L.; Weydts, T.; Oosterlinck, W.; Herijgers, P.; Puers, B.; Biocompatible Packaging of an Epicardial Accelerometer for Real-time Assesment of Cardiac Motion; Proceedia Engineering; vol. 168; pp. 80-83; Eurosensors; Budapest; 4-7 September 2016; 2017.

Bury, E.; Kaczer, B.; Chuang, K.; Franco, J.; Weckx, P.; Vaisman Chasin, A.; Simicic, M.; Linten, D.; Groeseneken, G.; Statistical assessment of the full VG/VD degradation space using dedicated device arrays; IEEE International Reliability Physics Symposium - IRPS; pp. 2D-5.1-2D-5.6; IEEE International Reliability Physics Symposium - IRPS; Monterey, CA USA; 2017-04-02; 2017.

Butzen, N.; Steyaert, M.; A 1.1 W/mm2-Power-Density 82%-Efficiency Fully Integrated 3: 1 Switched-Capacitor DC-DC Converter in Baseline 28nm CMOS using Stage Outphasing and Multiphase Soft-Charging; Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 60; pp. 178-179; International Solid-State Circuits Conference; San Francisco; 5-9 February 2017; 2017.

Cecconi, L.; Smets, S.; Benini, L.; Verhelst, M.; Optimal Tiling Strategy for Memory Bandwidth Reduction for CNNs; pp. 89-100; Advanced Concepts for Intelligent Vision Systems; Antwerp, Belgium; 18-21 September 2017; 2017.

Chen, S.; Hellings, G.; Linten, D.; Chiarella, T.; Mertens, H.; Boschke, R.; Mitard, J.; Kubicek, S.; Ritzenthaler, R.; Bury, E.; Wang, N.; Groeseneken, G.; Mocuta, A.; Horiguchi, N.; Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes; IEEE International Electron Devices Meeting - IEDM; pp. 171-174; IEEE International Electron Devices Meeting - IEDM; San Francisco, CA USA; 2017-12-02; 2017.

Dai, C.; Chen, S.; Linten, D.; Scholz, M.; Hellings, G.; Boschke, R.; Karp, J.; Hart, M.; Groeseneken, G.; Ker, M.; Mocuta, A.; Horiguchi, N.; Latchup in bulk finFET technology; IEEE International Reliability Physics Symposium - IRPS; pp. EL-1.1-EL-1.3; IEEE International Reliability Physics Symposium - IRPS; Monterey, CA USA; 2017-04-01; 2017.

De Pelecijn, E.; High speed time-multiplexed continuous time Sigma-Delta converters; IEEE EUROCON 2017 -17th International Conference on Smart Technologies; pp. 972-977; EUROCON; Ohrid, Macedonia; 6-8 July 2017; 2017.

De Smet, H.; De Roose, F.; Steudel, S.; Myny, K.; Willegems, M.; Smout, S.; Ameys, M.; Malinowski, P.; Gehlhaar, R.; Poduval, R.; Chen, X.; De Smet, J.; Vasquez Quintero, A.; Dehaene, W.; Genoe, J.; Thin and spherical-cap-shaped LCD with a flexible thin-film driver for use in a smart contact lens; Society for Information Display Mid-Europe Chapter Spring Meeting; Dresden; 12-13 March 2017; 2017.

De Wit, M.; Reynaert, P.; An F-band Active Phase Shifter in 28nm CMOS; 2017 IEEE MTT-S International Microwave Symposium (IMS); pp. 965-968; International Microwave Symposium; Honolulu; 4-9 June; 2017.

Devos, A.; Vigilante, M.; Reynaert, P.; Multiphase Digitally Controlled Oscillator for Future 5G Phased Arrays in 90 nm CMOS; Proceedings 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS); pp. 10-14; NORCAS; Copenhagen; 1-2 November 2016; 2017.

Diels, W.; Steyaert, M.; Tavernier, F.; Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers; 2017 European Solid-State Device Research Conference (ESSDERC); pp. 224-227; European Solid-State Device Research Conference (ESSDERC); Leuven; 11-14 September 2017; 2017.

Diels, W.; Steyaert, M.; Tavernier, F.; Schottky diodes in 40nm bulk CMOS for 1310nm high-speed optical receivers; 2017 Optical Fiber Communications Conference and Exhibition (OFC); pp. 1-3; Optical Fiber Communication Conference and Exhibition; Los Angeles; 19-23 March 2017; 2017.

144

Florent, K.; Lavizzari, S.; Di Piazza, L.; Popovici, M.; Vecchio, E.; Potoms, G.; Groeseneken, G.; Van Houdt, J.; First demonstration of vertically stacked ferroelectric Al doped HfO2 devices for NAND applications; Symposium on VLSI Technology; pp. 158-159; Symposium on VLSI Technology; Kyoto Japan; 2017-06-05; 2017.

Florent, K.; Lavizzari, S.; Di Piazza, L.; Popovici, M.; Potoms, G.; Raymaekers, T.; Groeseneken, G.; Van Houdt, J.; From planar to vertical capacitors : a first step towards ferroelectric V-FeFET integration; 47th European Solid-State Device Research Conference - ESSDERC; pp. 164-167; 47th European Solid-State Device Research Conference - ESSDERC; Leuven Belgium; 2017-09-11; 2017.

Franco, J.; Putcha, V.; Vais, A.; Sioncke, S.; Waldron, N.; Zhou, D.; Rzepa, G.; Roussel, P.; Groeseneken, G.; Heyns, M.; Collaert, N.; Linten, D.; Grasser, T.; Kaczer, B.; Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs; IEEE International Electron Devices Meeting - IEDM; pp. 175-178; IEEE International Electron Devices Meeting - IEDM; San Francisco, CA USA; 2017-12-02; 2017.

Franco, J.; Witters, L.; Vandooren, A.; Arimura, H.; Sioncke, S.; Putcha, V.; Vais, A.; Xie, Q.; Givens, M.; Tang, F.; Jiang, X.; Subirats, A.; Vaisman Chasin, A.; Ragnarsson, L.; Kaczer, B.; Linten, D.; Collaert, N.; Gate stack thermal stability and PBTI reliability challenges for 3D sequential integration: demonstration of a suitable gate stack for top and bottom tier nMOS; IEEE International Reliability Physics Symposium - IRPS; pp. 2B-3.1-2B3.5; IEEE International Reliability Physics Symposium - IRPS; Monterey, CA USA; 2017-04-02; 2017.

Genoe, J.; Verschueren, L.; De Roose, F.; Dehaene, W.; Heremans, P.; Pixel current calibration in digital-driven active matrix displays; 17th International Meeting on Information Display - IMID; pp. C67-1; 17th International Meeting on Information Display - IMID; Busan South-Korea; 2017-08-28; 2017.

Georgitzikis, E.; Malinowski, P.; Mamun, M.; Enzing, O.; Maes, J.; Hens, Z.; Heremans, P.; Cheyns, D.; Determining charge carrier extraction in lead sulfide quantum dot near infrared photodetectors; Physical Chemistry of Semiconductor Materials and Interfaces XVI; pp. 103480B; Physical Chemistry of Semiconductor Materials and Interfaces XVI; San Diego, CA USA; 2017-08-06; 2017.

Goovaerts, L.; De Cock, M.; Dehaene, W.; Integrated STEM: The passive house; pp. NA-NA; EAPRIL; Hämeenlinna, Finland; 29 November - 1 December 2017; 2017.

Goovaerts, L.; Struyven, K.; De Cock, M.; Dehaene, W.; Process evaluation for integrated STEM; ESERA; Dublin; 21-25 July 2017; 2017.

Guo, K.; Reynaert, P.; A 475-511GHz Radiating Source with SIW-based Harmonic Power Extractor in 40 nm CMOS; 2017 IEEE MTT-S International Microwave Symposium (IMS); Honololu, HI, USA; 4-9 June 2017; 2017.

Gupta, M.; Weckx, P.; Cosemans, S.; Schuddinck, P.; Baert, R.; Jang, D.; Sherazi, Y.; Raghavan, P.; Spessot, A.; Mocuta, A.; Dehaene, W.; Dedicated Technology Threshold voltage tuning for 6T SRAM beyond N7; pp. 1-4; International Conference on Integrated Circuit Design and Technology (ICICDT); Texas, Austin; 23-25 May 2017; 2017.

Gupta, M.; Weckx, P.; Cosemans, S.; Schuddinck, P.; Baert, R.; Jang, D.; Sherazi, Y.; Raghavan, P.; Spessot, A.; Mocuta, A.; Dehaene, W.; Dedicated technology threshold voltage tuning for 6T SRAM beyond N7; IEEE International Conference on Integrated Circuit Design and Technology - ICICDT; pp. 1-4; IEEE International Conference on Integrated Circuit Design and Technology - ICICDT; Austin, TX USA; 2017-05-23; 2017.

Gupta, M.; Weckx, P.; Cosemans, S.; Schuddinck, P.; Baert, R.; Yakimets, D.; Jang, D.; Sherazi, Y.; Raghavan, P.; Spessot, A.; Mocuta, A.; Dehaene, W.; Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7; Proceedings of the 47th European Solid-State Device Research Conference (ESSDERC); vol. 2017; pp. 256-259; European Solid-State Device Research Conference (ESSDERC); Leuven, Belgium; 11-14 September 2017; 2017.

Gupta, M.; Weckx, P.; Cosemans, S.; Schuddinck, P.; Baert, R.; Jang, D.; Sherazi, Y.; Raghavan, P.; Kaczer, B.; Spessot, A.; Mocuta, A.; Dehaene, W.; SRAM enablement beyond N7: a BTI study; IEEE International Reliability Physics Sysmposium - IRPS; pp. 4.1-4.6; International Reliability Physics Symposium (IRPS); Monterey, California; 2-6 April 2017; 2017.

Gurné, T.; Strackx, M.; Tytgat, M.; Cools, J.; Reynaert, P.; A 20Gbps 1.2GHz Full-Duplex Integrated AFE in 28nm CMOS for Copper Access; IEEE European Solid-State Circuits Conference (ESSCIRC); vol. 43; pp. 107-110; ESSCIRC; Leuven; 7-11 September 2017; 2017.

Ha, H.; Konijnenburg, M.; Lukita, B.; Van Wegberg, R.; Xu, J.; van den Hoven, R.; Lemmens, M.; Thoelen, R.; Van Hoof, C.; Van Helleputte, N.; A bio-impedance readout IC with frequency sweeping from 1k-to-1MHz for electrical impedance tomography; Symposium on VLSI Circuits; pp. C174-C175; Symposium on VLSI Circuits; Kyoto Japan; 2017-06-05; 2017.

145

Hallawa, A.; De Roose, J.; Andraud, M.; Verhelst, M.; Ascheid, G.; Instinct-driven dynamic hardware reconfiguration: evolutionary algorithm optimized compression for autonomous sensory agents; Proceedings of the Genetic and Evolutionary Computation Conference GECCO; pp. 1727-1734; GECCO; Berlin; July 15th-19th 2017; 2017.

Heremans, P.; de Jamblinne de Meux, A.; Bhoolokam, A.; Pourtois, G.; On the origin of NBS and NBIS in amorphous IGZO; 17th International Meeting on Information Display - IMID; pp. 1-5; 17th International Meeting on Information Display - IMID; Busan Korea; 2017-08-28; 2017.

Heremans, P.; Present and future technologies and applications of thin-film circuitry on flexible substrates; International Conference on Flexible and Printed Electronics - ICFPE; International Conference on Flexible and Printed Electronics - ICFPE; Jeju Korea; 2017-09-05; 2017.

Heremans, P.; Scaling AMOLED displays to high resolution; International Conference on Display Technology - ICDT; International Conference on Display Technology - ICDT; Fuzhou, Fujian China; 2017-02-20; 2017.

Huang, Y.; Desset, C.; Bourdoux, A.; Dehaene, W.; Van der Perre, L.; Massive MIMO Processing at the Semiconductors Edge: Exploiting the System and Circuit Margins for Power Savings; Proceedings of the 42nd IEEE International Conference on Acoustics, Speech and Signal Processing; IEEE International Conference on Acoustics, Speech and Signal Processing; New Orleans, USA; March 2017; 2017.

Indirayanti, P.; Reynaert, P.; A 32 GHz20 dBm-PSAT Transformer-based Doherty Power Amplifier for multi-Gb/s 5G Applications in 28 nm Bulk CMOS; pp. 1-3; IEEE Radio Frequency Integrated Circuits Symposium (RFIC); Honolulu, Hawai, USA; 4-6 June 2017; 2017.

Jeong, Y.; Huang, C.; Cheyns, D.; Brondani Torri, G.; Rottenberg, X.; Heremans, P.; pMUT device compatible with large-area display technology; 16th International Symposium on Electrets; 16th International Symposium on Electrets; Leuven Belgium; 2017-09-04; 2017.

Kaczer, B.; Rzepa, G.; Franco, J.; Weckx, P.; Vaisman Chasin, A.; Putcha, V.; Bury, E.; Simicic, M.; Roussel, P.; Hellings, G.; Veloso, A.; Matagne, P.; Grasser, T.; Linten, D.; Benchmarking time-dependent variability of junctionless nanowire FETs; International Reliability Physics Symposium - IRPS; pp. 2D-6.1-2D-6.7; International Reliability Physics Symposium - IRPS; Monterey, CA USA; 2017-04-02; 2017.

Ke, T.; Malinowski, P.; Nag, M.; Steudel, S.; Myny, K.; Genoe, J.; Kronemeijer, A.; van der Steen, J.; Gelinck, G.; Heremans, P.; Thin-film electronics for next generation display and IOT applications; International Display Manufacturing Conference - IDMC; pp. Fri-S19-01; International Display Manufacturing Conference - IDMC; Taipei Taiwan; 2017-09-20; 2017.

Khajenasiri, I.; Estebsari, A.; Verhelst, M.; Gielen, G.; A review on Internet of Things Solutions for Intelligent Energy control in buildings for smart city applications; Energy Procedia; vol. 111; pp. 770-779; 8th International Conference on Sustainability in Energy and Buildings (SEB); Turin, Italy; 11-13 Sept 2016; 2017.

Kil, D.; De Vloo, P.; Nuttin, B.; Puers, B.; A foldable neural electrode for 3D stimulation of Deep Brain Cavities; Procedia Engineering; vol. 168; pp. 137-142; Eurosensors; Budapest; 4-7 September 2016; 2017.

Kil, D.; Brancato, L.; Puers, B.; Dextran as a fast resorbable and mechanically stiff coating for flexible neural probes; Journal of Physics: Conference Series; vol. 922; Micromechanics and Microsystems Europe Workshop; Uppsala; 23-25 August 2017; 2017.

Kraak, D.; Agbo, I.; Taouil, M.; Hamdioui, S.; Weckx, P.; Cosemans, S.; Catthoor, F.; Dehaene, W.; Mitigation of sense amplifier degradation using input switching; 20th ACM/IEEE Design and Test in Europe Conference - DATE; pp. 858-863; 20th ACM/IEEE Design and Test in Europe Conference - DATE; Dresden Germany; 2017-03-28; 2017.

Kraak, D.; Agbo, I.; Taouil, M.; Hamdioui, S.; Weckx, P.; Cosemans, S.; Catthoor, F.; Dehaene, W.; Sense amplifier offset voltage mitigation under presence of BTI; Workshop on Reliability, Security and Quality - RESCUE; Workshop on Reliability, Security and Quality - RESCUE; Limassol Cyprus; 2017-05-22; 2017.

Levrie, K.; Jans, K.; Schepers, G.; Vos, R.; Van Dorpe, P.; Lagae, L.; Van Hoof, C.; Van Aerschot, A.; Stakenborg, T.; High resolution multiplexing for DNA arrays using a multi-electrode chip; 49th International Conferece on Solid State Devices and Materials - SSDM; pp. 945-946; 49th International Conferece on Solid State Devices and Materials - SSDM; Sendai Japan; 2017-09-19; 2017.

146

Li, X.; Van Hove, M.; Zhao, M.; Geens, K.; Lempinen, V.; Sormunen, J.; Stoffels, S.; Groeseneken, G.; Decoutere, S.; 200 V enhancement-mode p-GaN HEMTs fabricated on 200 mm GaN-on-SOI with trench isolation for monolithic integration; 41st Workshop on Compound Semiconductor Devices and Integrated Circuits - WOCSDICE; pp. 103-104; 41st Workshop on Compound Semiconductor Devices and Integrated Circuits - WOCSDICE; Las Palmas de Gran Canaria Spain; 2017-05-21; 2017.

Lorusso, G.; Ohashi, T.; Yamaguchi, A.; Inoue, O.; Sutani, T.; Horiguchi, N.; Boemmels, J.; Wilson, C.; Briggs, B.; Tan, C.; Raymaekers, T.; Delhougne, R.; Van den Bosch, G.; Di Piazza, L.; Kar, G.; Furnemont, A.; Fantini, A.; Donadio, G.; Souriau, L.; Crotti, D.; Yasin, F.; Appeltans, R.; Rao, S.; De Simone, D.; Rincon Delgadillo, P.; Leray, P.; Charley, A.; Zhou, D.; Veloso, A.; Collaert, N.; Hasumi, K.; Koshihara, S.; Ikota, M.; Okagawa, Y.; Ishimoto, T.; Enabling CD SEM metrology for 5nm technology node and beyond; Metrology, Inspection, and Process Control for Microlithography XXXI; pp. 1014512; Metrology, Inspection, and Process Control for Microlithography XXXI; San Jose, CA USA; 2017-02-26; 2017.

Malinowski, P.; Georgitzikis, E.; Maes, J.; Mamun, M.; Enzing, O.; Frazzica, F.; Van Olmen, J.; De Moor, P.; Heremans, P.; Hens, Z.; Cheyns, D.; Monolithic near infrared image sensors enabled by quantum dot photodetector; International Image Sensor Workshop - IISW; pp. R54; International Image Sensor Workshop - IISW; Hiroshima Japan; 2017-05-30; 2017.

Malinowski, P.; Ke, T.; Nakamura, A.; Vicca, P.; Kronemeijer, A.; Ameys, M.; van der Steen, J.; Steudel, S.; Kamochi, Y.; Iwai, Y.; Gelinck, G.; Heremans, P.; Photolithography as enabler of AMOLED displays beyond 1000 ppi; SID Symposium; pp. 623-626; SID Symposium; Los Angeles, CA USA; 2017-05-21; 2017.

Markovic, T.; Bao, J.; Ocket, I.; Kil, D.; Brancato, L.; Puers, B.; Nauwelaers, B.; Uniplanar microwave heater for digital microfluidics; Proceedings of the IEEE International Microwave Bio Conference 2017; pp. 1-4; 2017 First IEEE MTT-S International Microwave Bio Conference (IMBIOC); Goteborg, Sweden; 15-17 May 2017; 2017.

Meng, D.; Zhang, J.; Zhang, J.; Zhang, W.; Ji, Z.; Benbakhti, B.; Zheng, X.; Hao, Y.; Vigar, D.; Adamu-Lema, F.; Chandra, V.; Aitken, R.; Kaczer, B.; Groeseneken, G.; Asenov, A.; Interaction between hot carrier aging and PBTI degradation in nMOSFETs: characterization, modelling and lifetime prediction; IEEE International Reliability Physics Symposium - IRPS; pp. XT-5.1-XT-5.7; IEEE International Reliability Physics Symposium - IRPS; Monterey, CA USA; 2017-04-02; 2017.

Mercuri, M.; Liu, Y.; Young, A.; Torfs, T.; Bourdoux, A.; Van Hoof, C.; Digital IF phase-tracking doppler radar for accurate displacement measurements and vital signs monitoring; IEEE MTT-S International Microwave Symposium - IMS; pp. 1-4; IEEE MTT-S International Microwave Symposium - IMS; Honolulu, HI Hawaii; 2017-06-04; 2017.

Molderez, T.; de Wit, B.; Rabaey, K.; Verhelst, M.; Successive Parabolic Interpolation as Extremum Seeking Control for Microbial Fuel & Electrolysis Cells; IECON 2017; Beijing; 29 October - 1 November 2017; 2017.

Moons, B.; Uytterhoeven, R.; Dehaene, W.; Verhelst, M.; DVAFS: Trading Computational Accuracy for Energy Through Dynamic-Voltage-Accuracy-Frequency-Scaling; Design, Automation and Test in Europe (DATE); vol. 20; pp. 488-493; Design, Automation and Test in Europe (DATE); Lausanne; 27-31 March 2017; 2017.

Moons, B.; Uytterhoeven, R.; Dehaene, W.; Verhelst, M.; Envision: A 0.26-to-10 TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI; IEEE International Solid-State Circuits Conference (ISSCC); pp. 246-247; IEEE International Solid-State Circuits Conference (ISSCC); San Francisco; 6-8 February 2017; 2017.

Myny, K.; Lai, Y.; Papadopoulos, N.; De Roose, F.; Ameys, M.; Willegems, M.; Smout, S.; Steudel, S.; Dehaene, W.; Genoe, J.; A Flexible ISO14443-A Compliant 7.5mW 128b Metal-Oxide NFC Barcode Tag with Direct Clock Division Circuit from 13.56MHz Carrier; Digest of Technical Papers - IEEE International Solid-State Circuits Conference; pp. 258-258; 64th IEEE International Solid-State Circuits Conference (ISSCC); San Francisco: CA; FEB 05-09, 2017; 2017.

Papadopoulos, N.; De Roose, F.; Lai, Y.; van der Steen, J.; Ameys, M.; Dehaene, W.; Genoe, J.; Myny, K.; Flexible Selfbiased 66.7nJ/c.s. 6bit 26S/s successive-approximation C-2C ADC with offset cancellation using unipolar metal-oxide TFTs; IEEE Custom Integrated Circuits Conference - CICC; IEEE Custom Integrated Circuits Conference - CICC; Austin Texas, US; 2017-04-30; 2017.

Pourtois, G.; Dabral, A.; Sankaran, K.; Magnus, W.; Yu, H.; de Jamblinne de Meux, A.; Lu, A.; Clima, S.; Stokbro, K.; Schaekers, M.; Houssa, M.; Collaert, N.; Horiguchi, N.; Probing the intrinsic limitations of the contact resistance of metal/semiconductor interfaces through atomistic simulations; Semiconductors, Dielectrics, and Metals for Nanoelectronics 15: In Memory of Samares Kar; pp. 303-311; Semiconductors, Dielectrics, and Metals for Nanoelectronics 15: In Memory of Samares Kar; National Harbor, MD USA; 2017-10-01; 2017.

147

Putcha, V.; Franco, J.; Vais, A.; Sioncke, S.; Kaczer, B.; Xie, Q.; Calka, P.; Tang, F.; Jiang, X.; Givens, M.; Collaert, N.; Linten, D.; Groeseneken, G.; BTI Reliability of InGaAs nMOS gate-stack: on the impact of shallow and deep defect bands on the operating voltage range of III-V technology; IEEE International Reliability Physics Symposium - IRPS; pp. XT-8.1-XT-8.6; IEEE International Reliability Physics Symposium - IRPS; Monterey, CA USA; 2017-04-02; 2017.

Ramesh, S.; Ivanov, T.; Putcha, V.; Alian, A.; Sibaja-Hernandez, A.; Rooyackers, R.; Camerotto, E.; Milenin, A.; Pinna, N.; El Kazzi, S.; Veloso, A.; Lin, D.; Lagrain, P.; Favia, P.; Collaert, N.; De Meyer, K.; Record performance top-down In0.53Ga0.47As vertical nanowire FETs and vertical nanosheets; IEEE International Electron Devices Meeting - IEDM; pp. 409-412; IEEE International Electron Devices Meeting - IEDM; San Francisco, CA USA; 2017-12-02; 2017.

Ramkaj, A.; Strackx, M.; Steyaert, M.; Tavernier, F.; A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW Single-Channel SAR ADC in 28nm Bulk CMOS; European Solid State Circuits Conference; vol. 43; pp. 167-170; ESSCIRC; Leuven; 11-14 September 2017; 2017.

Reynaert, P.; Steyaert, W.; Standaert, A.; Simic, D.; Guo, K.; MM-wave and THz circuit design in standard CMOS technologies: challenges and opportunities; pp. 0-0; APMC2017; 2017.

Reyserhove, H.; Dehaene, W.; Design Margin Elimination Through Robust Timing Error Detection at Ultra-Low Voltage; Proceedings of the IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S); vol. 2017; pp. 1-3; SOI-3D-Subthreshold Microelectronics Technology Unified Conference; San Francisco; 16-19 October 2017; 2017.

Reyserhove, H.; Dehaene, W.; Design Margin Elimination in a Near-Threshold Timing Error Masking-Aware 32-bit ARM Cortex M0 in 40nm CMOS; Proceedings of the IEEE 43rd European Solid-State Circuits Conference (ESSCIRC); pp. 155-158; IEEE European Solid-State Circuits Conference (ESSCIRC); Leuven; 11-14 September 2017; 2017.

Rolin, C.; Fesenko, P.; Janneck, R.; Genoe, J.; Heremans, P.; Deposition of organic semiconductors: a path to effective devices; Int. Conference on Organic Electronics: Satellite Event ôFlexible electronics and photovoltaics: from science to markets”; Int. Conference on Organic Electronics: Satellite Event “Flexible electronics and photovoltaics: from science to markets”; St Petersbourg Russia; 2017-06-04; 2017.

Sacco, E.; Francese, P.; Brändli, M.; Menolfi, C.; Morf, T.; Cevrero, A.; Ozkaya, I.; Kossel, M.; Kull, L.; Luu, D.; Yueksel, H.; Gielen, G.; Toifl, T.; A 5Gb/s 7.1fJ/b/mm 8× Multi-Drop On-Chip 10mm Data Link in 14nm FinFET CMOS SOI at 0.5V; pp. C54-C55; IEEE Symposium on VLSI Circuits (VLSI); Kyoto, Japan; 5-8 June 2017; 2017.

Sadeghpour Shamsabadi, S.; Pobedinskas, P.; Haenen, K.; Puers, B.; A Piezoelectric Micromachined Ultrasound Transducers (pMUT) Array, for Wide Bandwidth Underwater Communication Applications; Multidisciplinary Digital Publishing Institute Proceedings; vol. 1; issue 4; pp. 364-369; Eurosensor 2017; Paris; 03-06 Sep 2017; 2017.

Sadeghpour Shamsabadi, S.; Meyers, S.; Kruth, J.; Vleugels, J.; Puers, B.; Single-element omnidirectional piezoelectric ultrasound transducer for under water communication; Multidisciplinary Digital Publishing Institute Proceedings; vol. 1; issue 4; pp. 363-363; Eurosensors 2017; Paris, France; 3-6 September 2017; 2017.

Sadeghpour, S.; Pobedinskas, P.; Haenen, K.; Puers, B.; A piezoelectric micromachined ultrasound transducers (pMUT) array; Eurosensors XXXI Conference; pp. 364; Eurosensors XXXI Conference; Paris France; 2017-09-03; 2017.

Sarafianos, A.; Steyaert, M.; A true two-quadrant fully integrated switched capacitor DC-DC converter supporting vertically stacked DVS-loads with up to 99.6% efficiency; 2017 Symposium on VLSI Circuits; pp. C210-C211; Symposium on VLSI circuits; Kyoto, Japan; 5-8 June 2017; 2017.

Simicic, M.; Morrison, S.; Parvais, B.; Weckx, P.; Kaczer, B.; Sawada, K.; Ammo, H.; Yamakawa, S.; Nomoto, K.; Ohno, M.; Linten, D.; Verkest, D.; Wambacq, P.; Groeseneken, G.; Gielen, G.; A fully-integrated method for RTN parameter extraction; Symposium on VLSI Technology; Kyoto, Japan; 5-8 June 2017; 2017.

Sioncke, S.; Franco, J.; Vais, A.; Putcha, V.; Nyns, L.; Sibaja-Hernandez, A.; Rooyackers, R.; Calderon Ardila, S.; Spampinato, V.; Franquet, A.; Maes, W.; Xie, Q.; Givens, M.; Tang, F.; Jiang, X.; Heyns, M.; Linten, D.; Mitard, J.; Thean, A.; Mocuta, D.; Collaert, N.; First demonstration of ~3500 cm2/V-s electron mobility and sufficient BTI reliability (max Vov up to 0.6V) In0.53Ga0.47As nFET using an IL/LaSiOx/HfO2 gate stack; Symposium on VLSI Technology; pp. 38-39; Symposium on VLSI Technology; Kyoto Japan; 2017-06-05; 2017.

148

Steudel, S.; van der Steen, J.; Nag, M.; Ke, T.; Smout, S.; BEL, T.; Van Diesen, K.; de Haas, G.; Maas, J.; de Riet, J.; Rovers, M.; Verbeek, R.; Huang, Y.; Chiang, S.; Ameys, M.; De Roose, F.; Dehaene, W.; Genoe, J.; Heremans, P.; Gelinck, G.; Kronemeijer, A.; Power saving through state retention in IGZO-TFT AMOLED displays for wearable applications; SID - Display Week; pp. 37-41; SID - Display Week; Los Angeles, CA USA; 2017-05-21; 2017.

Steyaert, M.; Sarafianos, A.; Butzen, N.; De Pelecijn, E.; Fully Integrated Power Management: The Missing Link?; 2017 European Conference on Circuit Theory and Design (ECCTD); vol. 2017; pp. 1-4; European Conference on Circuit Theory and Design; Catania, Italy; 4-6 September 2017; 2017.

Steyaert, W.; Reynaert, P.; Layout Optimizations for THz Integrated Circuit Design in Bulk Nanometer CMOS; Proceedings of the CSICS 2017; pp. 82-86; IEEE Compound Semiconductor Integrated Circuit Symposium; Miami, Florida, USA; 22-25 October 2017; 2017.

Theunis, R.; Baert, M.; Leroux, P.; Dehaene, W.; Highly broadband circular polarized patch antenna with 3 phase feed structure; 2017 11th European Conference on Antennas and Propagation; pp. 1-4; European Conference on Antennas and Propagation; Paris, France; 19-24 March 2017; 2017.

Thoen, B.; Ottoy, G.; Rosas, F.; Lauwereins, S.; Rajendran, S.; De Strycker, L.; Pollin, S.; Verhelst, M.; Saving energy in WSNs for acoustic surveillance applications while maintaining QoS; Proceedings 2017 IEEE SENSORS APPLICATIONS SYMPOSIUM (SAS); pp. 1-6; Sensors Applications Symposium (SAS); Glassboro; 13-15 March 2017; 2017.

Vaisman Chasin, A.; Franco, J.; Kaczer, B.; Putcha, V.; Weckx, P.; Ritzenthaler, R.; Mertens, H.; Horiguchi, N.; Linten, D.; Rzepa, G.; BTI reliability and time-dependent variability of stacked gate-all-around Si nanowire transistors; IEEE International Reliability Physics Symposium - IRPS; pp. 5C-4.1-5C-4.7; IEEE International Reliability Physics Symposium - IRPS; Monterey, CA USA; 2017-04-02; 2017.

Van Beek, S.; Martens, K.; Roussel, P.; Couet, S.; Souriau, L.; Swerts, J.; Kim, W.; Rao, S.; Mertens, S.; Lin, T.; Crotti, D.; Degraeve, R.; Bury, E.; Linten, D.; Kar, G.; Groeseneken, G.; Impact of processing and stack optimization on the reliability of perpendicular STT-MRAM; IEEE International Reliability Physics symposium - IRPS; pp. 5A-1.1-5A-1.5; IEEE International Reliability Physics symposium - IRPS; Monterey, CA USA; 2017-04-02; 2017.

Van Thienen, N.; Reynaert, P.; A 120GHz In-Band Full-Duplex PMF Transceiver with Tunable Electrical-Balance Duplexer in 40nm CMOS; Proceedings of the ESSCIRC; pp. 103-106; ESSCIRC; Leuven; 11-14 September 2017; 2017.

Vermeulen, B.; Radu, I.; Temst, K.; Groeseneken, G.; Martens, K.; Ferromagnetic thin films on high-k dielectrics: how and why?; IEEE Magnetics Society Summer School; IEEE Magnetics Society Summer School; Santander Spain; 2017-06-18; 2017.

Verreck, D.; Verhulst, A.; Van de Put, M.; Soree, B.; Magnus, W.; Collaert, N.; Mocuta, A.; Groeseneken, G.; Self-consistent 30-band simulation approach for (non-)uniformly strained confined heterostructure tunnel field-effect transistors; International Conference on Simulation of Semiconductor Processes and Devices - SISPAD; pp. 29-32; International Conference on Simulation of Semiconductor Processes and Devices - SISPAD; Kamakura Japan; 2017-09-07; 2017.

Vigilante, M.; Reynaert, P.; A 29-to-57GHz AM-PM Compensated Class-AB Power Amplifier for 5G Phased Arrays in 0.9V 28nm Bulk CMOS; Proceedings IEEE Radio Frequency Integrated Circuits Conference; pp. 116-119; IEEE Radio Frequency Integrated Circuits Conference; 4-6 June 2017; 2017.

Wang, N.; Chen, S.; Hellings, G.; Myny, K.; Steudel, S.; Scholz, M.; Boschke, R.; Linten, D.; Groeseneken, G.; ESD characterization of a-IGZO TFTs on Si and foil substrates; 47th European Solid-State Device Research Conference - ESSDERC; pp. 276-279; 47th European Solid-State Device Research Conference - ESSDERC; Leuven Belgium; 2017-09-11; 2017.

Weydts, T.; Brancato, L.; Soebadi, M.; De Ridder, D.; Puers, B.; In-Vivo Implantable Sensor System for Measuring Bladder Wall Movements; Proceedings; vol. 1; issue 4; pp. 1-5; Eurosensors; Paris; 03-06 September 2017; 2017.

Xama, N.; Coyette, A.; Esen, V.; Dobbelaere, W.; Vanhooren, R.; Gielen, G.; Automatic Testing of Analog ICs for Latent Defects using Topology Modification; pp. 1-6; IEEE European Test Symposium (ETS); Cyprus; 22-26 May 2017; 2017.

Xu, J.; Konijnenburg, M.; Ha, H.; Van Wegberg, R.; Lukita, B.; Zaliasl, S.; Van Hoof, C.; Van Helleputte, N.; A 36µW reconfigurable analog front-end IC for multimodal vital signs monitoring; Symposium on VLSI Circuits; pp. C170-C171; Symposium on VLSI Circuits; Kyoto Japan; 2017-06-06; 2017.

Zhang, Y.; Reynaert, P.; A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communications in 40nm CMOS; RFIC2017; vol. 1; issue 1; pp. 1-4; RFIC; 2017.

149

Çelik, U.; Steyaert, W.; Reynaert, P.; A 230.5–238.8-GHz magnetically coupled triple-push oscillator with inductive tuning for data transmission in 45-nm CMOS; Ph.D. Research in Microelectronics and Electronics (PRIME), 2017 13th Conference; pp. 185-188; PRIME 2017; Giardini Naxos - Taormina, Italy; 12-15 June 2017; 2017.

13.5 IC-p (Papers at international professionally oriented conferences and symposia, published in full in proceedings)

Goovaerts, L., Struyven, K., De Cock, M., Dehaene, W. (2017). Procesevaluatie binnen STEM@school: stand van zaken, Symposium 41-Symposium 41.

13.6 Meeting abstracts, presented at international conferences and symposia, published or not published in proceedings or journals

Aspell, P.; Bravo, C.; Dabrowski, M.; De Lentdecker, G.; Leroux, P.; De Robertis, G.; Irshad, A.; Lenzi, T.; Licciulli, F.; Loddo, F.; Petrow, H.; Robert, F.; Rosa, J.; Tavernier, F.; Tuuva, T.; A Verification Platform to provide the Functional, Characterization and Production testing for the VFAT3 ASIC; Nuclear Science Symposium; Atlanta, US; 21-28 October 2017; 2017.

Ceuppens, S.; Deprez, J.; Dehaene, W.; De Cock, M.; Design and implementation of optics teaching and learning materials in an integrated STEM Curriculum (Case Study); EAPRIL; 2017; 2017; 2017.

Ceuppens, S.; Deprez, J.; Dehaene, W.; De Cock, M.; Developing and implementing integrated STEM teaching and learning materials for optics; EAPRIL; Finland; 2017; 2017.

Ceuppens, S.; Deprez, J.; Dehaene, W.; De Cock, M.; Effects of an integrated STEM curriculum on linear function problems in physics and mathematics; GIREP-ICPE-EPEC 2017; Dublin; 2017; 2017.

Ceuppens, S.; Deprez, J.; Dehaene, W.; De Cock, M.; Representational fluency of linear relations in physics and mathematics; ESERA; Dublin; 2017; 2017.

Chen, S.; Hellings, G.; Scholz, M.; Linten, D.; Mertens, H.; Ritzenthaler, R.; Boschke, R.; Groeseneken, G.; Mocuta, A.; Horiguchi, N.; vfTLP characteristics of ESD diodes in bulk Si gate-all-around vertically stacked horizontal nanowire technology; 39th Electrical Overstress/Electrostatic Discharge Symposium - EOS/ESD; Tucson, AZ USA; 2017-09-10; 2017.

De Meester, J.; Langie, G.; De Cock, M.; Dehaene, W.; Designing integrated STEM education: how to transform a theory into practical learning units; EAPRIL2017; Hämeenlinna; 29 November - 1 December 2017; 2017.

De Meester, J.; Langie, G.; De Cock, M.; Dehaene, W.; Geïntegreerd STEM-onderwijs: kenmerken van en een model voor het ontwikkelen van STEM-integrerend leermateriaal – een vergelijkende case studie; ORD 2017; Antwerp; 28 - 30 June 2017; 2017.

De Meester, J.; Langie, G.; De Cock, M.; Dehaene, W.; The process of designing STEM-integrating learning materials; EAPRIL2017; Hämeenlinna; 29 November - 1 December 2017; 2017.

De Meester, J.; Langie, G.; De Cock, M.; Dehaene, W.; Method for the Development of STEM-integrating Learning Materials; ESERA 2017; Dublin; 21-25 August 2017; 2017.

De Wit, M.; Reynaert, P.; Polymer Waveguides as an Alternative to Optical and Copper High- Speed Communication; IEEE Radio Frequency Integrated Circuits Symposium (RFIC), IEEE International Microwave Symposium (IMS); Honolulu, Honolulu; 4-6 June 20174-9 June 2017; 2017.

Knipprath, H.; Boeve-de-Pauw, J.; Ceuppens, S.; De Cock, M.; Dehaene, W.; De Loof, H.; De Meester, J.; Depaepe, F.; Goovaerts, L.; Hellinckx, L.; Struyf, A.; Thibaut, L.; van de Velde, D.; Van Petegem, P.; How social, natural and applied scientists collide and connect: a story about interdisciplinarity put into practice in Flemish schools; International Conference on Interdisciplinary Social Sciences; 26-28 July 2017; 2017.

Knipprath, H.; De Meester, J.; Boeve-de-Pauw, J.; Ceuppens, S.; De Cock, M.; Dehaene, W.; De Loof, H.; Depaepe, F.; Goovaerts, L.; Hellinckx, L.; Struyf, A.; Thibaut, L.; Van de Velde, D.; Van Petegem, P.; Integrated STEM makes a difference!; EAPRIL; Hämeenlinna; 29 November - 1 December 2017; 2017.

150

Levrie, K.; Jans, K.; Schepers, G.; Vos, R.; Mora Lopez, C.; Van Dorpe, P.; Lagae, L.; Van Hoof, C.; Van Aerschot, A.; Stakenborg, T.; Electrochemical site-specific functionalization for high resolution multi-target biosensors; Bio-sensing technology; Riva del Garda, Italy; 7-10 May 2017; 2017.

Levrie, K.; Jans, K.; Schepers, G.; Vos, R.; Van Dorpe, P.; Lagae, L.; Van Hoof, C.; Van Aerschot, A.; Stakenborg, T.; High Resolution Multiplexing for DNA Arrays using a Multi-Electrode Chip; International Conference on Solid State Devices and Materials; Sendai, Japan; 19-22 September 2017; 2017.

Malinowski, P.; Georgitzikis, E.; Maes, J.; Mamun, M.; Enzing, O.; Chen, K.; Hadipour, A.; Heremans, P.; Hens, Z.; Cheyns, D.; SWIR detection with thin-film photodetectors based on colloidal quantum dots; Freiburg Infrared Colloquium; Freiburg im Breisgau Germany; 2017-03-14; 2017.

Molderez, T.; Zhang, X.; Verhelst, M.; Rabaey, K.; An integrated sensor board for real-time optimization of the electrical settings of a microbial electrolysis cell; International Conference on Bio-Sensing Technology; Riva Del Garda; 7-10 May 2017; 2017.

Nica, I.; Deprez, M.; Ceyssens, F.; Puers, B.; Nuttin, B.; Aerts, J.; Theta and High Gamma Waves During Free Motion in a Cortical Lesion of the Rat Brain; IEEE EMBS Neural Engineering Conference; IEEE EMBS Neural Engineering Conference; Shanghai; 25-28 May 2017; 2017.

Prinzie, J.; Christiansen, J.; Moreira, P.; Steyaert, M.; Leroux, P.; A 2.56 GHz Radiation Hard Phase Locked Loop ASIC for High Speed Serial Communication Links; Topical Workshop on Electronics for Particle Physics; Santa Cruz, US; 11-14 September 2017; 2017.

Prinzie, J.; Christiansen, J.; Moreira, P.; Steyaert, M.; Leroux, P.; A 2.56 GHz SEU Radiation Hard LC-Tank VCO for High-Speed Communication Links in 65 nm CMOS Technology; Nuclear and Space Radiation Effects Conference; New Orleans, US; 18-21 July 2017; 2017.

Prinzie, J.; Christiansen, J.; Moreira, P.; Steyaert, M.; Leroux, P.; Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology; Advancements in Nuclear Instrumentation Measurement Methods and their Applications (ANIMMA); Liege, Belgium; 19-23 June 2017; 2017.

Schreurs, A.; Leenders, N.; Sabanov, V.; Van den Haute, C.; Welkenhuysen, M.; Hoffman, L.; Braeken, D.; Baekelandt, V.; Balschun, D.; Optogenetic inhibition of long-term potentiation in the mouse dentate gyrus; 12th National Congress of the Belgian Society for Neuroscience; Ghent Belgium; 2017-05-22; 2017.

Thibaut, L.; Knipprath, H.; Dehaene, W.; Depaepe, F.; Measuring teachers’ attitudes toward teaching integrated STEM: instrument development and validation; EARLI; Tampere; 29/08-02/09/2017; 2017.

Thibaut, L.; Knipprath, H.; Dehaene, W.; Depaepe, F.; Predictive factors of teachers’ attitudes toward teaching integrated STEM; ESERA; Dublin; 21-25 August 2017; 2017.

Thibaut, L.; Knipprath, H.; Dehaene, W.; Depaepe, F.; Thematic poster: How school context and other factors relate to teachers’ attitudes toward teaching integrated STEM; EARLI 2017, Book of Abstracts; Biennial meeting of the European Association for Research on Learning and Instruction (EARLI); Tampere, Finland; 29 August - 2 September 2017; 2017.

Van Thienen, N.; Reynaert, P.; Bin Khalid, F.; Dielacher, F.; Liebetrau, T.; Hammerschmidt, D.; Video Data Communication over Polymer Microwave Fiber; Infineon Innovations Days; Villach; 24-24 April 2017; 2017.

Wu, J.; Kim, W.; Rao, S.; Garello, K.; Couet, S.; Liu, E.; Swerts, J.; Kundu, S.; Souriau, L.; Yasin, F.; Crotti, D.; Kar, G.; Jochum, J.; Van Bael, M.; Van Houdt, J.; Groeseneken, G.; Impact of temperature on the switching behavior of scaled perpendicular magnetic tunnel junctions; 62nd Annual Conference on Magnetism and Magnetic Materials - MMM; Pittsburgh, PA USA; 2017-11-06; 2017.

Zhang, Y.; Reynaert, P.; Polymer Waveguides as an Alternative to Optical and Copper High-Speed Communication; IEEE International Microwave Symposium (IMS); Honolulu; 2017.

13.7 IMa-p (Meeting abstracts, presented at international professionally oriented conferences and symposia, published or not published in proceedings or journals)

Thibaut, L., Knipprath, H., Dehaene, W., Depaepe, F. (2017). Teachers’ attitudes and practices in integrated STEM education.

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Dept. Electrical Engineering - MICAS Kasteelpark Arenberg 10 - box 2443 3001 Leuven, Belgium tel +32 16 32 10 77 www.esat.kuleuven.be/micas