Memory Consistency - University of...
Transcript of Memory Consistency - University of...
![Page 1: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/1.jpg)
Memory ConsistencyA Crash Course
Brandon LuciaCSE 471
Myers
![Page 2: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/2.jpg)
Memory ConsistencyModel
“Defines the value a read operation may readat each point during the execution”
Informal Definition:
![Page 3: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/3.jpg)
Memory ConsistencyModel
“Defines the value a read operation may readat each point during the execution”
“Defines the set of legal observable orders of memoryoperations during an execution”
Informal Definition:
![Page 4: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/4.jpg)
Memory ConsistencyModel
“Defines the value a read operation may readat each point during the execution”
“Defines the set of legal observable orders of memoryoperations during an execution”
“Defines which reorderings of memory operationsare permitted”
Informal Definition:
![Page 5: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/5.jpg)
Review: Coherence
Wr X
Wr X
2 Invariants:
1) “One Writer orOne or More Readers”
2) “Reading X gets the value of the last write to X”Rd X
![Page 6: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/6.jpg)
Review: Coherence
2 Invariants:
1) “One Writer orOne or More Readers”
2) “Reading X gets the value of the last write to X”
Wr X
Wr X
Rd X
I wrote X last
Blue wrote X
last
![Page 7: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/7.jpg)
Without Coherence
Wr X Wr X
Rd X
Which X?!
Cache XCache X
(The coherence invariants prevent this from happening)
Processors can’t decide who wrote last. Green is hosed.
![Page 8: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/8.jpg)
Coherence is Ordering
Wr X
Wr X
Coherence defines the set of legal orders of accesses to a single memory location
Wr X
Wr XOR
![Page 9: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/9.jpg)
Consistency is Ordering
Wr X
Wr Y
Consistency defines the set of legal orders of accesses to multiple memory locations
Wr X
Wr YOR
![Page 10: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/10.jpg)
Expectation
X=1
r1=Y
Y=1
r2=X
ProgramInitially X == Y == 0
Which final values of {r1, r2} are possible?
![Page 11: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/11.jpg)
Sequential Consistency (SC)The simplest, most intuitive memory consistency model
Two Invariants to SC:
Instructions areexecuted in program
order
All processors agreeon a total order of
executed instructions
![Page 12: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/12.jpg)
The SC “Switch”
Execute
Wr X
Rd Y
Wr Y
Rd X
Rd X
Execution
![Page 13: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/13.jpg)
The SC “Switch”
Execute
Wr X
Rd Y
Wr Y
Rd X
Rd X
ExecutionWr X
![Page 14: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/14.jpg)
The SC “Switch”
Execute
Wr X
Rd Y
Wr Y
Rd X
Rd X
ExecutionWr XRd Y
![Page 15: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/15.jpg)
The SC “Switch”
Execute
Wr X
Rd Y
Wr Y
Rd X
Rd X
ExecutionWr XRd YWr Y
![Page 16: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/16.jpg)
The SC “Switch”
Execute
Wr X
Rd Y
Wr Y
Rd X
Rd X
ExecutionWr XRd YWr YRd X
![Page 17: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/17.jpg)
The SC “Switch”
Execute
Wr X
Rd Y
Wr Y
Rd X
Rd X
ExecutionWr XRd YWr YRd XRd X
![Page 18: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/18.jpg)
Why is SC Important?Who cares?.... You care!
Intuitive (SC)Wr XRd YWr YRd XRd X
Weird (not SC)
Wr XRd Y
Wr YRd XRd X
Wr X
Rd Y
Wr Y
Rd X
Rd X
SC prohibits all reordering of instructions (Invariant 1)
SC is how programmers think.
![Page 19: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/19.jpg)
Why are Instructions Reordered?And when does it matter anyway?
![Page 20: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/20.jpg)
Why are Instructions Reordered?
Optimization.
![Page 21: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/21.jpg)
Reordering #1: Write BuffersExecution
M M
CPU can read its write buffer, but not others’
Buffered writes eventually end up in coherent shared memory
Coherent
CPU CPU
Write BufferWrite Buffer
![Page 22: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/22.jpg)
Reordering #1: Write BuffersExecution
X=1
r1=Y
Y=1
r2=X
M M
Program
Is r1==r2==0a valid result?
Initially X == Y == 0
![Page 23: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/23.jpg)
Reordering #1: Write BuffersExecution
X=1
r1=Y
Y=1
r2=X
M M
Program
Is r1==r2==0a valid result?
Initially X == Y == 0
r1 == r2 == 0 is not SC, but it can happen with write buffers
![Page 24: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/24.jpg)
Reordering #1: Write Buffers
Execution
r1=Y
Y=1
r2=X
M M
ProgramInitially X == Y == 0
X=1
![Page 25: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/25.jpg)
Reordering #1: Write Buffers
Execution
r1=Y r2=X
M M
ProgramInitially X == Y == 0
X=1
Y=1
![Page 26: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/26.jpg)
Reordering #1: Write Buffers
Execution
r1=Y r2=X
M M
ProgramInitially X == Y == 0
X=1 Y=1
![Page 27: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/27.jpg)
Reordering #1: Write Buffers
Execution
r2=X
M M
ProgramInitially X == Y == 0
X=1 Y=1
r1=Y
![Page 28: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/28.jpg)
Reordering #1: Write Buffers
ExecutionM M
ProgramInitially X == Y == 0
X=1 Y=1
r1=Y r2=X
![Page 29: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/29.jpg)
Reordering #1: Write Buffers
ExecutionM M
ProgramInitially X == Y == 0
X=1 Y=1
r1=Y [r1 <- 0]
r2=X
![Page 30: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/30.jpg)
Reordering #1: Write Buffers
ExecutionM M
ProgramInitially X == Y == 0
X=1 Y=1
r2=X [r2 <- 0]r1=Y [r1 <- 0]
![Page 31: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/31.jpg)
Reordering #1: Write Buffers
ExecutionM M
ProgramInitially X == Y == 0
X=1Y=1
r2=X [r2 <- 0]r1=Y [r1 <- 0]
WBs let reads finish before older writes (Not SC!)
![Page 32: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/32.jpg)
Reordering #2: Write Combining
Coalescing Write Buffer
X=1
ProgramX,Z in same $ line
Y=1Z=1
4 word cache line
![Page 33: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/33.jpg)
Reordering #2: Write Combining
Coalescing Write Buffer
X=1
ProgramX,Z in same $ line
Y=1Z=1
X=1
![Page 34: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/34.jpg)
Reordering #2: Write Combining
Coalescing Write Buffer
X=1
ProgramX,Z in same $ line
Y=1Z=1
X=1
Y=1
![Page 35: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/35.jpg)
Reordering #2: Write Combining
Coalescing Write Buffer
X=1
ProgramX,Z in same $ line
Y=1Z=1
X=1
Y=1
Z=1
![Page 36: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/36.jpg)
Reordering #2: Write Combining
Coalescing Write BufferX=1
Y=1
Z=1
Coalescing Write BufferX=1
Y=1
Z=1Coalesce
Combining the write to X & Z saves bandwidth,but reorders Z=1 and Y=1
![Page 37: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/37.jpg)
Reordering #3: Compilers
for (i .. 100)X = 1 X = 0print x
X = 0
Compiler for (i .. 100)X = 1
X = 0print x
Been hoisted!
The compiler hoists the write out of the loop, permitting new (non-SC) results (e.g., “1 0 0 0 0 0 0...”)
![Page 38: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/38.jpg)
When is Reordering a Problem?
![Page 39: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/39.jpg)
When is Reordering a Problem?
When Executions Aren’t SC
![Page 40: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/40.jpg)
When is an Execution Not SC?
Execution
X=1Y=1
r2=X [r2 <- 0]r1=Y [r1 <- 0]
X=1
r1=Y
Y=1
r2=X
Happens-Before Graph
When a memory operation happens before itself
![Page 41: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/41.jpg)
When is an Execution Not SC?
Execution
X=1Y=1
r2=X [r2 <- 0]r1=Y [r1 <- 0]
X=1
r1=Y
Y=1
r2=X
Happens-Before Graph
Program Order HB Edge
When a memory operation happens before itself
![Page 42: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/42.jpg)
When is an Execution Not SC?
Execution
X=1Y=1
r2=X [r2 <- 0]r1=Y [r1 <- 0]
X=1
r1=Y
Y=1
r2=X
Happens-Before Graph
Program Order HB Edge
Causal Order HB Edge
When a memory operation happens before itself
![Page 43: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/43.jpg)
When is an Execution Not SC?
Execution
X=1Y=1
r2=X [r2 <- 0]r1=Y [r1 <- 0]
X=1
r1=Y
Y=1
r2=X
Happens-Before Graph
If there is a cycle in the happens-before graph, the execution is not SC
When a memory operation happens before itself
![Page 44: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/44.jpg)
So... are Computers Wrong?!
SC is how programmers think.
SC prohibits all reordering of instructions
WBs let reads finish before older writes
Combining writes saves bandwidth but reorders writes
![Page 45: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/45.jpg)
Relaxed Memory Consistency
Relaxed Memory Models permit reorderings, unlike SC
![Page 46: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/46.jpg)
x86-TSO (intel x86s)
“The Write Buffer Memory Model”
X=1
r1=Y
r1=Y
Total Store Order - loads may complete before older stores to different locations complete.
Relaxes W->R order
![Page 47: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/47.jpg)
PSO(SPARC)
“The Write Combining Memory Model”
X=1
Partial Store Order - loads and stores may complete before older stores to different locations complete.
Y=1Z=1
Z=1 Relaxes W->W order
![Page 48: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/48.jpg)
In General
X=1
Y=1Z=1
Z=1X=1
r1=Y
r1=Yr2=X
r1=Y
r1=Y
W->W
r2=X
Y=1
Y=1
R->R R->WW->R
Starting with PSO and relaxing R->R and R->W yields Weak Ordering or Release Consistency (alpha)
Depending on the implementation
![Page 49: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/49.jpg)
SC and Relaxed Consistency
SC is required for correctness and programmer sanity
Reordering is required* for performance
Goal: Ensure SC executions while permitting Relaxed Consistency reorderings
+
*Usually; the MIPS memory model is SC (surprising!)
![Page 50: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/50.jpg)
How to ensure SC, but permitreordering?
![Page 51: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/51.jpg)
Synchronization Prevents Reordering
X=1
r1=Y
r1=Y
Memory Fence
Fence implementation depends on reordering implementation
Memory fences are another type of synchronization
Reordering prevented
![Page 52: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/52.jpg)
Synchronization Prevents Reordering
X=1
r1=Y
r1=Y
Memory Fence
Fence implementation depends on reordering implementation
Memory fences are another type of synchronization
Reordering prevented
TSO: Stall reads until write buffer is empty
![Page 53: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/53.jpg)
Synchronization For Real Programmers
X=1
r1=Y
r1=Y
Unlock
Memory fences are wrapped up in locks, etc.
Reordering prevented
Direct use of fences possible, but inadvisable.USE A SYNCHRONIZATION LIBRARY
Lock
![Page 54: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/54.jpg)
Data Races
Y=1Unlock
Synchronization imposes happens-before on otherwise unordered operations
Data Race: Unordered operations to the same memory location, at least one a write
Lock
r1=YUnlock
LockHB Order: Data race prevented
![Page 55: Memory Consistency - University of Washingtoncourses.cs.washington.edu/courses/cse471/13sp/lectures/ConsistencySlides.pdf · Memory Consistency Model “Defines the value a read](https://reader034.fdocuments.us/reader034/viewer/2022042107/5e8631ac99078346ab3d7fd3/html5/thumbnails/55.jpg)
Memory Models across the System Stack
Language Compiler Architecture
Java/C++: SC for data-race-free programs
Conservative with reordering when d-r-f can’t
be proved
Usually very weak for max optimization
(lots of reordering)
Note: fences from “above” ensure SC