Meeting 14 - University of Michigan

Meeting 14

Summer 2009 Doing DSP Workshop

Today:

◮ Admin comments.

◮ PicoBlaze picocomputer.

Many graphics from Xilinx materials.

No student knows his subject: the most he knows is where and how to find out

the things he does not know. — Woodrow Wilson

Doing DSP Workshop – Summer 2009 Meeting 14 – /40 Thursday – June 18, 2009

Projects

Audio waveform synthesizer –

sine, square wave, triangle, etc.

◮ Darin Rajabian

OFDM.

◮ Yu Wang

Motor speed control lab demon

stration.

◮ Zharori Cong

◮ B.K. Kim

Remote camera using ZigBee.

◮ James Kim

◮ Jordan Adams

Digital Filter Study.

◮ Vindhya Reddy

◮ Joanna Widjaja

Ultrasonic Vision Aide.

◮ Ronald Deang

Not cast in concrete.


Suggested Project Phases

◮ Start up.

◮ Basically define the task, locate useful resources, and verbalize

a possible plan of attack.

◮ Initial Start.

◮ Develop the initial proposal. If applicable, do MATLAB

simulation. Identify required parts and other resources needed

to be purchased. Should have a reasonably clear understanding

of what is to be done and how. Set up goals and time line.

◮ Work in earnest.

◮ Program, build, debug. Repeat.

◮ Completion. Sometime in August.

◮ Demonstration to the workshop.◮ Poster.

Feel free to use ChihWei and myself as resources.


Labs slipping

I hope to post Exercise 5 later this evening. Sorry about the delay.

I’ve not started on Exercise 6. I do plan to create it.

As is the case for the entire workshop, participation is voluntary.

You get to be the drummer and march accordingly. ChihWei and I are

working to set a context, provide access to PCs and FPGA/Piccolos and

provide support. How this is exploited is up to the workshop

participants. This is NOT a course.

For those who would like course credit for a project, a bit more structure

will be needed.

To do or not to do, and when. That’s your choice.


Updated tentative schedule

Week of June 15: Exercise 5, controlSTICK ADC, DAC, xfer meas..

Tuesday – FFTs.

Thursday – Xilinx 8bit PicoBlaze microcomputer (VHDL).

Week of June 22: Exercise 6, realtime FFT and waveform evaluation.

Tuesday – ChihWei will meet with workshop. (KM away.)

Thursday – ChihWei will meet with workshop. (KM away.)

Weeks following —

Lecture and lab complete, focus on projects.


Lab upgrade

The floors in EECS 4341 were stripped Tuesday night and waxed

Wednesday night.

Next week the tables will be upgraded. We will be clearing the current

tables Friday. The lab will not be operational until sometime next week.

An email message will be sent to the Workshop email list when the lab is

back to operational mode.

Sorry about the inconvenience. The opportunity to upgrade the student

work stations came up suddenly and unexpectedly.


Today’s presentation

Ken Chapman’s (Xilinx) PicoBlaze microcomputer, KCPSM3.

◮ Overview

◮ Instruction set

◮ Programming examples

◮ Adding hardware

◮ Interface examples

◮ Updating the program ROM without rebuilding

www.xilinx.com/ipcenter/processor_central/picoblaze/picoblaze_user_resources.htm

Much of the material presented here is from Xilinx documents.


www.xilinx.com/ipcenter/processor_central/picoblaze/picoblaze_user_resources.htm

Xilinx PicoBlaze web information


What is a PicoBlaze?

Free, small footprint, 8bit microcomputer for S3x and VertexX.

◮ Uses only 96 logic slices and one block RAM.

◮ Instruction store of 1024 18bit instructions.

◮ All instructions execute in two clock tics.

◮ S3 max execution speed is about 44 MIPS.

◮ 16 8bit byte general purpose registers.

◮ 64 internal scratch pad registers.

◮ 128 input and output addresses.

◮ 31 level call/return stack.

◮ small instruction set (RISC?).

◮ Supplied as VHDL code!!!!!!!!

◮ Generally programmed in assembly.

◮ Variants are used depending upon Xilinx device family.


Review: Slice counts

Device gates CLBs slices BRAMs used

XC3S200 200K 480 1920 12 bottom S3SB and NEXYS

XC3S1000 1000K 1920 7680 24 top S3SB and NEXYS

XC3S100E 100K 240 960 4 BASYS

XC3S500E 500K 1164 4656 20 S3E SB & NEXYS2

XC2VP30 — 3424 13696 136 VertexII Pro XUP board

Basic PicoBlaze uses: 96 slices and one BRAM.

Several PicoBlazes can be fit into a single FPGA.


PicoBlaze basic block diagram

From Xilinx PicoBlaze brochure.

This is the KCPSM3 version. Variants exist for use on earlier

Xilinx devices.


PicoBlaze instruction set

From Xilinx PicoBlaze brochure.


The PicoBlaze programming support

◮ The Chapman assembler (free) is slightly “nontraditional”.

◮ The Mediatronix assembler (free) is more “traditional” and

appears to being supported.

◮ A C compiler appears to be available.

◮ Programming the PicoBlaze requires thinking small.

◮ One of the first things I did was to write signed 16bit

decimal I/O support.

◮ Support exists to allow downloading the program ROM via

the JTAG interface without rebuilding the entire VHDL. This

might only work with the parallel JTAG cable.


Detailed PicoBlaze block diagram

From Xilinx KCPSM3 manual.


KCPSM3 VHDL block

From KCPSM3 manual.

processor: kcpsm3port map( address => address,

instruction => instruction,port_id => port_id,

write_strobe => write_strobe,out_port => out_port,

read_strobe => read_strobe,in_port => in_port,

interrupt => interrupt,interrupt_ack => interrupt_ack,

reset => ’0’,clk => clk);

program_rom: monitorport map( address => address,

instruction => instruction,-- proc_reset => processor_reset, --additional port for JTAG loader version

clk => clk);


Where to get the PicoBlaze?

From the web, www.xilinx.com/picoblaze .

The Spartan3 Starter Board comes with a board test in the

onboard flash rom.

A good starting point (the one I used) to learn about the

PicoBlaze and the Starter Board is the Clock and PCB monitor.

The included PDF writeup is terse but highly informative. The

source code, monitor.psm illustrates how to program the

PicoBlaze. The included VHDL code illustrates how to interface

to the PicoBlaze.

This and more can be found at

www.xilinx.com/products/boards/DO-SPAR3-DK/reference_designs.htm

A treasure trove!


www.xilinx.com/picoblaze

www.xilinx.com/products/boards/DO-SPAR3-DK/reference_designs.htm

The Clock and PCB reference design

◮ Created by Ken Chapman.

◮ Illustrates interfacing the Spartan 3 Starter Board devices to

the PicoBlaze using VHDL.

◮ Illustrates programming of the PicoBlaze.

◮ Supports external communication between a PC terminal

emulator and the PicoBlaze using a UART (VHDL included).

◮ Total system size: 267 slices.

KCPSM3

Program(BRAM)

Interface Logic SRAM 256K×16

SRAM 256K×16

PC RS232

Config PROMLEDs

Buttons

Switches

XC3S200

From Xilinx PCB monitor documentation.


Clock and PCB monitor design

PicoBlaze Digital Clock and Board Monitor 12

Block Diagram

FIFO

16 Byte

UART Tx

[17:16]

*RAM address [17:0]

[15:8]

[7:0]

* Common to bothRAM devices

*WE*OECEUBLB

IC10

CEUBLB

IC11

Port14

Port12

Port11

Port80

Port60

RAM enables

Data [15:0]

*OE

[7:0]

[15:8] IC1016

8

Ain[15:0]

Data [15:0]

*OE

[7:0]

[15:8] IC1116

PortA0

LED [7:0]

PortC0

UART Rx

16×8 Dual Port RAM

PortsE0-E3

20-bitcounter

2 MSBs

A

decode

D

7-SegmentDisplay

dp,g,f,e,d,c,b,a

AN0AN1AN2

AN3

KCPSM3

Program(BRAM)

PROMReader CCLK

OE

DIN

Ain[15:0]

PROMin[7:0]

Bin[15:0]

PROMin[7:0]

Port40

PROMstatus

Tx_status

FIFO16 Byte

Rx_status

Rx_Data

Tx_status

PROMstatus[15:8]

[7:0]

LBa

Bin[15:0]

[15:8]

[7:0]

LBb

CEa

Port 04

Port 00

Port 01

Port 03BUTTONS [3:0]

Port 02SWITCHES [7:0]

RAM_Data

Port 05

1 s timer



Fabric usage for 200K Spartan 3

PicoBlaze Digital Clock and Board Monitor 4

Design ResourcesThe design uses one Block RAM and 220 Logic slices. This is less than 12% of the XC3S200 device resources.

Floorplanner view FPGA Editor view

Notes: Constraints were used to stop the logic being spread all over the device! Such constraints are only required to make nice pictures!CLB Packing Factor was set to 1 (default value is 100) to achieve 220 slices.



How have I used the KCPSM3?

◮ Created personal basic version of monitor.psm.

◮ Reorganized the code somewhat (style issues).

◮ Added 16bit decimal input and output support.

◮ Some projects:

◮ First project was a test for a PN sequence correlator

generating a plot of its output using a Tektronix 4010

terminal emulator.◮ Used to test VHDL blocks.◮ Used to interface ODFM synchronization subsystem VHDL

block to MATLAB for testing. Moved MATLAB components

into VHDL a unit at a time and tested. Coprocessing or

cooperation.◮ Implementing a Tektronix 4010 emulator with XVGA display.

Maps 4010 command strings to hardware commands. Works

with RS232 or McBSP link.


Basic PicoBlaze monitor (my modified version)

◮ User command I/O via serial I/O (UART/FIFO).

16 byte command line buffer.

command line editing.

◮ Commands dispatched using table.

◮ Signed 16bit decimal in/out support.

◮ Hex output support.

◮ Can use McBSP link for input in place of RS232. McBSP link

is in preliminary stage of development.


Monitor start and command line input

cold_start:LOAD areg,00 ; clear areg;Start of the main program loop.;A prompt is transmitted to the UART transmitter and then;a command can be entered and interpreted.;load page_bits,40 ; instead start terminal runningjump em_idle;call send_ID

prompt_input:CALL send_prompt ; Prompt stringCALL receive_string ; obtain input string;Parse the string and perform actions as requiredCALL fetch_char_from_memoryCOMPARE areg, character_CR ; carriage return does nothingJUMP Z, prompt_inputCOMPARE areg, character_TJUMP Z, test_tem ; draw test patternCOMPARE areg, character_DJUMP Z, set_display ; set display pageCOMPARE areg, character_WJUMP Z, set_work ; set working pageCOMPARE areg, character_CJUMP Z, clear_work ; clear working page;trap other command starts here

bad_input_command:CALL send_Syntax_Error ;no valid commandJUMP prompt_input


Programming flow (Xilinx)

Very basic, no GUI, use an editor of choice. Command line executed.

design.vhd

Synthesis

PAR

Download Complete

Design(JTAG)

Assembler

<filename.psm>

ROM_form.vhd<filename.vhd>

iMPACT

The PSM program is assembled and the resulting

VHDL (or Verilog) file is included in the design.

This is then processed through the normal ISE tools

and used to configure the device via a JTAG

download cable.

From JTAG loader quick guide.


Mediatronix pBlaze IDE

It’s FREE!!!

Available at: http://www.mediatronix.com/pBlazeIDE.htm .

“pBlaze IDE is an Integrated Development Environment dedicated to the

fine KCPSM soft core, of Ken Chapman of Xilinx, now known as PicoBlazeZ

. This tool is still in beta and will probably stay there. Please let me know

if you find it useful. Also let me know of bugs and enhancements. There

are still many known issues, but the resulting code has been used many

times with success. The tool is based on the TSynEdit component and is

further developed with Delphi. It allows you to edit, format, assemble and

debug your KCPSM/PicoBlaze code. The emulation of I/O devices is still

in its infancy and needs more elaboration.

The assembly directives and opcodes have been adapted quite a bit to be

similar to mainstream assembly code. For debugging and emulation of

I/O some additional directives have been added.” From the Mediatronix web site.

Current version is: 3.6. Beta version is 3.74.


http://www.mediatronix.com/pBlazeIDE.htm

pBlaze IDE screen shot

From Mediatronix web site.


JTAG update of PicoBlaze program ROM

JTAG Loader - Quick Guide - 8 © 2004 Xilinx, Inc.All Rights Reserved

JTAG Loader ProgramsJTAG Loader Programs

Ken Chapman

(Xilinx UK) 2003

design.vhd

Synthesis

PAR

Download Complete

Design(JTAG)

Assembler

<filename.psm>

Enhanced

ROM_form.vhd

<filename.vhd>

iMPACT

hex2svfsetup

Describe JTAG chain

(run once only)

svf2xsvf -d -i <new_prog.svf> -o <new_prog.xsvf>

hex2svf <new_prog.hex> <new_prog.svf>

Assembler

<new_prog.psm>

<new_prog.hex>

playxsvf <new_prog.xsvf>

Ensure IMACT is closed before using ‘playxsvf’.

Once the new design is configured into the device, a new set of programs can be used to rapidly

change the PicoBlaze program.

From JTAG loader quick guide.


Comments on JTAG downloading

I believe that this only works with the Parallel JTAG

programming cable.

Use a batch file (supplied). Works well.

Allows ready modification of PicoBlaze block RAM instruction

memory without having to rebuild the entire VHDL project.

With care, I think that one can download new BRAM contents,

on the fly, to any RAM block using the JTAG interface.


Some comments and my usage

◮ 1024 instruction limit,

◮ available RAM is 64 bytes,

◮ 16 arithmetic registers.

◮ Used to develop the stand alone XVGA line drawing and

character generation VHDL modules.

◮ Can be interfaced to other processors via SPI, McBSP, or

UART protocols. Can also be interfaced Ethernet, USB.


Register discipline

;Special Register definitions -- there are 16 available;NAMEREG s0, areg ; a registerNAMEREG s1, breg ; b registerNAMEREG s2, temp ; highly volatile!!!!NAMEREG s3, str_ptr ; string pointer;;definitions of 16 bit AC and 16 bit MQ for extended precision arithmetic;NAMEREG s4, achNAMEREG s5, aclNAMEREG s6, mqhNAMEREG s7, mql;;Tektronix 4010 support;NAMEREG s8, hiyNAMEREG s9, loyNAMEREG sa, hixNAMEREG sb, loxNAMEREG sc, page_bits ; top 4 bits used to hold page bits;;; Registers sD thru sF are unassigned.


Scratch pad register discipline

;Scratch Pad Memory Locations -- there are 64 available;CONSTANT UART_temp, 00 ; temp used by UART supportCONSTANT LED_status, 01 ; Status of the 8 simple LEDs;; UART input and output routines were modified to only modify the contents of; the areg. No other (non-dedicated) registers are used. This greatly reduces; worries when doing UART input and output.;; The 16-bit singed input and output routines use registers as noted.;; UART character strings will be stored in scratch pad memory ending in carriage; A string can be up to 16 characters with the start location defined by this constant.;CONSTANT string_start, 30 ; 48 in decimal..using last 16 locationsCONSTANT string_limit, 40 ; string start+size of string buffer;


Print 16-bit signed value support

; print 16-bit signed integer .. value in ach, acl;; contents of areg, breg, temp, ach/l and mqh/l are modified;print_16bit:

LOAD temp,00 ; clear print switchesTEST ach,80 ; check sign bitJUMP NC, pr16a ; jump if positiveOR temp,02 ; note value was negativeXOR acl,FF ; make one’s complementXOR ach,FFADD acl,01 ; and add 1 to make two’s complementADDCY ach,00

pr16a:LOAD mqh,27 ; do 10000’s digitLOAD mql,10CALL print_digitLOAD mqh,03 ; do 1000’s digitLOAD mql,E8CALL print_digitLOAD mqh,00 ; do 100’s digitLOAD mql,64CALL print_digitLOAD mql,0A ; do 10’s digitCALL print_digitLOAD mql,01 ; do 1’s digitCALL print_digitRETURN


Print digit support

print_digit:LOAD areg,00 ; will form digit in areg

get_la:SUB acl,mql ; subtract mq from acSUBCY ach,mqhJUMP C, get_lb ; jump if result is negativeADD areg,01 ; otherwise add one to digit being formedJUMP get_la ; and loop

get_lb:ADD acl,mql ; undo the last subtractADDCY ach,mqhADD areg,30 ; make digit ASCIITEST temp,01 ; see if printing is activeJUMP C,get_lx ; jump if it isCOMPARE mql,01 ; see if last digitJUMP Z,get_lc ; if so print 0 as wellCOMPARE areg,30 ; check for 0 digitJUMP NZ,get_lc ; jump if it isn’t a leading zeroLOAD areg,character_spaceJUMP get_lx ; replace leading 0’s with spaces

get_lc: ; found a non-zero leading digitOR temp,01 ; note thisLOAD breg,areg ; save current digitLOAD areg,character_spaceTEST temp,02 ; see if negative sign is neededJUMP NC,get_ld ; jump if value is positiveADD areg,0D ; make space into minus

get_ld:CALL send_to_UARTLOAD areg,breg ; print first non leading digit

get_lx:CALL send_to_UARTRETURN


Signed 16-bit decimal input part 1.

; input 16-bit signed decimal value;; contents of areg, temp, ach/l and mqh/l are modified;; does not handle 32768..indeed, no overflow protection so ever!;input_decimal:

CALL fetch_char_from_memory ; get first characterCOMPARE areg,character_spaceJUMP Z,input_decimal ; skip leading spacesLOAD acl,00 ; clear accumulator lowLOAD ach,00 ; clear accumulator highLOAD temp,00 ; clear sign memoryCOMPARE areg,character_minus ; test for a minusJUMP NZ,in_nlb ; jump if didn’t get minus signOR temp,02 ; note a minus sign

in_nla:


Signed 16-bit decimal input part 2

in_nla:CALL fetch_char_from_memory ; main loop start

in_nlb:SUB areg,character_0 ; subtract asciiJUMP C,in_done ; below number range, end upCOMPARE areg,0AJUMP NC,in_done ; above number range, end upLOAD mql,acl ; save ac valueLOAD mqh,achSL0 acl ; multiply ac by 2SLA achSL0 acl ; now by 4SLA achADD acl,mql ; add start to get times 5ADDCY ach,mqhSL0 acl ; multiply by 2 again to get 10xSLA achADD acl,areg ; add digit valueADDCY ach,00JUMP in_nla ; and loop

in_done:TEST temp,02 ; test to see if leading minusJUMP Z,in_nlx ; jump if notXOR acl,FF ; form one’s complementXOR ach,FFADD acl,01 ; add one to form two’s complementADDCY ach,00

in_nlx:RETURN


McBSP serial input

;Read one character from the UART;;Character read will be returned in areg.;;The routine first tests the receiver FIFO buffer to see if data is present.;If the FIFO is empty, the routine waits until there is a character to read.;;Returns character in areg. No other registers affected.;

read_from_UART:INPUT areg, UART_status_portTEST areg, Mc0_data_presentJUMP NZ, read_characterJUMP read_from_UART

read_character:INPUT areg, 03OUTPUT areg, load_ledsreturn

;read_from_UART:; INPUT areg, UART_status_port ;test Rx_FIFO buffer; TEST areg, rx_data_present; JUMP NZ, read_character; JUMP read_from_UART;read_character:; INPUT areg, UART_read_port ;read from FIFO; RETURN


Interfacing VHDL modules

◮ Look at how Chapman did it. He did both input and output.

◮ I expanded port decoding. Chapman saved gates. Generally

a good idea not to be wasteful. I simplified and increased

the number of decoded port addresses.

◮ There seems to be a tendency to NOT comment VHDL code.

Not good.


Sliding correlator example

SR125 SR124 SR123 SR2 SR1 SR0

sample fromexternal source

16

32 bit-serial subtract units

16 bit-serial add units




1 bit-serial add unit

output

16

Subtract/ add networkfor

imaginary part

sample fromexternal source

16

16

control

load

done

0only even stages are connected to subtract unit

Bit serial sliding pn-correlator unit. Cut 1, rev 0 12July2005

18-bit values producedthen rounded to 16-bits


Example test display


Testing/debugging

Not necessary if you don’t make any mistakes.

Failing that:

◮ Don’t try to do everything all at once.

◮ Start simple, test, add complexity—bootstrap.

◮ Sort of divided into static vs dynamic.

◮ Often use PicoBlaze to exercise complex entities.

◮ For VHDL, can bring signals to connector.

◮ Can use Xilinx/MicroSim emulators to test.

◮ Xilinx ChipScope (I’m not familiar with this.)

◮ PicoBlaze allows “printf style” debugging.


Co-operation (co-processing)

Need a link between a DSK and or PC and an FPGA.

Some locally relevant choices:

◮ RS232.

◮ Parallel port.

◮ Ethernet.

◮ USB.

◮ High speed bit serial (SPI or McBSP).


Meeting 14 - University of Michigan

Documents

Transcript of Meeting 14 - University of Michigan