McCorquodale et a]. (45) Date of Patent: *Apr. 12,...

(12) United States Patent McCorquodale et a].

US007924110B2

US 7,924,110 B2 *Apr. 12, 2011

(10) Patent N0.: (45) Date of Patent:

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MONOLITHIC CLOCK GENERATOR AND TIMING/FREQUENCY REFERENCE

Inventors: Michael Shannon McCorquodale, Ann

331/117 R, 177 PE, 117 D, 173,175, 177 R, 177 V, DIG. 2, 176

See application ?le for complete search history.

Arbor, MI (US); Scott Michael Pernia, (56) References Cited Pinckney, MI (U S); Amar Sarbbasesh Basu, Troy, MI (Us) US. PATENT DOCUMENTS

4,847,876 A * 7/1989 Baumbach et a1. ......... .. 375/364

Assignee: Integrated Device Technology, Inc., 5,699,024 A * 12/1997 Manlove et a1. ..... .. 331/111 San Jose CA (Us) 6,154,095 A * 11/2000 Shigemori et a1. . 331/16

’ 6,356,161 B1* 3/2002 Nolan et a1. .. 331/176 . . . . . 7,116,183 B2* 10/2006 Wu ............................. .. 331/176

Not1ce: Subject' to any d1scla1mer, the term ofth1s 7,227,423 B2 * 6/2007 Mccorquodale et a1‘ 33l/179 patent 1s extended or adjusted under 35 2001/0020875 A1* 9/2001 Jansson ......................... .. 331/44

U.S.C. 154(b) by 63 days. * Cited by examiner

This patent is subject to a terminal dis- _ _ _ _ Claimer~ Primary Examiner * Davld M15

(74) Attorney, Agent, or Firm * Myers Bigel Sibley & Appl. N0.: 12/435,269 SaJOVe/C, P-A

Filed: May 4, 2009 (57) ABSTRACT In various embodiments, the invention provides a clock gen

Pl‘ior PllblicatiOIl Data erator and/or a timing and frequency reference, With multiple Us 2010/0019856 A1 Jan 28 2010 operating modes, such poWer conservation, clock, reference,

Related US. Application Data

Continuation of application No. 11/796,821, ?led on Apr. 28, 2007, noW Pat. No. 7,548,132, Which is a continuation of application No. 11/084,962, ?led on Mar. 21, 2005, noW Pat. No. 7,227,423.

Provisional application No. 60/555,193, ?led on Mar. 22, 2004.

Int. Cl. H03B 5/12 (2006.01) H03L 1/02 (2006.01) US. Cl. ................. .. 331/179; 331/117 FE; 331/176

Field of Classi?cation Search ................ .. 331/1 A,

331/2, 8, 10, 11, 16418, 25, 36 c, 36 L, 57,

and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a ?rst signal having a resonant frequency; an ampli?er; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the ?rst signal having the resonant frequency into a plurality of sec ond signals having a corresponding plurality of frequencies substantially equal to or loWer than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals. The output signal may be provided in any of various forms, such as differential or single-ended, and substantially square-Wave or sinusoidal.

37 Claims, 17 Drawing Sheets

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US. Patent Apr. 12, 2011 Sheet 1 0f 17 US 7,924,110 B2

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CURRENT INJECTION NAVEFORM

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US 7,924,110 B2

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U. S. Patent Apr. 12, 2011 Sheet 16 0f 17 US 7,924,110 B2

1005 @- 1005 Q 1005 Q 0

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US. Patent Apr. 12, 2011 Sheet 17 0f 17

FIG. 19

@122"

US 7,924,110 B2

GENERATE A RESONANT SIGNAL HAVING A RESONANT FREQUENCY

/ 1225

ADJUST THE RESONANT FREQUENCY IN RESPONSE TO TEMPERATURE

/12ao

T ADJUST THE RESONANT FREQUENCY IN

RESPONSE TO FABRICATION PROCESS VARIATION / 1235

DIVIDE THE RESONANT SIGNAL HAVING THE RESONANT FREQUENCY INTO A PLURALITY OF SECOND SIGNALS HAVING A PLURALITY OF FREQUENCIES SUBSTANTIALLY EQUAL TO OR

LOWER THAN THE RESONANT FREQUENCY

/ 1240

T SELECT AN OUTPUT SIGNAL FROM

THE PLURALITY OF SECOND SIGNALS _/ 1245

CONVERT DIFFERENTIAL SINUSOIDAL SIGNALTS) TO SINGLE-ENDED, SUBSTANTIALLY SQUARE

WAVE SIGNALS, HAVING SUBSTANTIALLY EQUAL HIGH AND LOW DUTY CYCLES, AS NEEDED

/1250

T SELECT AN OPERATING MODE OF A PLURALITY OF OPERATING MODES, INCLUDING CLOCK, TIMING/FREQUENCY REFERENCE, POWER

CONSERVATION, AND PULSE MODE

_/ 1255

1250 REFERENCE MODE?

SYNCHRONIZE A THIRD SIGNAL IN RESPONSE TO THE OUTPUT SIGNAL 3 51270

US 7,924,110 B2 1

MONOLITHIC CLOCK GENERATOR AND TIMING/FREQUENCY REFERENCE

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims priority to US. patent application Ser. No. 11/796,821, ?led Apr. 28, 2007, inventors Michael Shannon McCorquodale, Scott Michael Pernia, and Amar Sarbbaseh Basu, entitled “Mono lithic Clock Generator and Timing/Frequency Reference” (the “?rst related application”), Which is commonly assigned hereWith, the contents of Which are incorporated herein by reference, and With priority claimed for all commonly dis closed subject matter, Which further is a continuation of and claims priority to US. patent application Ser. No. 11/084, 962, ?led Mar. 21, 2005, now US. Pat. No. 7,227,423 issued Jun. 5, 2007, inventors Michael Shannon McCorquodale, Scott Michael Pernia, and Amar Sarbbaseh Basu, entitled “Monolithic Clock Generator and Timing/ Frequency Refer ence” (the “second related application”), Which is commonly assigned hereWith, the contents of Which are incorporated herein by reference, and With priority claimed for all com monly disclosed subject matter, Which further claims priority to US. Provisional Patent Application Ser. No. 60/555,193, ?led Mar. 22, 2004, inventor Michael Shannon McCor quodale, entitled “Monolithic and Top-DoWn Clock Synthe sis With Micromachined Radio Frequency Reference” (the “third related application”), Which is commonly assigned hereWith, the contents of Which are incorporated herein by reference, and With priority claimed for all commonly dis closed subject matter.

This application is also related to and claims priority to US. patent application Ser. No. 11/085,372, ?led Mar. 21, 2005, now US. Pat. No. 7,227,424 issued Jun. 5,2007, inven tors Michael Shannon McCorquodale and Scott Michael Per nia, entitled “Transconductance and Current Modulation for Resonant Frequency Control and Selection” (the “fourth related application”), Which is commonly assigned hereWith, the contents of Which are incorporated herein by reference, and With priority claimed for all commonly disclosed subject matter, and Which further claims priority to the third related application.

FIELD OF THE INVENTION

The present invention, in general, relates to oscillation or clocking signal generation, and more particularly, relates to a clock signal generator and timing/ frequency reference Which is free-running, self-referenced, accurate over fabrication process, voltage and temperature, has loW jitter, and Which may be monolithically integrated With other circuitry to form a single integrated circuit.

BACKGROUND OF THE INVENTION

Accurate clock generators or timing references have gen erally relied upon crystal oscillators, such as quartz oscilla tors, Which provide a mechanical, resonant vibration at a particular frequency. The dif?culty With such crystal oscilla tors is that they cannot be fabricated as part of the same integrated circuit (“IC”) driven by their clock signal. For example, microprocessors such as the Intel Pentium proces sor require a separate clock IC. As a consequence, virtually every circuit requiring an accurate clock signal requires an off-chip clock generator.

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2 There are several consequences for such non-integrated

solutions. For example, because such a processor must be connected through outside circuitry (such as on a printed circuit board (PCB)), poWer dissipation is comparatively increased. In applications Which rely on a ?nite poWer supply, such as battery poWer in mobile communications, such addi tional poWer dissipation is detrimental.

In addition, such non-integrated solutions, by requiring an additional IC, increase space and area requirements, Whether on the PCB or Within the ?nished product, Which is also detrimental in mobile environments. Moreover, such addi tional components increase manufacturing and production costs, as an additional IC must be fabricated and assembled With the primary circuitry (such as a microprocessor).

Other clock generators Which have been produced as inte grated circuits With other circuits are generally not very accu rate, particularly over fabrication process, voltage, and tem perature (“PVT”) variations. For example, ring, relaxation and phase shift oscillators may provide a clock signal suitable for some loW-sensitivity applications, but have been inca pable of providing the higher accuracy required in more sophisticated electronics, such as in applications requiring signi?cant processing capability. In addition, these clock gen erators or oscillators often exhibit considerable frequency drift, jitter, have a comparatively loW Q-value, and are subject to other distortions from noise and other interference. As a consequence, a need remains for a clock generator or

timing reference Which may be integrated monolithically With other circuitry, as a single IC, and Which is highly accu rate over PVT variations. Such a clock generator or timing reference should be free-running and self-referencing, and should not require locking or referencing to another reference signal. Such as clock generator or timing reference should exhibit minimal frequency drift and have comparatively loW jitter, and should be suitable for applications requiring a highly accurate system clock. Such a clock generator or tim ing reference should also provide multiple operating modes, including a clock mode, a reference mode, a poWer conser vation mode, and a pulsed mode.

SUMMARY OF THE INVENTION

In various exemplary embodiments, the invention provides a loW-jitter, free-running and self-referencing clock generator and/or a timing and frequency reference Which is highly accurate over PVT variations and Which can be integrated monolithically With other circuitry, to form a singular inte grated circuit. No separate reference oscillator is required. The various exemplary embodiments of the invention include features for highly accurate frequency generation over fabri cation process, voltage, and temperature (“PVT”) variations. These features include frequency tuning and selection, and compensation for frequency variations Which may be caused due to temperature and/ or voltage ?uctuations and fabrication process variations.

In addition, the various exemplary embodiments of the invention provide a clock generator and/or a timing and fre quency reference having multiple operating modes, including modes such as a poWer conservation mode, a clock mode, a reference mode, and a pulsed mode. In addition, the various embodiments provide multiple output signals at different fre quencies, and provide loW-latency and glitch-free sWitching betWeen these various signals.

Signi?cantly, the various exemplary embodiments of the invention generate a signi?cantly and comparatively high frequency, such as in the hundreds of MHZ and GHZ range, Which is then divided to a plurality of loWer frequencies. Each

US 7,924,110 B2 3

such division by “N” (a rational number, as a ratio of integers) results in a signi?cant noise reduction, With phase noise reduced by N and noise poWer reduced by N2. As a conse quence, the various exemplary embodiments of the invention result in signi?cantly less jitter than available With other oscillators, such as ring oscillators.

The various apparatus embodiments include a resonator, an ampli?er, and a frequency controller, Which may include various components or modules such as a temperature com pensator, a process variation compensator, a voltage isolator, a frequency divider, and a frequency selector. The resonator provides a ?rst signal having a resonant frequency. A tem perature compensator adjusts the resonant frequency in response to temperature, and the process variation compen sator adjusts the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider to divide the ?rst signal having the resonant frequency into a plurality of second sig nals having a corresponding plurality of frequencies sub stan tially equal to or loWer than the resonant frequency; and a frequency selector to provide an output signal from the plu rality of second signals. The frequency selector may further include a glitch-suppressor. The output signal may be pro vided in any of various forms, such as differential or single ended, and substantially square-Wave or sinusoidal.

The present invention may also include a mode selector coupled to the frequency selector, Wherein the mode selector is adapted to provide a plurality of operating modes, Which may be selected from a group comprising a clock mode, a timing and frequency reference mode, a poWer conservation mode, and a pulse mode.

For a reference mode, the invention may also include a synchronization circuit coupled to the mode selector; and a controlled oscillator coupled to the synchronization circuit and adapted to provide a third signal; Wherein in the timing and reference mode, the mode selector is further adapted to couple the output signal to the synchroniZation circuit to control timing and frequency of the third signal. Such a syn chroniZation circuit may be a delay-locked loop, a phase locked loop, or an injection locking circuit.

These and additional embodiments are discussed in greater detail beloW. Numerous other advantages and features of the present invention Will become readily apparent from the fol loWing detailed description of the invention and the embodi ments thereof, from the claims and from the accompanying draWings.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features and advantages of the present inven tion Will be more readily appreciated upon reference to the folloWing disclosure When considered in conjunction With the accompanying draWings and examples Which form a portion of the speci?cation, in Which:

FIG. 1 is a block diagram illustrating an exemplary system embodiment in accordance With the teachings of the present invention.

FIG. 2 is a block diagram illustrating a ?rst exemplary apparatus embodiment in accordance With the teachings of the present invention.

FIG. 3 is a block diagram illustrating a second exemplary apparatus embodiment in accordance With the teachings of the present invention.

FIG. 4 is a high-level schematic and block diagram illus trating exemplary frequency controller, oscillator and fre quency calibration embodiments in accordance With the teachings of the present invention.

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4 FIG. 5A is an exemplary graph illustrating oscillator volt

age Waveform (frequency) distortion With current injection into an oscillator.

FIG. 5B is an exemplary graph illustrating oscillator volt age Waveform (frequency) distortion or variation With tem perature.

FIG. 5C is an exemplary graph illustrating oscillator fre quency as a function of the transconductance of a sustaining ampli?er.

FIG. 6 is a circuit diagram illustrating ?rst exemplary nega tive transconductance ampli?er, temperature-responsive cur rent generator (I(T)), and LC tank oscillator embodiments in accordance With the teachings of the present invention.

FIG. 7A is a circuit diagram illustrating an exemplary temperature-responsive CTAT current generator in accor dance With the teachings of the present invention.

FIG. 7B is a circuit diagram illustrating an exemplary temperature-responsive PTAT current generator in accor dance With the teachings of the present invention.

FIG. 7C is a circuit diagram illustrating an exemplary temperature-responsive PTAT2 current generator in accor dance With the teachings of the present invention.

FIG. 7D is a circuit diagram illustrating an exemplary temperature-responsive current generator, With selected CTAT, PTAT, and PTAT2 con?gurations, in accordance With the teachings of the present invention.

FIG. 8 is a circuit and block diagram illustrating second exemplary negative transconductance ampli?er, temperature responsive current generator (I(T)), and LC tank oscillator embodiments in accordance With the teachings of the present invention.

FIG. 9 is a circuit diagram illustrating an exemplary con trolled capacitor module utiliZed in a frequency-temperature compensation module in accordance With the teachings of the present invention.

FIG. 10 is a circuit diagram illustrating an exemplary volt age control module 650 utiliZed in a frequency-temperature compensation module in accordance With the teachings of the present invention.

FIG. 11 is a circuit diagram illustrating an exemplary ?rst process variation compensation module in accordance With the teachings of the present invention.

FIG. 12 is a circuit diagram illustrating an exemplary sec ond process variation compensation module in accordance With the teachings of the present invention.

FIG. 13 is a block diagram illustrating an exemplary fre quency calibration module in accordance With the teachings of the present invention.

FIG. 14 is a block diagram illustrating an exemplary fre quency divider, square Wave generator, asynchronous fre quency selector and glitch suppression module in accordance With the teachings of the present invention.

FIG. 15 is a graphical diagram illustrating exemplary loW latency frequency sWitching in accordance With the teachings of the present invention.

FIG. 16 is a block diagram illustrating an exemplary fre quency divider in accordance With the teachings of the present invention.

FIG. 17 is a block diagram illustrating an exemplary poWer mode selection module in accordance With the teachings of the present invention.

FIG. 18 is a block diagram illustrating an exemplary syn chroniZation module for a second oscillator in accordance With the teachings of the present invention.

McCorquodale et a]. (45) Date of Patent: *Apr. 12,...

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