MB86R12 ’Emerald-P’ MB86R12 ‘Emerald-P’ · Revised Oct. 31, 2012...

Revised Oct. 31, 2012 rd-mb86r12-emerald-p-rev1-20

Fujitsu Semiconductor Europe GmbH

MB86R12 ’Emerald-P’

RevOct. 31, 2012Version 1-20

October 31, 2012

MB86R12 ‘Emerald-P’

Register Descriptions

Fujitsu Semiconductor Europe GmbH MB86R12 ’Emerald-P’

WARRANTY AND DISCLAIMER

To the maximum extent permitted by applicable law, Fujitsu Semiconductor Europe GmbH restricts itswarranties and its liability for the Product [Hardware, Software and Documentation], its performance andany consequential damages, on the use of the Product in accordance with (i) the terms of the LicenseAgreement and the Sale and Purchase Agreement under which agreements the Product has beendelivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to themaximum extent permitted by applicable law, Fujitsu Semiconductor Europe GmbH disclaims allwarranties and liabilities for the performance of the Product and any consequential damages in casesof unauthorized decompiling and/or reverse engineering and/or disassembling.

1. Fujitsu Semiconductor Europe GmbH warrants that the Product will perform substantially inaccordance with the accompanying written materials, [Specifications etc.], for a period of 90days from the date of receipt by the customer. Concerning the hardware components of theProduct, Fujitsu Semiconductor Europe GmbH warrants that the Product will be free fromdefects in material and workmanship under use and service as specified in the accompanyingwritten materials for a duration of 1 year from the date of receipt by the customer.

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2 rd-mb86r12-emerald-p-rev1-20 Revised Oct. 31, 2012

MB86R12 ’Emerald-P’ Fujitsu Semiconductor Europe GmbH

Preface

Intention and Target Audience of this DocumentThis document describes and gives you detailed insight to the stated Fujitsu semiconductor product.The MB86R12 ’Emerald-P’ device belongs to the Emerald SoC Family used for graphics applications.The target audience of this document is engineers developing products which will use the MB86R12 ’Em-erald-P’ device. It describes the function and operation of the device. Please read this document carefully.

TrademarksAPIX is a registered trademark of Inova Semiconductors GmbH, Grafinger Str. 26, 81671 Munich, GermanyARM is a registered trademark of ARM Limited in UK, USA and Taiwan. ARM is a trademark of ARM Limited in Japan and Korea. ARM Powered logo is a registered trademark of ARM Limited in Japan, UK, USA, and Taiwan.ARM Powered logo is a trademark of ARM Limited in Korea. PrimeCell: is owned by ARM Limited.

System names and product names which appear in this document are the trademarks of the respective company or organization.

LicensesUnder the conditions of Philips corporation I2C patent, the license is valid where the device is used in an I2C system which conforms to the I2C standard specification by Philips Corporation.The purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as de-fined by Philips.Please acquire license of MediaLB from SMSC and request the following document: OS62400 MediaLB De-vice Interface Macro Advanced Product Data Sheet.Please contact your FSEU Sales representative to acquire license for SD Card and request the following document: MB86R12 ’Emerald-P’ Hardware Manual - “Chapter 29: SDIO Host Controller”.

Revision BarsSignificant changes to the last version are marked with revision bars.

Revised Oct. 31, 2012 rd-mb86r12-emerald-p-rev1-20 3

October 31, 2012 rd-mb86r12-emerald-p-rev1-20 1

MB86R12 - ‘Emerald-P’ Fujitsu Semiconductor Europe GmbH

Document Revision History

Version Date Editor Comment0-01 05.05.2011 A. v. Treuberg/R.v.

Reitzenstein1st. version (draft)

0-02 08.06.2011 A. v. Treuberg/R.v. Reitzenstein

2nd. version (draft).

All register review

Base address added0-03 22.07.2011 A. v. Treuberg/R.v.

ReitzensteinPixel engine updated

Ext. Bus Controller updated0-04 26.08.2011 R.v. Reitzenstein All register chapters reviewed and updated0-05 01.12.2011 R.v.Reitzenstein All register chapters reviewed and updated0-90 07.02.2012 A. v. Treuberg/R.v.

ReitzensteinAll registers reviewed, some minor changes

1-00 08.03.2012 R.v. Reitzenstein Complete update. All registers reviewed, some minor changes

1-10 11.07.2012 R.v.Reitzenstein - Chapter 5, Register MCR_82 updated- Chapter 14, Base address for Registers D_YHLPF, D_CHLPF and D_VLPF updated.- Chapter 31, TCON - Register DIR_PIN12_CTRL [20:19] and [18:17] updated.

1-20 24.08.2012 A. v. Treuberg - Corrected 16 and 8 bit registers in CCNT, I2C, USART and HS-SPI (first fields were incorrectly stated as 31:x). Added RXSHIFT and TXBITCNT registers in HS-SPI.- I2C bus registers offsets corrected.


Table of Content

Chapter 1 - General Information - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -1-1

Chapter 2 - Memory Map - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -2-1

Chapter 3 - Clock Reset Generator (CRG)- - - - - - - - - - - - - - - - - - - - - - - - - - - - -3-1

Chapter 4 - Boot Controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -4-1

Chapter 5 - External Bus Interface- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -5-1

Chapter 6 - DDR Memory Controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -6-1

Chapter 7 - DMA Controller (HDMAC) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -7-1

Chapter 8 - AXI-DMA Controller (XDMAC)- - - - - - - - - - - - - - - - - - - - - - - - - - - - -8-1

Chapter 9 - General Purpose Input/Output (GPIO) - - - - - - - - - - - - - - - - - - - - - - - - -9-1

Chapter 10 - Pulse Width Modulator (PWM) - - - - - - - - - - - - - - - - - - - - - - - - - - - 10-1

Chapter 11 - Analog-to-Digital Converter (ADC) - - - - - - - - - - - - - - - - - - - - - - - - - 11-1

Chapter 12 - Display Controller (DISP) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 12-1

Chapter 13 - Display Controller 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 13-1

Chapter 14 - Writeback Processor- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14-1

Chapter 15 - Video Capture - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 15-1

Chapter 16 - 3D Graphic Engine - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 16-1

Chapter 17 - Shader - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 17-1

Chapter 18 - Pixel Engine - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 18-1

Chapter 19 - Command Sequencer (CMDSEQ) - - - - - - - - - - - - - - - - - - - - - - - - - 19-1

Chapter 20 - I2S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 20-1

Chapter 21 - UART - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 21-1

Chapter 22 - USART - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 22-1

Chapter 23 - I2C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 23-1

Chapter 24 - Serial Flash Interface (SFI)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - 24-1

Chapter 25 - IDE Host Controller (IDE66) - - - - - - - - - - - - - - - - - - - - - - - - - - - - 25-1

Chapter 26 - Chip Controller (CCNT) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 26-1

Chapter 27 - External Interrupt Controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - 27-1

Chapter 28 - SDIO Host Controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 28-1

Chapter 29 - Infrared Data Association (IrDA) - - - - - - - - - - - - - - - - - - - - - - - - - - 29-1

Chapter 30 - Signature Unit (SIG) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 30-1

Chapter 31 - Ethernet Link Controller - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31-1

Chapter 32 - Timing Controller (TCON) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 32-1

Chapter 33 - RLD - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 33-1

Chapter 34 - HS-SPI - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 34-1

Chapter 35 - Watchdog B - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35-1

Chapter 36 - Power Management Unit (PMU) - - - - - - - - - - - - - - - - - - - - - - - - - - 36-1

Chapter 37 - Transport Stream Interface (TS) - - - - - - - - - - - - - - - - - - - - - - - - - - 37-1

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Fujitsu Semiconductor Europe GmbH MB86R12 - ‘Emerald-P’

Chapter 38 - APIX TX - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 38-1

Chapter 39 - APIX RX- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 39-1

Chapter 40 - APIX (PHY) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 40-1

Chapter 41 - AXI-Bus - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 41-1

2 rd-mb86r12-emerald-p-rev1-20 October 31, 2012


Format of Register Description

Chapter 1: General InformationThis chapter describes the format and the meaning of the register tables, as well as the lock/unlockregisters of the MB86R12 ’Emerald-P’.

1.1 Format of Register Description

The register descriptions in the following sections use the format shown below to describe each bit fieldof a register.

1.2 Meaning of Items and Sign

Register address:

Register address shows the address (Offset address) of the register.

Bit Position:

Bit position shows bit position of the register.

Bit Field name:

Bit Field name shows bit name of the register.

Type:

Shows the read/write attribute of each bit field

R: Read W: Write W1C: Writing a value of "1" clears the register. R0:Read value is always "0" R1: Read value is always "1" W0: Write value is always "0", and write access of "1" is ignored W1: Write value is always "1", and write access of "0" is ignored

Reset value:

Reset value indicates the value of each bit field immediately after reset.

0:Initial value is "0" 1:Initial value is "1" X:Undefined

Unused register fields are marked with a solid grey background.

Bit vectors are unsigned integers, if nothing else specified.

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Meaning of Items and Sign

Blank for technical reasons

1 - 2 rd-mb86r12-emerald-p-rev1-20 October 31, 2012


Memory Map

Chapter 2: Memory MapThis chapter shows the memory and the register map of the MB86R12 ’Emerald-P’.

2.1 Access Limitation

1. CortexA9 can access only Region(0xffff8000-0xffffbfff)Other modules cannot be accessed to this area.

2. Display Controller, Video Capture Unit, and Write Back Unit can access only DDR2/3 Memory.

3. 3D Graphic Engine/Pixel Engine can access only DDR2/3 Memory, 3 built-in SRAMs, andExternal memory(0xffff0000-).

4. AXI Bus register (0xD000_0000-,0xD040_0000-) can access only Cortex-A9.

5. Follow master module are not supported ACP access:Display/Capture/WriteBack/3D Graphics Engine/Pixel Engine.ACP region(0x4000_0000-0x7fff_ffff /0xd020_0000-0xd02f_ffff) access is prohibited.

2.2 ACP Access

XSRAM,DDR2/3 support ACP access (*1)

If using Cortex-A9 ACP access, please set below settings:

1. Cortex-A90x4000_0000-0x7fff_ffff outer-shareable, secure, outer-cacheable, bufferable0x8000_0000-0xbfff_ffff non-shareable, inner-shareable0xd020_0000-0xd02f_ffff outer-shareable, secure, outer-cacheable, bufferable0xc100_0000-0xc10f_ffff non-shareable, inner- shareable

2. HDMAC,SDIO0x4000_0000-0x7fff_ffff cacheable, bufferable access only0x8000_0000-0xbfff_ffff (no limitation)0xd020_0000-0xd02f_ffff cacheable, bufferable access only0xc100_0000-0xc10f_ffff (no limitation)

3. 3D Graphics Engine/Pixel Engine0x4000_0000-0x7fff_ffff access prohibited0x8000_0000-0xbfff_ffff (no limitation)0xd020_0000-0xd02f_ffff access prohibited0xc100_0000-0xc10f_ffff (no limitation)

4. Display/Capture/WriteBack/0x4000_0000-0x7fff_ffff access prohibited0x8000_0000-0xafff_ffff (no limitation)0xd020_0000-0xd02f_ffff access prohibited0xc100_0000-0xc10f_ffff (no limitation)



Memory Map

2.3 AMBA Privileged Access Attribute

Cortex-A9/XDMAC/SDIO/HDMAC: Depend on master.

Other: Always privileged access.

*For Emerald, it is recommended to use always privileged access.

2.4 AMBA Secure Access Attribute

Cortex-A9/XDMAC: Depend on master.

Other: Always secure access.

**For Emerald, it is recommended to use always secure access.



Memory Map

2.5 Memory Map

Table 2-1 show the memory map of MB86R12 ’Emerald-P’.

Table 2-1: Memory map of the MB86R12 ’Emerald-P’(before remapped) Level-1 Level-2 Level-3 Start Address Unit Limitation

Reserved 0xFFFF_C000 ReservedCA9

only

Cortex-A9 Private Mem-ory

Region

0xFFFF_A000 Cortex-A9 From Cortex-A9 only

PL310 0xFFFF_8000 PL310AHB0 BootROM (Mirror) 0xFFFF_0000 BootROM(32KB) Cannot be

accessed from MediaLB, SDIO

AXI0 External Bus

Controller

Reserved 0xF000_0000 ReservedExtRAM 0xE000_0000 External RAM

Reserved 0xD120_0000 Reserved3D Graphics Engine

0xD100_0000 3DGE

Reserved 0xD087_0000 ReservedDisplay/Capture Reserved 0xD086_1000 Reserved

Capture 3 0xD086_0000 Capture 3Reserved 0xD085_1000 ReservedCapture 2 0xD085_0000 Capture 2Reserved 0xD084_1000 ReservedCapture 1 0xD084_0000 Capture 1Reserved 0xD083_1000 ReservedCapture 0 0xD083_0000 Capture 0Reserved 0xD082_1000 ReservedWrite Back 0xD082_0000 Write Back Reserved 0xD081_2000 ReservedDisplay 1 0xD081_0000 Display 1Reserved 0xD080_2000 ReservedDisplay 0 0xD080_0000 Display 0

Reserved 0xD054_0000 ReservedPTM 0xD050_0000 RegisterReserved 0xD041_1000 ReservedIrDA 0xD041_0000 IrDAReserved 0xD040_1000 ReservedAXI Bus 0xD040_0000 AXI Bus

PortSet Register

From Cortex-A9 only

XDMAC 0xD030_0000 XDMACXSRAM

(ACP *1)

0xD020_8000 Reserved0xD020_0000 SRAM(32KB)

Reserved 0xD010_0000 ReservedAXI Bus 0xD000_0000 AXI Bus

Interface RegisterReserved 0xC110_0000 Reserved



Memory Map

AXIO XSRAM

(NO ACP *1)

0xC100_8000 Reserved0xC100_0000 SRAM(32KB)

TS I/F 0xC000_0000 TS I/FDDR3

(NO ACP *1)

0x8000_0000 DDR2/3

(1Gbyte) DDR3

(ACP *1)

0x4000_0000 DDR2/3

(1Gbyte) Reserved 0x3f07_0000 ReservedAPB0 Reserved 0x3f06_0000 Reserved

USART USART_5 0x3f05_0000 USART_5USART_4 0x3f04_0000 USART_4USART_3 0x3f03_0000 USART_3USART_2 0x3f02_0000 USART_2USART_1 0x3f01_0000 USART_1USART_0 0x3f00_0000 USART_0

Reserved 0x3e21_0000 ReservedCRG_P 0x3e20_0000 CRG_PReserved 0x3e12_0000 ReservedCAN CAN_1 0x3e11_0000 CAN_1

CAN_0 0x3e10_0000 CAN_0Reserved 0x3e06_0000 ReservedUART UART_5 0x3e05_0000 UART_5

UART_4 0x3e04_0000 UART_4UART_3 0x3e03_0000 UART_3UART_2 0x3e02_0000 UART_2UART_1 0x3e01_0000 UART_1UART_0 0x3e00_0000 UART_0

Reserved 0x3d25_0000 ReservedI2C I2C_4 0x3d24_0000 I2C_4

I2C_3 0x3d23_0000 I2C_3I2C_2 0x3d22_0000 I2C_2I2C_1 0x3d21_0000 I2C_1I2C_0 0x3d20_0000 I2C_0

Reserved 0x3d11_0000 ReservedCCNT 0x3d10_0000 CCNTReserved 0x3d01_0000 ReservedPMU 0x3d00_0000 PMUReserved 0x3c41_0000 ReservedExternal Bus

Controller

0x3c40_0000 External Bus

Controller

(Register)Reserved 0x3c34_0000 ReservedGCNT 0x3c30_0000 GCNTReserved 0x3c23_0000 ReservedPWM PWM_2 0x3c22_0000 PWM_2

PWM_1 0x3c21_0000 PWM_1PWM_0 0x3c20_0000 PWM_0

Table 2-1: Memory map of the MB86R12 ’Emerald-P’(before remapped) (Continued)Level-1 Level-2 Level-3 Start Address Unit Limitation



Memory Map

APB0 Reserved 0x3c12_0000 ReservedADC ADC_1 0x3c11_0000 ADC_1

ADC_0 0x3c10_0000 ADC_0Reserved 0x3b51_0000 ReservedCRG_S 0x3b50_0000 CRG_SReserved 0x3b51_0000 ReservedEXIRC EXIRC_1 0x3b41_0000 EXIRC_1

EXIRC_0 0x3b40_0000 EXIRC_0Reserved 0x3b31_0000 ReservedGPIO 0x3b30_0000 GPIOReserved 0x3b21_0000 ReservedBC 0x3b20_0000 BCReserved 0x3b11_0000 ReservedWDT A 0x3b10_0000 WDTReserved 0x3b01_0000 ReservedTimers 0x3b00_0000 Timers

Reserved 0x3a04_0000 ReservedAHB2 APIX APIX TX xh2 0x3a03_0000 APIX TX xh2

APIX TX ch1 0x3a02_0000 APIX TX ch1APIX TX ch0 0x3a01_0000 APIX TX ch0APIX RX 0x3a00_0000 APIX RX

Reserved 0x3900_0000 ReservedCommand Sequencer

0x38F0_0000 Command Sequencer1

0x38E0_0000 Command Sequencer0

Pixel Engine 0x38C0_0000 Pixel EngineDisplay 2 0x38A0_0000 Display 2DDR Controller 0x3840_0000 DDR ControllerReserved 0x3823_0000 ReservedSIG SIG_2 0x3822_0000 SIG_2

SIG_1 0x3821_0000 SIG_1SIG_0 0x3820_0000 SIG_0

HS_SPI 0x3810_0000 HS_SPI (Register)0x2810_0000 HS_SPI (Memory)

TCON 0x2800_0000 TCONReserved 0x1700_0000 ReservedAHB1 SFI_1 0x1600_0000 SFI_1 Serial Flash

0x1500_0000 SFI_1 registerReserved 0x0700_0000 ReservedSFI_0 0x0600_0000 SFI_0 Serial Flash

0x0500_0000 SFI_0 registerReserved 0x04E4_0000 ReservedI2S I2S_3 0x04E3_0000 I2S_3

I2S_2 0x04E2_0000 I2S_2I2S_1 0x04E1_0000 I2S_1I2S_0 0x04E0_0000 I2S_0




Memory Map

AHB1 HDMAC 0x04D0_0000 HDMAC Cannot be accessed from IDE66, HDMAC, RLD, Ether

RLD 0x04C0_0000 RLDReserved 0x04B0_0000 ReservedWDT B 0x04A0_0000 WDT Cannot be

accessed from Ether, IDE66

IDE66 0x0490_0000 IDE66 Cannot be accessed from IDE66

Ethernet 0x0480_0000 Ethernet Cannot be accessed from RLD, Ether, IDE66

HSRAM1 0x0400_8000 Reserved0x0400_0000 SRAM(32KB)

Reserved 0x00D0_0000 ReservedAHB0 BootROM (mirror) 0x00C0_0000 BootROM Cannot be

accessed from MediaLB, SDIO

Reserved 0x00B0_0000 ReservedMediaLB 0x00A0_0000 MediaLB Cannot be

accessed from MediaLB

Reserved 0x0093_0000 ReservedSDIO SDIO 2 0x0092_0000 SDIO 2 Cannot be

accessed from SDIO2

SDIO 1 0x0091_0000 SDIO 1 Cannot be accessed from SDIO1

SDIO 0 0x0090_0000 SDIO 0 Cannot be accessed from SDIO0

Reserved 0x0020_0000 ReservedHSRAM0 0x0010_8000 Reserved

0x0010_0000 SRAM(32KB)BootROM 0x0000_8000 Reserved

0x0000_0000 BootROM(32KB) Cannot be accessed from MLB,SDIO

Table 2-2: Memory Map of MB86R12 (after remapped)Level-1 Level-2 Level-3 Start Address Macro Limitation

same as "before remaped"AHB 0 HSRAM0 0x0000_8000 Reserved

0x0000_0000 SRAM(32KB)




Memory Map

2.6 Register Access

Basically, register in MB86R12 should be accessed by single 32bit length.

1. All size, all burst type

XSRAM (0xc100_0000-,0xd020_0000-) SFI memory (0x0600_0000-,0x1600_0000-) EBC memory (0xe000_0000-) HSRAM0 (0x0010_0000-) HSRAM1 (0x0400_0000-) HS_SPI memory (0x2810_0000-) Boot ROM (0x0000_0000-,0xffff_0000-)

2. Almost all size, all burst type

DDR memory (0x4000_0000-,0x8000_0000-) * Except small size WRAP burst (16 bytes or less)

3. 8/32bit single access

USART (0x3f00_0000-, 0x3f01_0000-, 0x3f02_0000-, 0x3f03_0000-, 0x3f04_0000-, 0x3f05_0000-)

4. 32bit single/burst access

TCON DIR_SSqCnts Register HS_SPI HSSPI_TXFIFO 0-15/HSSPI_RXFIFO 0-15 Register Display Controller CTLUDATA/Palette Register Command Sequencer HIF Register 3DGE DDLFIFO Register



Memory Map




Chapter 3: Clock Reset Generator (CRG)This chapter shows all Register of unit Clock Reset Generator (CRG)

Table 3-1: Register OverviewBase Address Register Address Register Name Register Description

3E20_0000 (CRG-P)3B50_0000 (CRG_S)

Base address + 000h CRPLC PLL control register

Base address + 004h CRRDY PLL ready monitor registerBase address + 008h CRSTP Stop control registerBase address + 010h CRIMA Interrupt mask control registerBase address + 014h CRPIC Interrupt clear registerBase address + 020h CRRSC Reset control registerBase address + 024h CRSWR Software reset request registerBase address + 028h CRRRS Register controlled reset request registerBase address + 02Ch CRRSM Reset and monitor registerBase address + 030h CRCDC Clock divider control registerBase address + 100h CRDM0 Clock divider mode register of CLK0Base address + 104h CRLP0 Low power control register of CLK0Base address + 110h CRDM1 Clock divider mode register of CLK1Base address + 114h CRLP1 Low power control register of CLK1Base address + 120h CRDM2 Clock divider mode register of CLK2Base address + 124h CRLP2 Low power control register of CLK2Base address + 130h CRDM3 Clock divider mode register of CLK3Base address + 134h CRLP3 Low power control register of CLK3Base address + 140h CRDM4 Clock divider mode register of CLK4Base address + 144h CRLP4 Low power control register of CLK4Base address + 150h CRDM5 Clock divider mode register of CLK5Base address + 154h CRLP5 Low power control register of CLK5Base address + 160h CRDM6 Clock divider mode register of CLK6Base address + 164h CRLP6 Low power control register of CLK6Base address + 170h CRDM7 Clock divider mode register of CLK7Base address + 174h CRLP7 Low power control register of CLK7Base address + 180h CRDM8 Clock divider mode register of CLK8Base address + 184h CRLP8 Low power control register of CLK8Base address + 190h CRDM9 Clock divider mode register of CLK9Base address + 194H CRLP9 Low power control register of CLK9.Base address + 1A0H CRDMA Clock divider mode register of CLKA.Base address + 1A4H CRLPA Low power control register of CLKA.Base address + 1B0H CRDMB Clock divider mode register of CLKB.Base address + 1B4H CRLPB Low power control register of CLKB.Base address + 1C0H CRDMC Clock divider mode register of CLKC.Base address + 1C4H CRLPC Low power control register of CLKC.Base address + 1D0H CRDMD Clock divider mode register of CLKD.Base address + 1D4H CRLPD Low power control register of CLKD.Base address + 1E0H CRDME Clock divider mode register of CLKE.Base address + 1E4H CRLPE Low power control register of CLKE.Base address + 1F0H CRDMF Clock divider mode register of CLKF.Base address + 1F4H CRLPF Low power control register of CLKF.



Register Description

3.1 Register Description

3.1.1 CRPLCPLL control register.

Bit Position Bit Field Name Type Reset Bit Description

[31:25] Reserved - - -

[24] PLLBYPASS RW PLLBYPASS PLL bypass mode. This bit is used to enter or exit PLL bypass mode. When this bit is set/cleared, the CRG unit enters/exits PLL bypass mode. This bit is initial-ized when a CRSTn port is asserted. The initial value is determined by the value of the PLLBYPASS pin. Note: Please do NOT change the PLLBYPASS bit while the FBMODE[5:0] bits are 6’b000000.0: PLL clock is not bypassed.1: PLL clock is bypassed.

[23:20] Reserved - - -

[19:16] LUWMODE RW 0xA PLL lock-up wait time. These bits are used to set PLL lock-up wait time. The relation between the lock-up wait time and these bits is determined by the following tables. It is necessary to set an appropriate period according to the specification of PLL macro. These bits are initialized when a CRSTn port is asserted.LUWMODETLUW (Time Lockup Wait):0: 64 x TREFCLK1: 128*TREFCLK2: 512*TREFCLK3: 768*TREFCLK4: 1024*TREFCLK5: 1536*TREFCLK6: 2048*TREFCLK7: 3072*TREFCLK8: 4096*TREFCLK9: 6144*TREFCLK10: 8192*TREFCLK11: 12288*TREFCLK12: 16384*TREFCLK13: 24576*TREFCLK14: 32768*TREFCLK15: 49152*TREFCLK

[15:12] Reserved - - -

[11:8] PSMODE RW {3'b000,PSMODE} Sets the dividing ratio of the PLL clock fre-quency.This bit is initialized when a CRSTn port is asserted.0000: Divider n = 10001: Divider n = 1 / (1 * 2)

[7:6] Reserved - - -




3.1.2 CRRDYPLL ready monitor register.

[5:0] FBMODE RW 6'b000000(PLLBYPASS=1)/ 6'b111111(PLLBYPASS=0)

Stops operation of the PLL clock.Note: Please be sure to set as PLL BYPASS mode before stopping PLL.6'b00_0000: The PLL is stopped6'b11_1111: The PLL is activated


[31:5] Reserved - - -

[4] PSRMNT R 0 PSMODE monitor. The PSMODE bit indicates that the PSMODE bits setting (CRPLC register) have been used in the PLL clock frequency calculation. It is used to confirm that the PSMODE change operation was completed. This bit is initialized when a CRSTn port is asserted or the value of PSMODE bits is changed. Its initial value is 0. Write accesses to this (read-only) bit are ignored.0: PSMODE value is not used for the PLL clock frequency.1: PSMODE value is used for the PLL clock fre-quency.


[0] PLLRDY R 0 PLLREADY monitor. PLLRDY bit indicates an overflow of PLL lock-up wait time that is set by the LUWMODE[3:0] bits (CRPLC register). This bit does NOT indi-cate that the PLL is locked-up but only that the PLL lock-up wait time has expired. This bit is ini-tialized when CRSTn port is asserted or the value of FBMODE bits is changed, and the initial value is 0. Write accesses to this (read-only) bit are ignored.0: PLL is not ready.1: PLL is ready.





3.1.3 CRSTPStop control register.

3.1.4 CRIMAInterrupt mask control register.


[31:2] Reserved - - -

[1] STOPMNT RW0 0 Stop mode monitorThe STOPMNT bit is used to monitor the Stop mode. If the CRG unit is in stop mode, this bit is set. This bit is initialized when a CRSTn port is asserted, and its initial value is 0. Write accesses with 1 are ignored. This bit is set only when CRG is in Stop mode.0: Not in Stop mode1: In Stop mode

[0] STOPEN RW 0 Stop mode enableThe CRG unit enters stop mode when this bit is set and the STANDBYWFI port is asserted. This bit is initialized when a CRSTn port is asserted, and its initial value is 0.0: STOPDISABLED - Do not enter Stop mode.1: STOPENABLED - Enter Stop mode when the STANDBYWFI port is asserted.


[31:1] Reserved - - -

[0] RDYINTM RW 1 Mask signal of PLLRDY interruptThis bit masks PLLRDYINT interrupt that indi-cates an overflow of the PLL lock-up wait time. If this bit is set, the interrupt doesn’t occur when the PLL lock-up wait time has expired. If not set, the interrupt occurs and the PLLRDYINT port is asserted. This bit is initialized when a CRSTn port is asserted, and its initial value is 1.0: Don't mask the PLLRDYINT interrupt.1: Mask the PLLRDYINT interrupt.




3.1.5 CRPICInterrupt clear register.

3.1.6 CRRSCCRG Reset control register.


[31:1] Reserved - - -

[0] PLLRDYINT RW0 0 PLLRDY interrupt clearThis bit is PLLRDYINT interrupt monitor that indicates an overflow of PLL lock-up wait time. When PLL lock-up wait time is completed and RDYINTM bit is set low, the PLLRDYINT port is asserted and this bit is set. This bit is also used to clear the interrupt via PLLRDYINT port. The PLLRDYINT port is deasserted and this bit is cleared by writing access (0 or 1) to this bit. This bit is initialized when CRSTn port is asserted, and the initial value is 0.0: The PLLRDYINT interrupt is not asserted. - 1: The PLLRDYINT interrupt is asserted. -


[31:20] Reserved - - -

[19:16] SRSTMODE RW F SRST reset pulse widthThis bit is used to set pulse width of SRSToutn. It is necessary to set an appropriate reset time according to the specification of the debugging tool. TCCLK: CCLK cycle time. These bits are initialized when CRSTn port is asserted.0: 8 x TCCLK. - 1: 12 x TCCLK. - 2: 16 x TCCLK. - 3: 24 x TCCLK. - 4: 32 x TCCLK. - 5: 48 x TCCLK. - 6: 64 x TCCLK. - 7: 96 x TCCLK. - 8: 128 x TCCLK. - 9: 192 x TCCLK. - 10: 256 x TCCLK. - 11: 384 x TCCLK. - 12: 512 x TCCLK. - 13: 768 x TCCLK. - 14: 1024 x TCCLK. - 15: 1536 x TCCLK. -

[15:10] Reserved - - -




[9] WDRSTM RW 0 Watchdog reset mode. A watchdog reset occurs immediately after the WDRSTREQ port is asserted. The reset opera-tion is determined by this bit. When high, CRG initializes the logic including this module. When low, CRG initializes the logic excluding this mod-ule and all register values of this module are preserved before and after reset. This bit is initialized when a CRSTn port is asserted and its initial value is 0.0: CRG doesn’t initialize itself by asserting a watchdog reset.1: CRG initializes itself by asserting a watchdog reset.

[8] SWRSTM RW 0 Software reset mode. A software reset occurs immediately after the SWRSTREQ bit is set. The reset operation is determined by this bit. When high, the CRG unit initializes the logic including this module. When low, CRG initializes the logic excluding this mod-ule and all register values of this module are preserved before and after reset. This bit is initialized when a CRSTn port is asserted and its initial value is 0.0: CRG doesn’t initialize itself by asserting a software reset.1: CRG initializes itself by asserting a software reset.


[3:0] ARSTMODE RW 0xA This bit is used to set the pulse width of the ARESETn signal (software reset pulse width). It is necessary to set an appropriate reset time according to the specification of the AMBA peripherals. After ARESETn has been asserted for the cycles shown in the following table, it is deasserted on the coincident edge of all clocks. Therefore the following table indicates the mini-mum width of the ARESETn pulse. TCCLK: CCLK Cycle time. These bits are initialized if a CRSTn port is asserted0: 8 x TCCLK. - 1: 12 x TCCLK. - 2: 16 x TCCLK. - 3: 24 x TCCLK. - 4: 32 x TCCLK. - 5: 48 x TCCLK. - 6: 64 x TCCLK. - 7: 96 x TCCLK. - 8: 128 x TCCLK. - 9: 192 x TCCLK. - 10: 256 x TCCLK. - 11: 384 x TCCLK. - 12: 512 x TCCLK. - 13: 768 x TCCLK. - 14: 1024 x TCCLK. - 15: 1536 x TCCLK. -





3.1.7 CRSWRSoftware reset request register.

3.1.8 CRRRSRegister controlled reset request register.

Notes:

*1 When you use AHB1 modules, please release RRESETn[8]

*2 When you use AHB2 modules, please release RRESETn[20]

*3 When you want to access from AHB0 masters to other bus slaves, please release RRESETn[25]

*4 If you use ADC/PWM module, please release both RRESETn[22] and RRESETn[26]


[31:1] Reserved - - -

[0] SWRSTREQ RW 0 Software reset requestThis bit is used to assert a software reset. A software reset occurs immediately after this bit is set. The operation of the reset is determined by SWRSTM bit (CRRSM register). This bit is initialized when CRSTn port is asserted and its initial value is 0. The value is always 0 when read access to this bit occurs.




Bit Position

Bit Field Name

Type Reset Bit Description

[31:0] RRSTREQ RW 0 Register-controlled reset requestThis bitfield is used to assert/deassert register-controlled resets (RRE-SETn[31:0]). RRESETn[y] (active low) is asserted immediately after the RRSTREQ[y] bit is set to 0 or ARESETn is asserted. It is deasserted after the RRSTREQ[y] bit has been set to 1.This bit is initialized when CRSTn port is asserted or software/watchdog reset occurs and its initial value is 0.0: Assert requests for RRESETn[y]1: Deassert requests for RRESETn[y]Modules controlled by the register fieldsRESETN[31]: USART/CAN Register*7/UART Register*7/CRG_P Register*7RRESETN[30]: CAN/USART/CRG_P Register*6RRESETN[29]: I2CRESETN[28]: -RRESETN[27]: -ADC/PWM /EBC Register*5/Display0, Display1 Register*5/Capture Register*5/WriteBack Register*5RRESETN[25]: AHB0 Bridge (AHB0 ® other bus) *3RRESETN[24]: GPIO/EXIRCRRESETN[23]: TIMER/WDT_ARRESETN[22]: ADC/PWMRRESETN[21]: APIXRRESETN[20]: AHB2 Bus *2/Display2 register/CmdSeq register/PixelEngine register/DDRC registerRRESETN[19]: HS_SPIRRESETN[18]: SIGRRESETN[17]: TCONRRESETN[16]: IDE66RRESETN[15]: WDT_BRRESETN[14]: EtherRRESETN[13]: I2SRRESETN[12]: SFIRRESETN[11]: RLDRRESETN[10]: HDMACRRESETN[9]: HSRAM1RRESETN[8]: AHB1 Bus *1RRESETN[7]: DDR2/3 ControllerRRESETN[6]: 3D Graphics Engine/PixelEngineRRESETN[5]: Display/Capture/WritebackRRESETN[4]: IrDARRESETN[3]: -RRESETN[2]: SDIO InterfaceRRESETN[1]: MediaLBRRESETN[0]: CRG_P




3.1.9 CRRSMReset and monitor register.

3.1.10 CRCDCClock divider control register.


[31:4] Reserved - - -

[3] PORESET RW 1 PORESETn monitorThis bit monitors a Power-On PORESETn reset. It is set only when a power on reset is asserted through PORESETn port. It is necessary to write 0 to clear this bit. This bit is initialized when PORESETn port is asserted and its initial value is 1. Writing 1 is ignored.0: PORESETn was not asserted.1: PORESETn was asserted.

[2] SRST RW 0 SRST reset monitorThis bit monitors a SRST reset from a debug-ging tool. It is set only when a SRST reset occurs through the XSRSTinn port. It is neces-sary to write 0 to clear this bit. This bit is initialized when PORESETn port is asserted and its initial value is 0. Writing 1 is ignored.0: XSRSTinn was not asserted.1: XSRSTinn was asserted.

[1] SWRST RW 0 Software reset monitor. It is set only after a software reset has occurred. It is necessary to write 0 to clear this bit.0: Software reset was not asserted.1: Software reset was asserted.

[0] WDRST RW 0 Watchdog reset monitor. This bit is set when a watchdog reset occurs. It is necessary to write 0 to clear this bit. This bit is initialized when PORESETn port is asserted and its initial value is 0. Writing 1 is ignored.0: Watchdog reset was not asserted.1: Watchdog reset was asserted.


[31:1] Reserved - - -

[0] DCHREQ RW 0 Clock divider mode update requestThis bit updates the clock divider modes. If this bit is set after the CRDMx registers are set, the operation to change the clock divider modes begins and it is updated on the coincident edge of all CLKx[y] clocks. This bit is automatically cleared after the divider modes are updated. This bit is initialized when CRSTn port is asserted and its initial value is 0.0: Don't update clock divider mode.1: Update clock divider mode.




3.1.11 CRDMx (x=0h...Fh)Clock divider mode register of CLK0.


[31:8] Reserved - - -

[7:0] DIVMODEx RW 0 CLKx domain divider modeThese bits are used to set CLKx domain (gated-CLKx and CLKx[7:0]) divider modes. CLKx domain divider mode is determined using the following calculation. fCLKx = fCCLK X [(1/3)M X (1/2)N] (where N=0~3 and M=0~3.) fCLKx : clock frequency of CLKx domain (ungated CLKx and CLKx[7:0]) fCCLK : clock frequency of CCLK Parameters M and N are determined according to the DIVMODEx bits. E.g. when the bitfield is set to 0x47M = 2, N = 3fCLKx = fCCLK X (1/72). 0x00: fCLKx = fCCLK x (1/1). - 0x01: fCLKx = fCCLK x (1/2). - 0x03: fCLKx = fCCLK x (1/4). - 0x07: fCLKx = fCCLK x (1/8). - 0x0F: fCLKx = fCCLK x (1/16). - Initial value0x02: fCLKx = fCCLK x (1/3). - Not 50/50 duty cycle0x05: fCLKx = fCCLK x (1/6). - 0x0B: fCLKx = fCCLK x (1/12). - 0x17: fCLKx = fCCLK x (1/24). - 0x08: fCLKx = fCCLK x (1/9). - Not 50/50 duty cycle0x11: fCLKx = fCCLK x (1/1). - 0x23: fCLKx = fCCLK x (1/36). - 0x47: fCLKx = fCCLK x (1/72). - 0x1A: fCLKx = fCCLK x (1/27). - Not 50/50 duty cycle0x35: fCLKx = fCCLK x (1/54). - 0x6B: fCLKx = fCCLK x (1/108). - 0xD7: fCLKx = fCCLK x (1/216). - Others: reserved - These bits are initialized when a CRSTn port is asserted and their initial value is determined by the value of CRIDx[7:0] ports. Note 1 : Writing access is ignored while the DCHREQ bit of the CRCDC register is high.Note 2 : When N = 0 and M = 1, 2, 3, the duty cycle of the ungatedCLKx and CLKx is NOT 50/50. Note 3 : N = 0..3, M = 0..3.




3.1.12 CRLPx (x=0h...Fh)Low power control register of CLK0

.


[31:24] CENx R 0xFF CLK[7:0] low power state monitorThese bits monitor the internal CENx[7:0] signal. CENx[y] is low when CLKx[y] is stopped. 0: CLKx[y] is stopped. - 1: CLKx[y] is not stopped. - These bits are initialized when CRSTn port is asserted, and the initial value is 8’b11111111. Write accesses are ignored. These are read-only bits.

[23:16] CACTIVE_Cx R 0 These bits monitor internal CACTIVE_Cx[7:0] signals. These bits are set when the external CACTIVEx[y] port is high. 0: Low power active request is not asserted. - 1: Low power active request is asserted. - These bits are initialized when CRSTn port is asserted, and the initial value is 8’h00. Write accesses are ignored. These are read-only bits.

[15:8] LPOWERHSx R 0 These bits monitor internal LPOWERHSx[7:0] signals. These bits are set when the hand-shakes of low power interface (CSYSREQ and CSYSACK) between CRG and a peripheral on the CLKx[y] domain continues. 0: Writing access to CSYSREQ_Rx[y] is accept-able. - 1: Writing access to CSYSREQ_Rx[y] is ignored. - These bits are initialized when CRSTn port is asserted, and the initial value is 8’b00000000. Write accesses are ignored. These are read-only bits.

[7:0] CSYSREQ_Rx RW 0xFF These bits control the clock gates of CLKx[7:0]. CLKx[y] is stopped / activated by writing access to the CSYSREQ_Rx[y] bit. CLKx[y] is also acti-vated when a peripheral requests its clock through CACTIVE_Cx[y]. 0: CLKx[y] stop request. - 1: CLKx[y] active request. - These bits are initialized when CRSTn port is asserted, and the initial value is 8’b11111111.



Chapter 4: Boot ControllerThis chapter describes all registers of the boot controller unit.

Table 4-1: Register OverviewBase

AddressRegister Address Register Name Register Description

3B20_0000 Base address + 0000h REMAPSTA Remap status register Base address + 0004h REMAPSET Remap set register Base address + 0010h VIHSTA VINITHI status register Base address + 0030h GPREG0/1/2/

3 General Purpose register 0

Base address + 0034h DSH0SEL General Purpose register 1 Base address + 0038h DSH0SEL General Purpose register 2 Base address + 003Ch DSH0SEL General Purpose register 3 Base address + 0050h DSH0SEL Default Slave AHB_0 Select Control register Base address + 0054h DSH1SEL Default Slave AHB_1 Select Control register Base address + 0058h DSH2SEL Default Slave AHB_2 Select Control register Base address + 005Ch DSP0SEL Default Slave APB_0 Select Control register Base address + 0060h DSX0SEL Default Slave AXI_0 Select Control register





4.1.1 REMAPSTARemap status register

Address Base address + 0x00 (h)Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Name ReservedR/W -Initial value

-

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Name Reserved

Rem

apSt

a-tu

s

R/W - RInitial value

- 0

Bit field no. Bit field name Description

0 RemapStatus This read-only bit indicates the current status of the Remap register.

The initial value of this bit is "0".

The following table shows relations between Remap and memory map sta-tus.

0: Before remapping

1: After remapping




4.1.2 REMAPSETRemap set register


-


Rem

apSe

t

R/W - WInitial value

- -

Bit field no. Bit field name Description[0] RemapSet This write-only bit is used to set the remap register.

Writing "1" to this bit sets the Remap register.

Writing "0" is ignored.




4.1.3 VIHSTAVINITHI status register


-


VIH

STA

R/W - RInitial value

- 0

Bit field no. Bit field name Description[0] VIH Status This read-only bit indicates the current status of the VIHSTA register. The

VIHSTA register indicates the current status of VINITHI of Cortex-A9. For the details 0f VINITHI of Cortex-A9, please refer to the Technical Reference Manual of Cortex-A9 MP issued by ARM Limited.




4.1.4 GPREG0/1/2/3General purpose register

Address Base address + 0x30, 0x34, 0x38, 0x3C (h)Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Name GPREG 0/1/2/3R/W RWInitial value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Name GPREG 0/1/2/3R/W RWInitial value

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit field no. Bit field name Description[31:0] GPREG 0/1/2/3 These General Purpose Registers are 32-bit wide readable/writeable regis-

ters.

The initial value is "0".




4.1.5 DSH0SELDefault Slave AHB_0 register


-

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Name

Res

erve

d

Boo

t RO

M

Res

erve

d

Res

erve

d

Res

erve

d

SD

IO 2

SD

IO 1

SD

IO 0

Res

erve

d

HS

RA

M 0

Med

ia L

B

R/W - RW RW RW RW RW RW RW - RW RWInitial value

- 0 0 0 0 0 0 0 - 0 0

Bit field no. Bit field name Description[31:10] Reserved Reserved[9] Boot ROM These bit switch a Slave interface of the Boot ROM unit and an error

response circuit.

1: enables an error response circuit

0: enables a Slave interface[8] Reserved Reserved, do not modify.

[7] Reserved Reserved, do not modify.

[6] Reserved Reserved, do not modify.

[5] SDIO 2 These bit switch a Slave interface of the SDIO 2 unit and an error response circuit.


0: enables a Slave interface[4] SDIO 1 These bit switch a Slave interface of the SDIO 1 unit and an error response

circuit.


0: enables a Slave interface[3] SDIO 0 These bit switch a Slave interface of the SDIO 0 unit and an error response

circuit.


0: enables a Slave interface[2] Reserved Reserved

[1] HSRAM 0 These bit switch a Slave interface of the HSRAM 0 unit and an error response circuit.


0: enables a Slave interface




[0] Media LB These bit switch a Slave interface of the Media LB unit and an error response circuit.









-

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Name

ReservedID

E66

Eth

er

WD

T B

I2S

3

I2S

2

I2S

1

I2S

0

SFI 1

SFI 0

RLD

HD

MA

C

HS

RA

M 1

R/W - RW RW RW RW RW RW RW RW RW RW RW RWInitial value

- 0 0 0 0 0 0 0 0 0 0 0 0

Bit field no. Bit field name Description[31:12] Reserved Reserved[11] IDE66 These bit switch a Slave interface of the IDE66 unit and an error response

circuit.


0: enables a Slave interface[10] Ether These bit switch a Slave interface of the Ethernet unit and an error

response circuit.


0: enables a Slave interface[9] WDT B These bit switch a Slave interface of the Watchdog B unit and an error

response circuit.


0: enables a Slave interface[8] I2S 3 These bit switch a Slave interface of the I2S 3 unit and an error response

circuit.



circuit.



circuit.



circuit.






[4] SFI 1 These bit switch a Slave interface of the SFI 1 unit and an error response circuit.


0: enables a Slave interface[3] SFI 0 These bit switch a Slave interface of the SFI 0 unit and an error response

circuit.


0: enables a Slave interface[2] RLD These bit switch a Slave interface of the RLD unit and an error response

circuit.


0: enables a Slave interface[1] HDMAC These bit switch a Slave interface of the HDMAC unit and an error

response circuit.


0: enables a Slave interface[0] HSRAM 1 These bit switch a Slave interface of the HSRAM 1 unit and an error

response circuit.









-

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Name

Res

erve

d

SIG

2

SIG

1

SIG

0 Reserved

Dis

play

2

Com

man

d Se

quen

cer

Pix

el E

ngin

e

DD

R R

egis

ter

Reserved

HS

_SP

I

TCO

N

R/W - RW RW RW - RW RW RW RW - RW RWInitial value - 0 0 0 - 0 0 0 0 - 0 0

Bit field no. Bit field name Description[31:15] Reserved Reserved[14] SIG 2 These bit switch a Slave interface of the SIG 2 unit and an error response

circuit.


0: enables a Slave interface[13] SIG 1 These bit switch a Slave interface of the SIG 1 unit and an error response

circuit.


0: enables a Slave interface[12] SIG 0 These bit switch a Slave interface of the SIG 0 unit and an error response

circuit.


0: enables a Slave interface[11:10] Reserved Reserved

[9] Display 2 These bit switch a Slave interface of theDisplay 2 unit and an error response circuit.


0: enables a Slave interface[8] Command

SequencerThese bit switch a Slave interface of the Command Sequencer unit and an error response circuit.


0: enables a Slave interface[7] Pixel Engine These bit switch a Slave interface of the Pixel Engine unit and an error

response circuit.






[6] DDR Register These bit switch a Slave interface of the DDR Register unit and an error response circuit.



[1] HS_SPI These bit switch a Slave interface of the HS_SPI unit and an error response circuit.


0: enables a Slave interface[0] TCON These bit switch a Slave interface of the TCON and an error response cir-

cuit.







4.1.8 DSP0SELDefault Slave APB_0 register

Address Base address + 0x5C (h)Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Name ReservedR/W -Initial value

-

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Name

Reserved

UA

RT/

USA

RT

5

UA

RT/

USA

RT

4

UA

RT/

USA

RT

3

UA

RT/

USA

RT

2

UA

RT/

USA

RT

1

UA

RT/

USA

RT

0

Reserved

R/W - RW RW RW RW RW RW -Initial value - 0 0 0 0 0 0 -

Bit field no. Bit field name Description[31:10] Reserved Reserved[9] UART/USART

5These bit switch a Slave interface of the UART/USART 5 unit and an error response circuit.


0: enables a Slave interface[8] UART/USART



















4.1.9 DSX0SELDefault Slave AXI_0 register

Address Base address + 0x60 (h)Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16NameR/WInitial valueBit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Name

Reserved

AC

P

XS

RA

M

XD

MA

C

DD

R3

3DG

E (3

D

Gra

phic

Dis

play

/Cap

-tu

re/W

rite-

R/W - RW RW RW RW RW RWInitial value - 0 0 0 1 0 0

Bit field no. Bit field name Description[31:6 Reserved Reserved[5] ACP These bit switch a Slave interface of the ACP unit and an error response

circuit.


0: enables a Slave interface[4] XSRAM These bit switch a Slave interface of the XSRAM unit and an error

response circuit.


0: enables a Slave interface[3] XDMAC These bit switch a Slave interface of the XDMAC unit and an error

response circuit.


0: enables a Slave interface[2] DDR3 These bit switch a Slave interface of the DDR3 unit and an error response

circuit.


0: enables a Slave interface[1] 3DGE (3D

Graphic Engine)

These bit switch a Slave interface of the 3DGE (3D Graphic Engine) unit and an error response circuit.


0: enables a Slave interface[05] Display/Cap-

ture/WriteThese bit switch a Slave interface of the Display/Capture/Write unit and an error response circuit.





Chapter 5: External Bus InterfaceThis chapter describes all registers of the External Bus Interface unit.

Table 5-1: Register Overview

Base Address Register Address Register Name Register Description3C40_0000 Base address + 0000h MODE0 Mode Register 0

Base address + 0004h MODE1 Mode Register 1Base address + 0008h MODE2 Mode Register 2Base address + 0020h TIM0 Timing Register 0Base address + 0024h TIM1 Timing Register 1Base address + 0028h TIM2 Timing Register 2Base address + 0040h AREA0 Area Register 0 Base address + 0044h AREA1 Area Register 1Base address + 0048h AREA2 Area Register 2





5.1.1 MODE0 ... MODE2Mode Register 0 ... 2.


[31:7] Reserved - - -

[6] RDY RW 0 READY MODESet this bit to '1' to enable a handshake sig-nal with a low-speed peripheral that uses a READY signal.The READY signal must change to 'L' between the falling edge of ChipSelect and the falling edge of the read/write strobe sig-nal.Set this bit to '0' when a device such as an SRAM memory which doesn't use the READY signal is accessed.

0: READY mode OFF

1: READY mode ON The function is not applicable to RDY-/BUSY signal of Flash Memory.

[5] PAGE RW 0 PAGE access modeThis bit controls the NOR Flash page access mode.In NOR Flash page access mode, the first address cycle is issued according to the setting of the First Read Address Cycle (FRADC).After that, accesses are continuously exe-cuted until the 16 bytes boundary is reached, according to the setting of the Read Access Cycle (RACC).When this mode is selected, set RBMON to '0' and the Read Address Cycle (RADC) to '0'.

0: NOR flash page access mode OFF

1: NOR flash page access mode ON




5.1.2 TIM0...TIM2 Timing Register 0 ...2

This register is used to configure the read/write characteristics for flash memory.

If a reserved value is set to a bitfield, the correct response of Enable Blank Check (EBC) is notguaranteed. If in NAND flash mode, the timing of WEX and REX is set via the timing register like WEXand OEX.

[4] NAND RW 0 NAND flash mode.This bit controls the mode to connect NAND Flash.To enable the access to NAND Flash, this bit must be set to '1'.In NAND Flash mode, the corresponding MCSX is fixed to 'L', and NAND Flash dedi-cated pin is used in accesses after this.Reset this bit to '0' if NAND is not used, the CSX is fixed to 'H' and the NAND Flash is kept in a power saving state.

0: NAND flash mode OFF

1: NAND flash mode ON

[1:0] WIDTH RW 0 Specifies the data bit width of a connected device.

0: 8bit (NAND flash only)

1: 16bit

2: 32bit

3: ReservedNote that if this bit is set to '11' (reserved) the enable blank check (EBC) may function incorrectly.


[31:28] WIDLC RW 0 Write Idle Cycle.These bits set the number of idle cycles after write accessing.Specify 2 or greater value, when RDY Bit is set to '1'.'0' : 1 cycle (initial value)...'15' : 16 cycles





[27:24] WWEC RW 5 Write Enable Cycle.These bits set the number of cycles for write enable assertion.The setting of these bits also affects the MDQM (byte mask signal).'0' : 1 cycle...'5' : 6 cycles...'14' : 15 cycles'15' : Reserved

[23:20] WADC RW 5 These bits set the number of setup cycles of the write address.The address is output for the cycles set in these bits, but the write enable is not asserted during such cycles.Specify 10 to use a low-speed device with Ready function.'0' : 1 cycle...'5' : 6 cycles...'14' : 15 cycles'15' : Reserved

[19:16] WACC RW 15 Write Access Cycle.These bits set the number of cycles neces-sary for write access.The address is not changed during the cycles specified in these bits.The value must be greater than the sum of the Address Setup Cycle (WADC) and the Write Enable Cycle (WWEC).'0' : Reserved'1 : Reserved'2' : 3 cycles...'15' : 16 cycles





[15:12] RIDLC RW 15 Read Idle Cycle.These bits set the number of idle cycles after the read access.The bits are used to avoid data collision caused by a write access immediately after the read access.Specify 15 when a low-speed device with Ready function is used.'0' : 1 cycle...'15' : 16 cycles

[11:8] FRADC RW 0 First Read Address Cycle.These bits are used exclusively for the set-ting of NOR Flash that supports the page mode access.The bits set the initial latency of the address in the read access of the Flash.The address is held during the specified cycles only in the first accessing.After that, accesses are performed accord-ing to the number of cycles set in RACC.In the page mode access, MCSX and MOEX are asserted at the same time.When any value other than '0' is set in these bits, specify '0' in the RADC (Read Address Setup Cycle).'0' : 0 cycles (initial value)...'15' : 15 cycles

[7:4] RADC RW 0 Read Address Setup cycle.These bits set the number of setup cycles of the read address.In the read address setup cycles, MCSX and the address is asserted, but MOEX is not asserted.When '0' is selected, MOEX and MCSX are asserted at the same time.'0' : 0 cycles (initial value)...'15' : 15 cycles





5.1.3 AREA0 ...AREA2Area Register 0 ... 2.

If a reserved value is set to a bitfield and /or the unused MEM_XCS[n] is accessed, the correct responseof Enable Blank Check (EBC) is not guaranteed.

[3:0] RACC RW 15 Read Access Cycle.These bits set necessary cycles for read access.The address is not changed during the cycles specified in these bits, and data is fetched in the final cycle.Specify 15 to use a low-speed device with Ready function.'0' : 0 cycles...'15' : 16 cycles (initial value)


[31:23] Reserved - - -





[22:16] MASK RW 0x7F Address mask.These bits set the mask value of the value set in ADDR.The MEMory Controller masks the ADDR and internal bus address (masked when '1' is set) according the specified mask and compares them.When they match, it accesses MCSX signal. [22:16] mask addresses [26:20] respectively.Example :ADDR = '00001000'MASK = '0000011'When to be selected :Internal bus address (address of the external I/F) AD = 0x10900000Masking :ADDR and (!MASK) = '00001000'AD [27:20] and (!MASK) = '00001000' ... Match. The device is selected.When not to be selected :Internal bus address (address of the external I/F) AD = 0x10c00000Masking :ADDR and (!MASK) = '00001000'AD [27:20] and (!MASK) = '00001100' ... Not match. The device is not selected.

The masking selects the size of the region.In the example, 0x10800000?0x10b00000 (4MB) are selected.The bits for which '1' is specified in masking are lost in the mask processing.The bits are invalidated even they have been set in ADDR.If the LSB in the example is '1' (ADDR = '00001001'), the same address field is selected since it is invalidated in the masking.The following shows relations between mask set-tings and the sizes of address fields :'0000000' : 1MB '0000111' : 8MB'0000001' : 2MB'0001111' : 16MB'0000011' : 4MB'0011111' : 32MBNote: Each address field must not overlap.

[15:8] Reserved - - -





[7:0] ADDR RW 0 Address.These bits specify addresses to set the corre-sponding MCSX region.The addresses are those in the fixed 256MB area assigned to the SRAM/Flash interface.Value equivalent to part of the addresses [27:20] must be defined.




Chapter 6: DDR Memory ControllerThis chapter describes all registers of the DDR Memory Controller unit.

Table 6-1: Register Overview Base Address Register Address Register Name Register Description

3840_0000 Base address + 0400h REG_STR This register maintains status information which is output by the Memory Controller.

Base address + 0404h REG_MCC This register controls the signal output to the Memory Controller.

Base address + 0408h REG_RST This register controls the reset of each macro.Base address + 040Ch REG_PWR0 This register is used to suspend the operation of

I/O cells.Base address + 0410h REG_PWR1 This register can suspend an I/O cells driver or

receiver operation, as well as its ZQ bias.Base address + 0414h REG_INIT0 This register sets the output timing for com-

mands in DDR2 mode.Base address + 0418h REG_INIT1 This register sets the output timing for com-

mands in DDR2 mode.Base address + 041Ch REG_INIT2 This register initializes each macro.Base address + 0420h REG_INIT3Base address + 0424h REG_INIT4 This register initializes each unitBase address + 0428h REG_INIT5 This register is used to initialize each macro.Base address + 042Ch REG_TDS0 This register can set each Delay value of

DQDQS macro0. Base address + 0430h REG_TDS1 This register can set each Delay value of

DQDQS macro1.Base address + 0434h REG_TDS2 This register can set each Delay value of

DQDQS macro2.Base address + 0438h REG_TDS3 This register can set each Delay value of

DQDQS macro3.Base address + 043Ch REG_TDS4 This register can set each Delay value of

DQDQS macro4.Base address + 0440h REG_UP Update can do the PZQ initial calibration result

via this register.Base address + 0000h MCR_0Base address + 0004h MCR_1Base address + 0008h MCR_2Base address + 000Ch MCR_3Base address + 0010h MCR_4Base address + 0014h MCR_5Base address + 0018h MCR_6Base address + 001Ch MCR_7Base address + 0020h MCR_8Base address + 0024h MCR_9Base address + 0028h MCR_10Base address + 002Ch MCR_11Base address + 0030h MCR_12Base address + 0034h MCR_13Base address + 0038h MCR_14Base address + 003Ch MCR_15Base address + 0040h MCR_16Base address + 0044h MCR_17Base address + 0048h MCR_18Base address + 004Ch MCR_19Base address + 0050h MCR_20



3840_0000 Base address + 0054h MCR_21Base address + 0058h MCR_22Base address + 005Ch MCR_23Base address + 0060h MCR_24Base address + 0064h MCR_25Base address + 0068h MCR_26Base address + 006Ch MCR_27Base address + 0070h MCR_28Base address + 0074h MCR_29Base address + 0078h MCR_30Base address + 007Ch MCR_31

Base address + 0080h MCR_32



Base address + 008Ch MCR_35





Base address + 00A0h MCR_40



Base address + 00ACh MCR_43

Base address + 00B0h MCR_44



Base address + 00BCh MCR_47

Base address + 00CCh MCR_51

Base address + 00DCh MCR_55

Base address + 00E8h MCR_58

Base address + 00F8h MCR_62

Base address + 00FCh MCR_63














Table 6-1: Register Overview (Continued)Base Address Register Address Register Name Register Description



3840_0000 Base address + 0134h MCR_77











Table 6-1: Register Overview (Continued)Base Address Register Address Register Name Register Description





6.1.1 REG_STR

This register maintains status information output from Memory Controller.

Address 3840_0400Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Reserved r_data_byte_disableR/W R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R/W0 R R R RInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Name

Reserved r_port_busy Reserved

r_refresh_in_

pro-cess

r_controller_busy

Reserved

R/W R/W0 R/W0 R/W0 R R R R R R/W0 R/W0 R/W0 R R R/W0 R/W0 R/W0Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit[3] r_controller_busyMemory controller's busy state is shown.0 not busy1 busy

Bit[4] r_refresh_in_processRefreshing SDRAM is shown.0 not executing a refresh command.1 executing a refresh command.

Bit[12:8] r_port_busyThe busy state of the port is shown. Each bit of this parameter corresponds to each AXI port.0 not busy1 busy

Bit[19:16] r_data_byte_disableThe effective byte lane of the data bus is shown.0 enable1 disable




6.1.2 REG_MCC

This register can control the signal output to Memory Controller.

Address 3840_0404Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Reservedr_mpr_mask

Reserved r_axiy_awcobuf

R/WR0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R/WR0/W0

R0/W0

R0/W0

R/W R/W R/W R/W R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Reservedr_dfi_init_co

mp

R/WR0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R/W1

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit[0] r_dfi_init_compPlease change this bit to "1" (after completing the initialization sequence) before issuing the first command.

0 DFI initialization is not complete

1 DFI initialization is completeBit[20:16] r_axiy_awcobuf

Please set 11111 to this bitBit[24] r_mpr_mask

It mask the commands output from Memory Controller when Gate training for DDR2 mode. 0 Do not mask1 Mask




6.1.3 REG_RST

This register can control reset of PHY.

Address 3840_0408Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Reservedrx_soft

rstxrx_pzq

rstxrx_dllr

stx

R/WR0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R/W R/W R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name Reservedrx_rstx_pzq

rx_rstx_dqdq

s

rx_rstx_cmd

rx_rstx_ck

R/WR0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R/W R/W R/W R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit[0] rx_rstx_ckReset of PHY can be controlled by this bit. 0 Reset1 Release

Bit[1] rx_rstx_cmdReset of PHY can be controlled by this bit. 0 Reset1 Release

Bit[2] rx_rstx_dqdqsReset of PHY can be controlled by this bit. 0 Reset1 Release

Bit[3] rx_rstx_pzqReset of PHY can be controlled by this bit. 0 Reset1 Release

Bit[16] rx_dllrstxReset for DLL of PHY can be controlled by this bit. 0 Reset1 Release

Bit[17] rx_pzqrstxReset for the calibration circuit of PHYcan be controlled by this bit. 0 Reset1 Release

Bit[18] rx_softrstxReset for the read counter of PHY can be controlled by this bit. 0 Reset1 Release




6.1.4 REG_PWR0

This register can do Driver suspend of I/O. I/O becomes Hi-Z if Driver is done in Suspend, and the inputof SDRAM becomes irregular.

Address 3840_ 040CBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Reserved r_suspd_cmd[23:16]

R/WR0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R/W R/W R/W R/W R/W R/W R/W R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Name r_suspd_cmd[15:0]R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit[0] r_suspd_cmd[0]Driver suspend of I/O for MA0 can control by this bit. 0 Enable1 Suspend


















Bit[15] r_suspd_cmd[15]Driver suspend of I/O for MBA0 can control by this bit. 0 Enable1 Suspend



Bit[18] r_suspd_cmd[18]Driver suspend of I/O for MXWE can control by this bit. 0 Enable1 Suspend

Bit[19] r_suspd_cmd[19]Driver suspend of I/O for MXCAS can control by this bit. 0 Enable1 Suspend

Bit[20] r_suspd_cmd[20]Driver suspend of I/O for MXRAS can control by this bit. 0 Enable1 Suspend




Limitations

It is reserved that this bit is changed excluding the self-refresh mode.

Do not write "1" in Bit23 of this register.

Bit[21] r_suspd_cmd[21]Driver suspend of I/O for MXCS can control by this bit. 0 Enable1 Suspend

Bit[22] r_suspd_cmd[22]Driver suspend of I/O for MODT can control by this bit. 0 Enable1 Suspend

Bit[23] r_suspd_cmd[23]Driver suspend of I/O for MCKE can control by this bit. 0 Enable1 Suspend Prohibition




6.1.5 REG_PWR1

This register can suspend an I/O cells driver or receiver operation, as well as its ZQ bias.

An I/O cell switches to Hi-Z if its driver is suspended and input from a DRAM is blocked.

The DQS, DQ I/O, and Loop Back I/O current can be reduced by suspending an I/O cells receiver.

Therefore, read accesses can then not be executed in this case.

The ZQ bias I/O current can be reduced by suspending the ZQ bias I/O cell.

Note however, that a PZQ code update can then not be done.

Address 3840_0410Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name Reservedr_susp_lbio_

3

r_susp_lbio_

2

r_susp_lbio_

1

r_susp_lbio_

0

R/WR0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R/W R/W R/W R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Namer_suspr_dq_

3

r_suspr_dq_

2

r_suspr_dq_

1

r_suspr_dq_

0

r_suspd_dq_

3

r_suspd_dq_

2

r_suspd_dq_

1

r_suspd_dq_

0Reserved

r_suspd_ck

R/W R/W R/W R/W R/W R/W R/W R/W R/WR0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R0/W0

R/W

Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit[0] r_suspd_ckDriver suspend of MCK?MXCK can control by this bit. 0 Enable1 Suspend

Bit[8] r_suspd_dq_0Driver suspend of MDQ0~MDQ7?MDM0?MDQS0?MXDQS0 can control by this bit. 0 Enable1 Suspend




Bit[12] r_suspr_dq_0Receiver suspend of MDQ0~MDQ7?MDQS0?MXDQS0 can control by this bit. 0 Enable1 Suspend




Limitations

Except the case of 16bit SDRAM x1 connection, it is prohibited that this bit is changed excluding theself-refresh mode.In case of 16bit SDRAM x1 connection, set this bit as follow,

bit[11:10]=11, bit[15:14]=11, bit[19:18]=11 at “11.3.1.1 Initialization procedure”.




Bit[16] r_susp_lbio_0Receiver suspend of LoopBack I/O 0 can control by this bit. 0 Enable1 Suspend







6.1.6 REG_INIT0

This register sets the output timing for commands in DDR2 mode.

It is fixed for DDR3 mode (see below).

Set this register before releasing a reset via the REG_RST register.

Address 3840_0414Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Name r_cmd_lat15 r_cmd_lat14 r_cmd_lat13 r_cmd_lat12 r_cmd_lat11 r_cmd_lat10 r_cmd_lat09 r_cmd_lat08R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Name r_cmd_lat07 r_cmd_lat06 r_cmd_lat05 r_cmd_lat04 r_cmd_lat03 r_cmd_lat02 r_cmd_lat01 r_cmd_lat00R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WInitial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit[1:0] r_cmd_lat00Please set 00 to this bit. Do not set other values.



















Limitations

Fix it before releasing each reset by REG_RST register (3840_0408h).

Do not change the value for other periods.

6.1.7 REG_INIT1

This register sets the output timing for commands in DDR2 mode.

It is fixed for DDR3 mode (see below).

Set this register before releasing a reset via the REG_RST register.

Do not change this register at any other time.

Limitations

Fix it before releasing each reset by REG_RST register (3840_0408h).

Do not change the value for other periods.

Address 3840_0418Bit 31 30 29 28 27 26 25

MB86R12 ’Emerald-P’ MB86R12 ‘Emerald-P’ · Revised Oct. 31, 2012...

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