MAX 8724E

General DescriptionThe MAX1908/MAX8724 highly integrated, multichemistrybattery-charger control ICs simplify the construction ofaccurate and efficient chargers. These devices use ana-log inputs to control charge current and voltage, and canbe programmed by the host or hardwired. The MAX1908/MAX8724 achieve high efficiency using a buck topologywith synchronous rectification.

The MAX1908/MAX8724 feature input current limiting.This feature reduces battery charge current when theinput current limit is reached to avoid overloading the ACadapter when supplying the load and the battery chargersimultaneously. The MAX1908/MAX8724 provide outputsto monitor current drawn from the AC adapter (DC inputsource), battery-charging current, and the presence ofan AC adapter. The MAX1908’s conditioning charge fea-ture provides 300mA to safely charge deeply dischargedlithium-ion (Li+) battery packs.

The MAX1908 includes a conditioning charge featurewhile the MAX8724 does not.

The MAX1908/MAX8724 charge two to four series Li+cells, providing more than 5A, and are available in aspace-saving 28-pin thin QFN package (5mm × 5mm).An evaluation kit is available to speed designs.

ApplicationsNotebook and Subnotebook Computers

Personal Digital Assistants

Hand-Held Terminals

Features♦ ±0.5% Output Voltage Accuracy Using Internal

Reference (0°C to +85°C)

♦ ±4% Accurate Input Current Limiting

♦ ±5% Accurate Charge Current

♦ Analog Inputs Control Charge Current andCharge Voltage

♦ Outputs for MonitoringCurrent Drawn from AC AdapterCharging CurrentAC Adapter Presence

♦ Up to 17.6V Battery-Voltage Set Point

♦ Maximum 28V Input Voltage

♦ >95% Efficiency

♦ Shutdown Control Input

♦ Charges Any Battery ChemistryLi+, NiCd, NiMH, Lead Acid, etc.

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Low-Cost Multichemistry Battery Chargers

________________________________________________________________ Maxim Integrated Products 1

28 27 26 25 24 23 22

IINP

CSSP

CSSN

DHI

BST

LX DLOV

8 9 10 11 12 13 14

SHDN

ICHG

ACIN

ACOK

REFI

N

ICTL

GND

15

16

17

18

19

20

21

VCTL

BATT

CELLS

CSIN

CSIP

PGND

DLO

7

6

5

4

3

2

1

CCV

CCI

CCS

REF

CLS

LDO

DCIN

MAX1908MAX8724

THIN QFN

TOP VIEW

Pin Configuration

Ordering Information

MAX1908MAX8724

AC ADAPTERINPUT

TO EXTERNALLOAD

LDO

FROM HOST µP

10µH

0.015Ω

BATT+

DCIN

REFIN

VCTL

ICTL

ACIN

ACOK

SHDN

ICHG

IINP

CCV

CCI

CCS

CELLS

LDO

BST

DLOV

DHI

LX

DLO

PGND

CSIP

CSINBATT

REF CLS GND

CSSP CSSN

0.01Ω

Minimum Operating Circuit

19-2764; Rev 2; 7/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX1908ETI -40°C to +85°C 28 Thin QFN

MAX8724ETI -40°C to +85°C 28 Thin QFN

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ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3V, VVCTL = VICTL = 0.75 x VREFIN, CELLS = float, CLS =REF, VBST - VLX = 4.5V, ACIN = GND = PGND = 0, CLDO = 1µF, LDO = DLOV, CREF = 1µF; CCI, CCS, and CCV are compensatedper Figure 1a; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

DCIN, CSSP, CSSN, ACOK to GND.......................-0.3V to +30VBST to GND............................................................-0.3V to +36VBST to LX..................................................................-0.3V to +6VDHI to LX...................................................-0.3V to (VBST + 0.3V)LX to GND .................................................................-6V to +30VBATT, CSIP, CSIN to GND .....................................-0.3V to +20VCSIP to CSIN or CSSP to CSSN or PGND

to GND...............................................................-0.3V to +0.3VCCI, CCS, CCV, DLO, ICHG,

IINP, ACIN, REF to GND...........................-0.3V to (VLDO + 0.3V)DLOV, VCTL, ICTL, REFIN, CELLS, CLS,

LDO, SHDN to GND .................................................-0.3V to +6VDLOV to LDO.........................................................-0.3V to +0.3VDLO to PGND .........................................-0.3V to (VDLOV + 0.3V)LDO Short-Circuit Current...................................................50mAContinuous Power Dissipation (TA = +70°C)

28-Pin Thin QFN (5mm × 5mm) (derate 20.8mW/°C above +70°C) .........................1666.7mW

Operating Temperature Range ..........................-40°C to +85°CJunction Temperature ......................................................+150°CStorage Temperature Range .............................-60°C to +150°CLead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CHARGE VOLTAGE REGULATION

VVCTL = VREFIN (2, 3, or 4 cells) -0.5 +0.5

VVCTL = VREFIN / 20 (2, 3, or 4 cells) -0.5 +0.5 Battery Regulation VoltageAccuracy

VVCTL = VLDO (2, 3, or 4 cells) -0.5 +0.5

%

VCTL Default Threshold VVCTL rising 4.0 4.1 4.2 V REFIN Range (Note 1) 2.5 3.6 V REFIN Undervoltage Lockout VREFIN falling 1.20 1.92 V CHARGE CURRENT REGULATION

CSIP-to-CSIN Full-Scale Current-Sense Voltage

VICTL = VREFIN 71.25 75 78.75 mV

VICTL = VREFIN -5 +5

VICTL = VREFIN x 0.6 -5 +5

VICTL = VLDO -6 +6 Charging Current Accuracy

MAX8724 only: VICTL = VREFIN x 0.058 -33 +33

%

ICTL Default Threshold VICTL rising 4.0 4.1 4.2 V BATT/CSIP/CSIN Input VoltageRange

0 19 V

VDCIN = 0 or VICTL = 0 or SHDN = 0 1 CSIP/CSIN Input Current Charging 400 650

µA

Cycle-by-Cycle Maximum CurrentLimit

IMAX RS2 = 0.015Ω 6.0 6.8 7.5 A

ICTL Power-Down ModeThreshold Voltage

VICTL rising REFIN /

100 REFIN /

55 REFIN /

33 V

VVCTL = VICTL = 0 or 3V -1 +1 ICTL, VCTL Input Bias Current VDCIN = 0, VVCTL = VICTL= VREFIN = 5V -1 +1 µA

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ELECTRICAL CHARACTERISTICS (continued)(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3V, VVCTL = VICTL = 0.75 x VREFIN, CELLS = float, CLS =REF, VBST - VLX = 4.5V, ACIN = GND = PGND = 0, CLDO = 1µF, LDO = DLOV, CREF = 1µF; CCI, CCS, and CCV are compensatedper Figure 1a; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)


VDCIN = 5V, VREFIN = 3V -1 +1 REFIN Input Bias Current VREFIN = 5V -1 +1

µA

ICHG Transconductance GICHG VCSIP - VCSIN = 45mV 2.7 3 3.3 µA/mV

VCSIP - VCSIN = 75mV -6 +6

VCSIP - VCSIN = 45mV -5 +5 ICHG Accuracy VCSIP - VCSIN = 5mV -40 +40

%

ICHG Output Current VCSIP - VCSIN = 150mV, VICHG = 0 350 µA

ICHG Output Voltage VCSIP - VCSIN = 150mV, ICHG = float 3.5 V INPUT CURRENT REGULATION

CSSP-to-CSSN Full-ScaleCurrent-Sense Voltage

72 75 78 mV

VCLS = VREF -4 +4 Input Current-Limit Accuracy VCLS = VREF / 2 -7.5 +7.5

%

CSSP, CSSN Input VoltageRange

8 28 V

VDCIN = 0 0.1 1 CSSP, CSSN Input Current VCSSP = VCSSN = VDCIN > 8V 350 600 µA

CLS Input Range 1.6 REF V CLS Input Bias Current VCLS = 2V -1 +1 µA

IINP Transconductance GIINP VCSSP - VCSSN = 75mV 2.7 3 3.3 µA/mV

VCSSP - VCSSN = 75mV -5 +5 IINP Accuracy VCSSP - VCSSN = 37.5mV -7.5 +7.5

%

IINP Output Current VCSSP - VCSSN = 150mV, VIINP = 0 350 µA

IINP Output Voltage VCSSP - VCSSN = 150mV,VIINP = float 3.5 V SUPPLY AND LDO REGULATOR

DCIN Input Voltage Range VDCIN 8 28 V VDCIN falling 7 7.4 DCIN Undervoltage-Lockout Trip

Point

VDCIN rising 7.5 7.85 V

DCIN Quiescent Current IDCIN 8.0V < VDCIN < 28V 3.2 6 mA

VBATT = 19V, VDCIN = 0 1 BATT Input Current IBATT VBATT = 2V to 19V, VDCIN = 19.3V 200 500 µA

LDO Output Voltage 8V < VDCIN < 28V, no load 5.25 5.4 5.55 V LDO Load Regulation 0 < ILDO < 10mA 34 100 mV

LDO Undervoltage-Lockout TripPoint

VDCIN = 8V 3.20 4 5.15 V

REFERENCE

REF Output Voltage 0 < IREF < 500µA 4.072 4.096 4.120 V

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REF Undervoltage-Lockout TripPoint

VREF falling 3.1 3.9 V

TRIP POINTS

BATT Power-Fail Threshold VDCIN falling, referred to VCSIN 50 100 150 mV

BATT Power-Fail ThresholdHysteresis

200 mV

ACIN Threshold ACIN rising 2.007 2.048 2.089 V ACIN Threshold Hysteresis 0.5% of REF 20 mV

ACIN Input Bias Current VACIN = 2.048V -1 +1 µA

SWITCHING REGULATOR

DHI Off-Time VBATT = 16V, VDCIN = 19V,VCELLS = VREFIN

0.36 0.4 0.44 µs

DHI Minimum Off-Time VBATT = 16V, VDCIN = 17V,VCELLS = VREFIN

0.24 0.28 0.33 µs

DHI Maximum On-Time 2.5 5 7.5 ms

DLOV Supply Current IDLOV DLO low 5 10 µA

BST Supply Current IBST DHI high 6 15 µA

BST Input Quiescent Current VDCIN = 0, VBST = 24.5V,VBATT = VLX = 20V

0.3 1 µA

LX Input Bias Current VDCIN = 28V, VBATT = VLX = 20V 150 500 µA

LX Input Quiescent Current VDCIN = 0, VBATT = VLX = 20V 0.3 1 µA

DHI Maximum Duty Cycle 99 99.9 % Minimum Discontinuous-ModeRipple Current

0.5 A

Battery Undervoltage ChargeCurrent

VBATT = 3V per cell (RS2 = 15mΩ),MAX1908 only, VBATT rising

150 300 450 mA

CELLS = GND, MAX1908 only, VBATT rising 6.1 6.2 6.3

CELLS = float, MAX1908 only, VBATT rising 9.15 9.3 9.45 Battery Undervoltage CurrentThreshold

CELLS = VREFIN, MAX1908 only, VBATT rising 12.2 12.4 12.6

V

DHI On-Resistance High VBST - VLX = 4.5V, IDHI = +100mA 4 7 Ω DHI On-Resistance Low VBST - VLX = 4.5V, IDHI = -100mA 1 3.5 Ω DLO On-Resistance High VDLOV = 4.5V, IDLO = +100mA 4 7 Ω DLO On-Resistance Low VDLOV = 4.5V, IDLO = -100mA 1 3.5 Ω ERROR AMPLIFIERS

GMV Amplifier Transconductance GMV V V C T L = V LD O, V BAT T = 16.8V ,C E LLS = V RE F IN

0.0625 0.125 0.2500 µA/mV

GMI Amplifier Transconductance GMI VICTL = V RE F IN , VCSIP - VCSIN = 75mV 0.5 1 2.0 µA/mV

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GMS Amplifier Transconductance GMS VCLS = VREF, VCSSP - VCSSN = 75mV 0.5 1 2.0 µA/mV

CCI, CCS, CCV Clamp Voltage 0.25V < VCCV,CCS,CCI < 2V 150 300 600 mV

LOGIC LEVELS

CELLS Input Low Voltage 0.4 V

CELLS Input Float Voltage CELLS = float (VREFIN/ 2) -0.2V

VREFIN/ 2

( V R E F IN / 2) + 0.2V

V

CELLS Input High Voltage VREFIN- 0.4V

V

CELLS Input Bias Current CELLS = 0 or VREFIN -2 +2 µA

ACOK AND SHDN

ACOK Input Voltage Range 0 28 V ACOK Sink Current V ACOK = 0.4V, VACIN = 3V 1 mA

ACOK Leakage Current V ACOK = 28V, VACIN = 0 1 µA

SHDN Input Voltage Range 0 LDO V V SHDN = 0 or VLDO -1 +1 SHDN Input Bias Current VDCIN = 0, V SHDN = 5V -1 +1

µA

SHDN Threshold V SHDN falling 22 23.5 25 % of

VREFIN

SHDN Threshold Hysteresis 1 % ofVREFIN

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ELECTRICAL CHARACTERISTICS(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3V, VVCTL = VICTL = 0.75 x VREFIN, CELLS = FLOAT, CLS =REF, VBST - VLX = 4.5V, ACIN = GND = PGND = 0, CLDO = 1µF, LDO = DLOV, CREF = 1µF; CCI, CCS, and CCV are compensatedper Figure 1a; TA = -40°C to +85°C, unless otherwise noted.) (Note 2)


CHARGE VOLTAGE REGULATION

VVCTL = VREFIN (2, 3, or 4 cells) -0.6 +0.6

VVCTL = VREFIN / 20 (2, 3, or 4 cells) -0.6 +0.6 Battery Regulation VoltageAccuracy

VVCTL = VLDO (2, 3, or 4 cells) -0.6 +0.6

%

REFIN Range (Note 1) 2.5 3.6 V REFIN Undervoltage Lockout VREFIN falling 1.92 V CHARGE CURRENT REGULATION

CSIP-to-CSIN Full-Scale Current-Sense Voltage

VICTL = VREFIN 70.5 79.5 mV

VICTL = VREFIN -6 +6

VICTL = VREFIN × 0.6 -7.5 +7.5

VICTL = VLDO -7.5 +7.5 Charging Current Accuracy

MAX8724 only: VICTL = VREFIN x 0.058 -33 +33

%

BATT/CSIP/CSIN Input VoltageRange

0 19 V

VDCIN = 0 or VICTL = 0 or SHDN = 0 1 CSIP/CSIN Input Current Charging 650

µA

Cycle-by-Cycle Maximum CurrentLimit

IMAX RS2 = 0.015Ω 6.0 7.5 A

ICTL Power-Down ModeThreshold Voltage

VICTL rising REFIN /

100 REFIN /

33 V

ICHG Transconductance GICHG VCSIP - VCSIN = 45mV 2.7 3.3 µA/mV

VCSIP - VCSIN = 75mV -7.5 +7.5

VCSIP - VCSIN = 45mV -7.5 +7.5 ICHG Accuracy VCSIP - VCSIN = 5mV -40 +40

%

INPUT CURRENT REGULATION

CSSP-to-CSSN Full-ScaleCurrent-Sense Voltage

71.25 78.75 mV

VCLS = VREF -5 +5 Input Current-Limit Accuracy VCLS = VREF / 2 -7.5 +7.5

%

CSSP, CSSN Input VoltageRange

8 28 V

VDCIN = 0 1 CSSP, CSSN Input Current VCSSP = VCSSN = VDCIN > 8V 600

µA

CLS Input Range 1.6 REF V IINP Transconductance GIINP VCSSP - VCSSN = 75mV 2.7 3.3 µA/mV

VCSSP - VCSSN = 75mV -7.5 +7.5 IINP Accuracy VCSSP - VCSSN = 37.5mV -7.5 +7.5 %

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ELECTRICAL CHARACTERISTICS (continued)(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3V, VVCTL = VICTL = 0.75 x VREFIN, CELLS = FLOAT, CLS =REF, VBST - VLX = 4.5V, ACIN = GND = PGND = 0, CLDO = 1µF, LDO = DLOV, CREF = 1µF; CCI, CCS, and CCV are compensatedper Figure 1a; TA = -40°C to +85°C, unless otherwise noted.) (Note 2)


SUPPLY AND LDO REGULATOR

DCIN Input Voltage Range VDCIN 8 28 V DCIN Quiescent Current IDCIN 8V < VDCIN < 28V 6 mA

VBATT = 19V, VDCIN = 0 1 BATT Input Current IBATT VBATT = 2V to 19V, VDCIN = 19.3V 500 µA

LDO Output Voltage 8V < VDCIN < 28V, no load 5.25 5.55 V LDO Load Regulation 0 < ILDO < 10mA 100 mV

REFERENCE

REF Output Voltage 0 < IREF < 500µA 4.065 4.120 V TRIP POINTS

BATT Power-Fail Threshold VDCIN falling, referred to VCSIN 50 150 mV

ACIN Threshold VACIN rising 2.007 2.089 V SWITCHING REGULATOR

DHI Off-Time VBATT = 16V, VDCIN = 19V,VCELLS = VREFIN

0.35 0.45 µs

DHI Minimum Off-Time VBATT = 16V, VDCIN = 17V,VCELLS = VREFIN

0.24 0.33 µs

DHI Maximum On-Time 2.5 7.5 ms

DHI Maximum Duty Cycle 99 % Battery Undervoltage ChargeCurrent

VBATT = 3V per cell (RS2 = 15mΩ),MAX1908 only, VBATT rising

150 450 mA

CELLS = GND, MAX1908 only, VBATT rising 6.09 6.30

CELLS = float, MAX1908 only, VBATT rising 9.12 9.45 Battery Undervoltage CurrentThreshold

CELLS = VREFIN, MAX1908 only, VBATT rising 12.18 12.6

V

DHI On-Resistance High VBST - VLX = 4.5V, IDHI = +100mA 7 Ω DHI On-Resistance Low VBST - VLX = 4.5V, IDHI = -100mA 3.5 Ω DLO On-Resistance High VDLOV = 4.5V, IDLO = +100mA 7 Ω DLO On-Resistance Low VDLOV = 4.5V, IDLO = -100mA 3.5 Ω ERROR AMPLIFIERS

GMV Amplifier Transconductance GMV V V C T L = V LD O, V BAT T = 16.8V ,C E LLS = V RE F IN

0.0625 0.250 µA/mV

GMI Amplifier Transconductance GMI VICTL = V RE F IN , VCSIP - VCSIN = 75mV 0.5 2.0 µA/mV

GMS Amplifier Transconductance GMS VCLS = VREF, VCSSP - VCSSN = 75mV 0.5 2.0 µA/mV

CCI, CCS, CCV Clamp Voltage 0.25V < VCCV,CCS,CCI < 2V 150 600 mV

LOGIC LEVELS

CELLS Input Low Voltage 0.4 V

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ELECTRICAL CHARACTERISTICS (continued)(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3V, VVCTL = VICTL = 0.75 x VREFIN, CELLS = FLOAT, CLS =REF, VBST - VLX = 4.5V, ACIN = GND = PGND = 0, CLDO = 1µF, LDO = DLOV, CREF = 1µF; CCI, CCS, and CCV are compensatedper Figure 1a; TA = -40°C to +85°C, unless otherwise noted.) (Note 2)


CELLS Input Float Voltage CELLS = float (VREFIN/ 2) -0.2V

( V R E F IN / 2) + 0.2V

V

CELLS Input High Voltage VREFIN- 0.4V

V

ACOK AND SHDN

ACOK Input Voltage Range 0 28 V ACOK Sink Current V A COK = 0.4V, VACIN = 3V 1 mA

SHDN Input Voltage Range 0 LDO V

SHDN Threshold V S HDN falling 22 25 % of

VREFIN

Note 1: If both ICTL and VCTL use default mode (connected to LDO), REFIN is not used and can be connected to LDO.Note 2: Specifications to -40°C are guaranteed by design and not production tested.

LOAD-TRANSIENT RESPONSE(BATTERY INSERTION AND REMOVAL)

MAX1908 toc01

1ms/div

IBATT2A/div

VBATT5V/div

VCCI 500mV/divVCCV 500mV/div

ICTL = LDOVCTL = LDO

CCV

CCI

LOAD-TRANSIENT RESPONSE(STEP IN-LOAD CURRENT)

MAX1908 toc02

1ms/div

V_BATT2V/div

V_CCI500mV/div

V_CCS500mV/div

16.8V

0

0LOADCURRENT

5A/div

ADAPTERCURRENT

5A/div

ICTL = LDOCHARGING CURRENT = 3AV_BATT = 16.8VLOAD STEP = 0 TO 4AI_SOURCE LIMIT = 5A

CCI

CCS

CCI

CCS

V_BATT2V/div

0

0

0

CHARGECURRENT

2A/div

LOADCURRENT

5A/div

ADAPTERCURRENT

5A/div

LOAD-TRANSIENT RESPONSE(STEP IN-LOAD CURRENT)

MAX1908 toc03

1ms/divICTL = LDOCHARGING CURRENT = 3AVBATT = 16.8VLOAD STEP = 0 TO 4AI_SOURCE LIMIT = 5A

Typical Operating Characteristics(Circuit of Figure 1, VDCIN = 20V, TA = +25°C, unless otherwise noted.)

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INDUCTORCURRENT

500mA/div

VDCIN10V/div

VBATT500mV/div

LINE-TRANSIENT RESPONSEMAX1908 toc04

10ms/divICTL = LDOVCTL = LDOICHARGE = 3ALINE STEP 18.5V TO 27.5V

-1.0

-0.8

-0.9

-0.6

-0.7

-0.4

-0.5

-0.3

-0.1

-0.2

0

0 2 3 41 5 6 7 98 10

LDO LOAD REGULATION

MAX

1908

toc0

5

LDO CURRENT (mA)

V LDO

ERR

OR (%

)

VLDO = 5.4V

-0.05

-0.03

-0.04

-0.01

-0.02

0.01

0

0.02

0.04

0.03

0.05

8 12 14 1610 18 20 22 2624 28

LDO LINE REGULATION

MAX

1908

toc0

6

VIN (V)

V LDO

ERR

OR (%

)

ILDO = 0VLDO = 5.4V

-0.10

-0.07

-0.08

-0.09

-0.06

-0.05

-0.04

-0.03

-0.02

-0.01

0

0 200100 300 400 500

REF VOLTAGE LOAD REGULATION

MAX

1908

toc0

7

REF CURRENT (µA)

V REF

ERR

OR (%

)

-0.10

-0.04

-0.06

-0.08

-0.02

0

0.02

0.04

0.06

0.08

0.10

-40 10-15 35 60 85

REF VOLTAGE ERROR vs. TEMPERATURE

MAX

1908

toc0

8

TEMPERATURE (°C)

V REF

ERR

OR (%

)

90

00.01 1010.1

EFFICIENCY vs. CHARGE CURRENT

30

10

70

50

100

40

20

80

60

MAX

1908

toc0

9

CHARGE CURRENT (A)

EFFI

CIEN

CY (%

)VBATT = 16V

VBATT = 8V

VBATT = 12V

0

100

50

250

200

150

300

350

450

400

500

0 4 62 8 10 12 14 16 18 20 22

FREQUENCY vs. VIN - VBATT

MAX

1908

toc1

0

(VIN - VBATT) (V)

FREQ

UENC

Y (k

Hz)

ICHARGE = 3AVCTL = ICTL = LDO

3 CELLS

4 CELLS

-0.4

-0.1

-0.3

-0.5

0

0.2

0.3

0.4

0.5

0 1 2 3 4

OUTPUT V/I CHARACTERISTICS

MAX

1908

toc1

1

BATT CURRENT (A)

BATT

VOL

TAGE

ERR

OR (%

)

0.1

-0.2

2 CELLS

3 CELLS

4 CELLS

0

0.02

0.01

0.03

0.06

0.07

0.05

0.04

0.08

0 0.2 0.3 0.4 0.50.1 0.6 0.7 0.8 0.9 1.0

BATT VOLTAGE ERROR vs. VCTLM

AX19

08 to

c12

VCTL/REFIN (%)

BATT

VOL

TAGE

ERR

OR (%

)

4 CELLSREFIN = 3.3VNO LOAD

Typical Operating Characteristics (continued)(Circuit of Figure 1, VDCIN = 20V, TA = +25°C, unless otherwise noted.)

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10 ______________________________________________________________________________________

-1

1

0

3

2

4

5

0 1.00.5 1.5 2.0

CURRENT SETTING ERROR vs. ICTL

MAX

1908

toc1

3

VICTL (V)

CURR

ENT-

SETT

ING

ERRO

R (%

)

VREFIN = 3.3V

0

1.5

1.0

0.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 1.00.5 1.5 2.0 2.5 3.0

ICHG ERROR vs. CHARGE CURRENT

MAX

1908

toc1

4

IBATT (A)

ICHG

(%)

VBATT = 16VVBATT = 12VVBATT = 8V

VREFIN = 3.3V

-40

-30

-20

-10

0

10

20

30

40

0 1 2 3 4

IINP ERROR vs. SYSTEM LOAD CURRENT

MAX

1908

toc1

5

SYSTEM LOAD CURRENT (A)

IINP

ERRO

R (%

) IBATT = 0

-80

-60

-40

-20

0

20

40

60

80

0 0.5 1.0 1.5 2.0

IINP ERROR vs. INPUT CURRENT

MAX

1908

toc1

6

INPUT CURRENT (A)

IINP

ERRO

R (%

)

SYSTEM LOAD = 0

ERROR DUE TO SWITCHING NOISE

Typical Operating Characteristics (continued)(Circuit of Figure 1, VDCIN = 20V, TA = +25°C, unless otherwise noted.)

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Pin Description

PIN NAME FUNCTION

1 DCIN Charging Voltage Input. Bypass DCIN with a 1µF capacitor to PGND.

2 LDO D evi ce P ow er S up p l y. Outp ut of the 5.4V l i near r eg ul ator sup p l i ed fr om D C IN . Byp ass w i th a 1µF cap aci tor to GN D .

3 CLS Source Current-Limit Input. Voltage input for setting the current limit of the input source.

4 REF 4.096V Voltage Reference. Bypass REF with a 1µF capacitor to GND.

5 CCS Input-Current Regulation Loop-Compensation Point. Connect a 0.01µF capacitor to GND.

6 CCI Output-Current Regulation Loop-Compensation Point. Connect a 0.01µF capacitor to GND.

7 CCV Voltage Regulation Loop-Compensation Point. Connect 1kΩ in series with 0.1µF capacitor to GND.

8 SHDN Shutdown Control Input. Drive SHDN logic low to shut down the MAX1908/MAX8724. Use with a thermistor todetect a hot battery and suspend charging.

9 ICHG Charge-Current Monitor Output. ICHG is a scaled-down replica of the charger output current. Use ICHG tomonitor the charging current and detect when the chip changes from constant-current mode to constant-voltage mode. The transconductance of (CSIP - CSIN) to ICHG is 3µA/mV.

10 ACIN AC Detect Input. Input to an uncommitted comparator. ACIN can be used to detect AC-adapter presence.

11 ACOK AC Detect Output. High-voltage open-drain output is high impedance when VACIN is less than VREF / 2.

12 REFIN Reference Input. Allows the ICTL and VCTL inputs to have ratiometric ranges for increased accuracy.

13 ICTL Output Current-Limit Set Input. ICTL input voltage range is VREFIN / 32 to VREFIN. The device shuts down ifICTL is forced below VREFIN / 100. When ICTL is equal to LDO, the set point for CSIP - CSIN is 45mV.

14 GND Analog Ground

15 VCTL Output-Voltage Limit Set Input. VCTL input voltage range is 0 to VREFIN. When VCTL is equal to LDO, the setpoint is (4.2 x CELLS) V.

16 BATT Battery Voltage Input

17 CELLS Cell Count Input. Trilevel input for setting number of cells. GND = 2 cells, float = 3 cells, REFIN = 4 cells.

18 CSIN Output Current-Sense Negative Input

19 CSIP Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN.

20 PGND Power Ground

21 DLO Low-Side Power MOSFET Driver Output. Connect to low-side NMOS gate.

22 DLOV Low-Side Driver Supply. Bypass DLOV with a 1µF capacitor to GND.

23 LX High-Side Power MOSFET Driver Power-Return Connection. Connect to the source of the high-side NMOS.

24 BST High-Side Power MOSFET Driver Power-Supply Connection. Connect a 0.1µF capacitor from LX to BST.

25 DHI High-Side Power MOSFET Driver Output. Connect to high-side NMOS gate.

26 CSSN Input Current-Sense Negative Input

27 CSSP Input Current-Sense Positive Input. Connect a current-sense resistor from CSSP to CSSN.

28 IINP Input-Current Monitor Output. IINP is a scaled-down replica of the input current. IINP monitors the totalsystem current. The transconductance of (CSSP - CSSN) to IINP is 3µA/mV.

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The MAX1908/MAX8724 include all the functions neces-sary to charge Li+ batteries. A high-efficiency synchro-nous-rectified step-down DC-DC converter controlscharging voltage and current. The device also includesinput source current limiting and analog inputs for set-ting the charge current and charge voltage. Controlcharge current and voltage using the ICTL and VCTLinputs, respectively. Both ICTL and VCTL are ratiometricwith respect to REFIN, allowing compatibility with D/Asor microcontrollers (µCs). Ratiometric ICTL and VCTLimprove the accuracy of the charge current and voltageset point by matching VREFIN to the reference of thehost. For standard applications, internal set points forICTL and VCTL provide 3A charge current (with 0.015Ωsense resistor), and 4.2V (per cell) charge voltage.Connect ICTL and VCTL to LDO to select the internal setpoints. The MAX1908 safely conditions overdischargedcells with 300mA (with 0.015Ω sense resistor) until thebattery-pack voltage exceeds 3.1V × number of series-connected cells. The SHDN input allows shutdown froma microcontroller or thermistor.

The DC-DC converter uses external N-channelMOSFETs as the buck switch and synchronous rectifierto convert the input voltage to the required chargingcurrent and voltage. The Typical Application Circuitshown in Figure 1 uses a µC to control charging cur-rent, while Figure 2 shows a typical application withcharging voltage and current fixed to specific valuesfor the application. The voltage at ICTL and the value ofRS2 set the charging current. The DC-DC convertergenerates the control signals for the external MOSFETsto regulate the voltage and the current set by the VCTL,ICTL, and CELLS inputs.

The MAX1908/MAX8724 feature a voltage-regulationloop (CCV) and two current-regulation loops (CCI andCCS). The CCV voltage-regulation loop monitors BATTto ensure that its voltage does not exceed the voltageset by VCTL. The CCI battery current-regulation loopmonitors current delivered to BATT to ensure that itdoes not exceed the current limit set by ICTL. A thirdloop (CCS) takes control and reduces the battery-charging current when the sum of the system load andthe battery-charging input current exceeds the inputcurrent limit set by CLS.

Setting the Battery Regulation VoltageThe MAX1908/MAX8724 use a high-accuracy voltageregulator for charging voltage. The VCTL input adjuststhe charger output voltage. VCTL control voltage canvary from 0 to VREFIN, providing a 10% adjustmentrange on the VBATT regulation voltage. By limiting theadjust range to 10% of the regulation voltage, the exter-nal resistor mismatch error is reduced from 1% to0.05% of the regulation voltage. Therefore, an overallvoltage accuracy of better than 0.7% is maintainedwhile using 1% resistors. The per-cell battery termina-tion voltage is a function of the battery chemistry.Consult the battery manufacturer to determine this volt-age. Connect VCTL to LDO to select the internal defaultsetting VBATT = 4.2V × number of cells, or program thebattery voltage with the following equation:

CELLS is the programming input for selecting cell count.Connect CELLS as shown in Table 1 to charge 2, 3, or 4Li+ cells. When charging other cell chemistries, useCELLS to select an output voltage range for the charger.

The internal error amplifier (GMV) maintains voltage regulation (Figure 3). The voltage error amplifier is compensated at CCV. The component values shown inFigures 1 and 2 provide suitable performance for mostapplications. Individual compensation of the voltage reg-ulation and current-regulation loops allows for optimalcompensation (see the Compensation section).

V CELLS VVVBATT

VCTL

REFIN= × + ×

4 0 4.


12 ______________________________________________________________________________________

Table 1. Cell-Count Programming

CELLS CELL COUNT

GND 2

Float 3

VREFIN 4

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______________________________________________________________________________________ 13

DCIN

LDO

MAX1908MAX8724

CLSREFGND

CELLS

DLOV

AC ADAPTER INPUT8.5V TO 28V

12.6V OUTPUT VOLTAGE

7.5A INPUTCURRENT LIMIT

DHI

D3BST

SMARTBATTERY

HOST

ACIN

D2

R659kΩ

1%R7

19.6kΩ1%

C51µF

VCTL

ICTL

REFIN

ACOK

ICHG

IINP

R81MΩ

R920kΩ

R1010kΩ

C140.1µF

C200.1µF

CCV

C110.1µF

R51kΩ

CCI

CCS

C100.01µF

C90.01µF

C121µF

C12 × 10µF

C131µF

C150.1µF

LX

C161µF

LDO

R1333Ω

CSSP CSSN(FLOAT-THREE CELLS SELECT)

D1RS1

0.01Ω

L110µH

RS20.015Ω

CSIP

CSIN

PGND

DLON1b

N1a

BATT

C422µF

BATT+

R19, R20, R2110kΩ

AVDD/REF

SCL

SDA

TEMP

BATT-

A/D INPUT

A/D INPUT

OUTPUT

D/A OUTPUT

VCC

SCL

SDA

A/D INPUT

GND

PGND GND

TO EXTERNAL LOAD

SHDN

0.1µF 0.1µF

Figure 1. µC-Controlled Typical Application Circuit

Typical Application Circuits

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14 ______________________________________________________________________________________

TO EXTERNAL LOAD

MAX1908MAX8724

CLSREFGND

CELLS

REFIN (4 CELLS SELECT)

DLOV

AC ADAPTERINPUT

8.5V TO 28V

DHI

D3BST

BATTERY

ACIN

D2

LDO

LDO

16.8V OUTPUT VOLTAGE2.5A CHARGE LIMIT

4A INPUT CURRENT LIMIT

R659kΩ

1% R719.6kΩ

1%

R1115kΩ

R1212kΩ

C51µF

C121.5nF

SHDN

ICHG

IINP

R1910kΩ1%

R2010kΩ1%

CCV

C110.1µF

R51kΩ

CCI

CCS

C100.01µF

C90.01µF

C121µF

C12 × 10µF

C131µF

C150.1µF

LX

C161µF

LDO

R1333Ω

CSSP CSSN

RS10.01Ω

L110µH

RS20.015Ω

CSIP

CSIN

PGND

DLON1b

N1a

FROM HOST µP(SHUTDOWN)

N

BATT

GNDPGND

C422µF

BATT+

REFIN

VCTL

DCIN

BATT-

THM

ICTL

R1410.5kΩ1%

R158.25kΩ1%

R168.25kΩ1%

P1

R1719.1kΩ1%

R1822kΩ1%

ACOK

0.01µF 0.01µF

Figure 2. Typical Application Circuit with Fixed Charging Parameters

Typical Application Circuits (continued)

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______________________________________________________________________________________ 15

MAX1908MAX8724

LOGICBLOCK

GMS

SHDN

GND

CLS

CCS

CSSP

CSSN

CSIP

CSIN

ICTL

CCI

BATT

CELLS

CCV

VCTL

23.5%REFIN

GND

DCIN

SRDY

5.4VLINEAR

REGULATOR

1/55

ICTL

REF/2

RDY

4V

CELLSELECTLOGIC

4.096VREFERENCE

LVC

REFIN

CSI

BAT_UV3.1V/CELL

R1LVC

DCIN

LDO

REF

REFIN

ACIN

ACOK

IINP

ICHG

BST

DHI

LX

DLOV

DLO

PGND

MAX1908 ONLY

X75mVREF

LEVELSHIFTER

X75mVREFIN

X400mVREFIN

DC-DCCONVERTER

GMI

GMV

GM

LEVELSHIFTER

N

GM

LEVELSHIFTER

DRIVER

DRIVER

Figure 3. Functional Diagram

Functional Diagram

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The ICTL input sets the maximum charging current. Thecurrent is set by current-sense resistor RS2, connectedbetween CSIP and CSIN. The full-scale differential voltage between CSIP and CSIN is 75mV; thus, for a0.015Ω sense resistor, the maximum charging currentis 5A. Battery-charging current is programmed withICTL using the equation:

The input voltage range for ICTL is VREFIN / 32 toVREFIN. The device shuts down if ICTL is forced belowVREFIN / 100 (min).

Connect ICTL to LDO to select the internal default full-scale charge-current sense voltage of 45mV. Thecharge current when ICTL = LDO is:

where RS2 is 0.015Ω, providing a charge-current setpoint of 3A.

The current at the ICHG output is a scaled-down replicaof the battery output current being sensed across CSIPand CSIN (see the Current Measurement section).

When choosing the current-sense resistor, note that thevoltage drop across this resistor causes further powerloss, reducing efficiency. However, adjusting ICTL toreduce the voltage across the current-sense resistorcan degrade accuracy due to the smaller signal to theinput of the current-sense amplifier. The charging cur-rent-error amplifier (GMI) is compensated at CCI (seethe Compensation section).

Setting the Input Current LimitThe total input current (from an AC adapter or other DCsource) is a function of the system supply current andthe battery-charging current. The input current regulatorlimits the input current by reducing the charging current when the input current exceeds the input current-l imit set point. System current normally fluctuates as portions of the system are powered up ordown. Without input current regulation, the source mustbe able to supply the maximum system current and themaximum charger input current simultaneously. Byusing the input current limiter, the current capability ofthe AC adapter can be lowered, reducing system cost.

The MAX1908/MAX8724 limit the battery charge currentwhen the input current-limit threshold is exceeded,ensuring the battery charger does not load down the

AC adapter voltage. An internal amplifier compares thevoltage between CSSP and CSSN to the voltage atCLS. VCLS can be set by a resistive divider betweenREF and GND. Connect CLS to REF for the full-scaleinput current limit.

The input current is the sum of the device current, thecharger input current, and the load current. The devicecurrent is minimal (3.8mA) in comparison to the chargeand load currents. Determine the actual input currentrequired as follows:

where η is the efficiency of the DC-DC converter.

VCLS determines the reference voltage of the GMSerror amplifier. Sense resistor RS1 and VCLS determinethe maximum allowable input current. Calculate theinput current limit as follows:

Once the input current limit is reached, the chargingcurrent is reduced until the input current is at thedesired threshold.

When choosing the current-sense resistor, note that thevoltage drop across this resistor causes further powerloss, reducing efficiency. Choose the smallest value forRS1 that achieves the accuracy requirement for theinput current-limit set point.

Conditioning ChargeThe MAX1908 includes a battery voltage comparatorthat allows a conditioning charge of overdischargedLi+ battery packs. If the battery-pack voltage is lessthan 3.1V × number of cells programmed by CELLS,the MAX1908 charges the battery with 300mA currentwhen using sense resistor RS2 = 0.015Ω. After the battery voltage exceeds the conditioning chargethreshold, the MAX1908 resumes full-charge mode,charging to the programmed voltage and current limits.The MAX8724 does not offer this feature.

AC Adapter DetectionConnect the AC adapter voltage through a resistivedivider to ACIN to detect when AC power is available,as shown in Figure 1. ACIN voltage rising trip point isVREF / 2 with 20mV hysteresis. ACOK is an open-drainoutput and is high impedance when ACIN is less thanVREF / 2. Since ACOK can withstand 30V (max), ACOKcan drive a P-channel MOSFET directly at the chargerinput, providing a lower dropout voltage than aSchottky diode (Figure 2).

IVV RSINPUTCLS

REF= × 0 075

1.

I II V

VINPUT LOADCHG BATT

IN= +

××

η

IV

RSCHG = 0 0452

.

IV

V RSCHGICTL

REFIN= × 0 075

2.


16 ______________________________________________________________________________________

Current MeasurementUse ICHG to monitor the battery charging current beingsensed across CSIP and CSIN. The ICHG voltage isproportional to the output current by the equation:

VICHG = ICHG x RS2 x GICHG x R9

where ICHG is the battery charging current, GICHG isthe transconductance of ICHG (3µA/mV typ), and R9 isthe resistor connected between ICHG and ground.Leave ICHG unconnected if not used.

Use IINP to monitor the system input current beingsensed across CSSP and CSSN. The voltage of IINP isproportional to the input current by the equation:

VIINP = IINPUT x RS2 x GIINP x R10

where IINPUT is the DC current being supplied by the ACadapter power, GIINP is the transconductance of IINP(3µA/mV typ), and R10 is the resistor connected betweenIINP and ground. ICHG and IINP have a 0 to 3.5V outputvoltage range. Leave IINP unconnected if not used.

LDO RegulatorLDO provides a 5.4V supply derived from DCIN andcan deliver up to 10mA of load current. The MOSFETdrivers are powered by DLOV and BST, which must beconnected to LDO as shown in Figure 1. LDO suppliesthe 4.096V reference (REF) and most of the control cir-cuitry. Bypass LDO with a 1µF capacitor to GND.

ShutdownThe MAX1908/MAX8724 feature a low-power shutdownmode. Driving SHDN low shuts down the MAX1908/MAX8724. In shutdown, the DC-DC converter is dis-abled and CCI, CCS, and CCV are pulled to ground.The IINP and ACOK outputs continue to function.

SHDN can be driven by a thermistor to allow automaticshutdown of the MAX1908/MAX8724 when the batterypack is hot. The shutdown falling threshold is 23.5%(typ) of VREFIN with 1% VREFIN hysteresis to providesmooth shutdown when driven by a thermistor.

DC-DC ConverterThe MAX1908/MAX8724 employ a buck regulator witha bootstrapped NMOS high-side switch and a low-sideNMOS synchronous rectifier.

CCV, CCI, CCS, and LVC Control BlocksThe MAX1908/MAX8724 control input current (CCScontrol loop), charge current (CCI control loop), orcharge voltage (CCV control loop), depending on theoperating condition.

The three control loops, CCV, CCI, and CCS are broughttogether internally at the LVC amplifier (lowest voltageclamp). The output of the LVC amplifier is the feedbackcontrol signal for the DC-DC controller. The output of theGM amplifier that is the lowest sets the output of the LVCamplifier and also clamps the other two control loops towithin 0.3V above the control point. Clamping the othertwo control loops close to the lowest control loop ensuresfast transition with minimal overshoot when switchingbetween different control loops.

DC-DC ControllerThe MAX1908/MAX8724 feature a variable off-time, cycle-by-cycle current-mode control scheme. Depending uponthe conditions, the MAX1908/MAX8724 work in continu-ous or discontinuous-conduction mode.

Continuous-Conduction ModeWith sufficient charger loading, the MAX1908/MAX8724operate in continuous-conduction mode (inductor currentnever reaches zero) switching at 400kHz if the BATT voltage is within the following range:

3.1V x (number of cells) < VBATT < (0.88 x VDCIN )

The operation of the DC-DC controller is controlled bythe following four comparators as shown in Figure 4:

IMIN—Compares the control point (LVC) against 0.15V(typ). If IMIN output is low, then a new cycle cannotbegin.

CCMP—Compares the control point (LVC) against thecharging current (CSI). The high-side MOSFET on-timeis terminated if the CCMP output is high.

IMAX—Compares the charging current (CSI) to 6A(RS2 = 0.015Ω). The high-side MOSFET on-time is ter-minated if the IMAX output is high and a new cyclecannot begin until IMAX goes low.

ZCMP—Compares the charging current (CSI) to 33mA(RS2 = 0.015Ω). If ZCMP output is high, then bothMOSFETs are turned off.

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18 ______________________________________________________________________________________

IMAX

RESET

1.8V

0.15V

0.1V

5ms

LVC

CONTROL

CELLS

SETVSETI

CCVCCICCS

GMS

GMI

GMV

CLS

DLO

DHI

CSIX20

tOFFGENERATOR

BST

S

R Q

CCMP

ZCMP

IMIN

CHG

R Q

S

CSSX20

CSSP AC ADAPTER

CSSN

BST

DHI

LX

RS1 LDO

D3

N1a

N1b

CBST

L1

RS2

DLO

CSIP

CSIN

COUT

BATT

BATTERY

MAX1908MAX8724

Q

CELL SELECT

LOGIC

Figure 4. DC-DC Functional Diagram

DC-DC Functional Diagram

In normal operation, the controller starts a new cycle byturning on the high-side N-channel MOSFET and turning off the low-side N-channel MOSFET. When thecharge current is greater than the control point (LVC),CCMP goes high and the off-time is started. The off-time turns off the high-side N-channel MOSFET andturns on the low-side N-channel MOSFET. The opera-tional frequency is governed by the off-time and isdependent upon VDCIN and VBATT. The off-time is setby the following equations:

where:

These equations result in fixed-frequency operationover the most common operating conditions.

At the end of the fixed off-time, another cycle begins ifthe control point (LVC) is greater than 0.15V, IMIN =high, and the peak charge current is less than 6A (RS2= 0.015Ω), IMAX = high. If the charge current exceedsIMAX, the on-time is terminated by the IMAX comparator.IMAX governs the maximum cycle-by-cycle current limitand is internally set to 6A (RS2 = 0.015Ω). IMAX pro-tects against sudden overcurrent faults.

If during the off-time the inductor current goes to zero,ZCMP = high, both the high- and low-side MOSFETsare turned off until another cycle is ready to begin.

There is a minimum 0.3µs off-time when the (VDCIN -VBATT) differential becomes too small. If VBATT ≥ 0.88 ×VDCIN, then the threshold for minimum off-time isreached and the tOFF is fixed at 0.3µs. A maximum on-time of 5ms allows the controller to achieve >99% dutycycle in continuous-conduction mode. The switchingfrequency in this mode varies according to the equation:

Discontinuous ConductionThe MAX1908/MAX8724 enter discontinuous-conductionmode when the output of the LVC control point falls below0.15V. For RS2 = 0.015Ω, this corresponds to 0.5A:

In discontinuous mode, a new cycle is not started untilthe LVC voltage rises above 0.15V. Discontinuous-mode operation can occur during conditioning chargeof overdischarged battery packs, when the charge cur-rent has been reduced sufficiently by the CCS controlloop, or when the battery pack is near full charge (con-stant voltage charging mode).

MOSFET DriversThe low-side driver output DLO switches betweenPGND and DLOV. DLOV is usually connected througha filter to LDO. The high-side driver output DHI is boot-strapped off LX and switches between VLX and VBST.When the low-side driver turns on, BST rises to onediode voltage below DLOV.

Filter DLOV with a lowpass filter whose cutoff frequencyis approximately 5kHz (Figure 1):

Dropout OperationThe MAX1908/MAX8724 have 99% duty-cycle capabilitywith a 5ms (max) on-time and 0.3µs (min) off-time. Thisallows the charger to achieve dropout performance limit-ed only by resistive losses in the DC-DC converter com-ponents (D1, N1, RS1, and RS2, Figure 1). Replacingdiode D1 with a P-channel MOSFET driven by ACOKimproves dropout performance (Figure 2). The dropoutvoltage is set by the difference between DCIN and CSIN.When the dropout voltage falls below 100mV, the chargeris disabled; 200mV hysteresis ensures that the chargerdoes not turn back on until the dropout voltage rises to300mV.

CompensationEach of the three regulation loops—input current limit,charging current limit, and charging voltage limit—arecompensated separately using CCS, CCI, and CCV,respectively.

fRC F

kHzC = =× ×

=12

12 33 1

4 8π π µΩ

.

IV

RSA for RSMIN =

×= =0 15

20 20 5 2 0 015

.. . Ω

fL I

V VsRIPPLE

CSSN BATT

=×

−( ) +

1

0 3. µ

ft tON OFF

=+1

IV t

LRIPPLEBATT OFF=

×

tL I

V VONRIPPLE

CSSN BATT=

×−

t sV V

VOFFDCIN BATT

DCIN= ×

−2 5. µ

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CCV Loop DefinitionsCompensation of the CCV loop depends on the para-meters and components shown in Figure 5. CCV andRCV are the CCV loop compensation capacitor andseries resistor. RESR is the equivalent series resistance(ESR) of the charger output capacitor (COUT). RL is theequivalent charger output load, where RL = VBATT /ICHG. The equivalent output impedance of the GMVamplifier, ROGMV ≥ 10MΩ. The voltage amplifiertransconductance, GMV = 0.125µA/mV. The DC-DCconverter transconductance, GMOUT = 3.33A/V:

where ACSI = 20, and RS2 is the charging current-sense resistor in the Typical Application Circuits.

The compensation pole is given by:

The compensation zero is given by:

The output pole is given by:

where RL varies with load according to RL = VBATT / ICHG.

Output zero due to output capacitor ESR:

The loop transfer function is given by:

Assuming the compensation pole is a very lowfrequency, and the output zero is a much higher fre-quency, the crossover frequency is given by:

To calculate RCV and CCV values of the circuit of Figure 2: Cells = 4COUT = 22µFVBATT = 16.8VICHG = 2.5AGMV = 0.125µA/mVGMOUT = 3.33A/VROGMV = 10MΩf = 400kHz

Choose crossover frequency to be 1/5th theMAX1908’s 400kHz switching frequency:

Solving yields RCV = 26kΩ.

Conservatively set RCV = 1kΩ, which sets the crossoverfrequency at:

fCO_CV = 3kHz

Choose the output-capacitor ESR such that the output-capacitor zero is 10 times the crossover frequency:

fR C

MHzZ ESRESR OUT

_ .=×

=12

2 412π

Rf CESRCO CV OUT

=× × ×

=12 10

0 24π _

. Ω

fGMV R GM

CkHzCO CV

CV OUT

OUT_ =

× ×=

280

π

fGMV R GM

CCO CVCV OUT

OUT_ =

× ×2π

LTF GM R GMV R

sC R sC R

sC R sC R

OUT L OGMV

OUT ESR CV CV

CV OGMV OUT L

= × × × ×

+ ×( ) + ×( )+ ×( ) + ×( )

1 1

1 1

fR CZ ESR

ESR OUT_ =

×1

2π

fR CP OUT

L OUT_ =

×1

2π

fR CZ CV

CV CV_ =

×1

2π

fR CP CV

OGMV CV_ =

×1

2π

GMA RSOUT

CSI=

×1

2


20 ______________________________________________________________________________________

GMOUT

BATT

CCVGMV

REFRCV

CCV

ROGMV

RESR RL

COUT

Figure 5. CCV Loop Diagram

The 22µF ceramic capacitor has a typical ESR of0.003Ω, which sets the output zero at 2.412MHz.

The output pole is set at:

where:

Set the compensation zero (fZ_CV) such that it is equiv-alent to the output pole (fP_OUT = 1.08kHz), effectivelyproducing a pole-zero cancellation and maintaining asingle-pole system response:

Choose CCV = 100nF, which sets the compensationzero (fZ_CV) at 1.6kHz. This sets the compensation pole:

CCI Loop DefinitionsCompensation of the CCI loop depends on the parame-ters and components shown in Figure 7. CCI is the CCIloop compensation capacitor. ACSI is the internal gainof the current-sense amplifier. RS2 is the charge cur-rent-sense resistor, RS2 = 15mΩ. ROGMI is the equiva-lent output impedance of the GMI amplifier ≥ 10MΩ.GMI is the charge-current amplifier transconductance= 1µA/mV. GMOUT is the DC-DC converter transcon-ductance = 3.3A/V. The CCI loop is a single-pole sys-tem with a dominant pole compensation set by fP_CI:


Since:

The loop transfer function simplifies to:

LTF GMIR

sR COGMI

OGMI CI= ×

+ ×1

GMA RSOUT

CSI=

×1

2

LTF GM A RS GMIR

sR COUT CSIOGMI

OGMI CI= × × ×

+ ×2

1

fR CP CI

OGMI CI_ =

×1

2π

fR C

HzP CVOGMV CV

_ .=×

=12

0 16π

CR kHz

nFCVCV

=×

=12 1 08

147π .

fR CZ CV

CV CV_ =

×1

2π

RVI

Battery ESRLBATT

CHG= =

∆∆

fR C

kHzP OUTL OUT

_ .=×

=12

1 08π

MA

X1

90

8/M

AX

87

24


______________________________________________________________________________________ 21

CCV LOOP GAINvs. FREQUENCY

FREQUENCY (Hz)

GAIN

(dB)

100k10k1k10010

-40

-20

0

20

40

60

80

-601 1M

CCV LOOP PHASEvs. FREQUENCY

FREQUENCY (Hz)

PHAS

E (D

EGRE

ES)

100k10k1k10010

-120

-105

-90

-75

-60

-45

-1351 1M

Figure 6. CCV Loop Gain/Phase vs. Frequency

MA

X1

90

8/M

AX

87

24

The crossover frequency is given by:

The CCI loop dominant compensation pole:

where the GMI amplifier output impedance, ROGMI =10MΩ.

To calculate the CCI loop compensation pole, CCI:

GMI = 1µA/mV

GMOUT = 3.33A/V

ROGMI = 10MΩf = 400kHz

Choose crossover frequency fCO_CI to be 1/5th theMAX1908/MAX8724 switching frequency:

Solving for CCI, CCI = 2nF.

To be conservative, set CCI = 10nF, which sets thecrossover frequency at:

The compensation pole, fP_CI is set at:

CCS Loop DefinitionsCompensation of the CCS loop depends on the parame-ters and components shown in Figure 9. CCS is the CCSloop compensation capacitor. ACSS is the internal gain ofthe current-sense amplifier. RS1 is the input current-sense resistor, RS1 = 10mΩ. ROGMS is the equivalentoutput impedance of the GMS amplifier ≥ 10MΩ. GMS is

fGMI

R CHzP CI

OGMI CI_ .=

×=

20 0016

π

fGMI

nFkHzCO CI_ = =

2 1016

π

fGMI

CkHzCO CI

CI_ = =

280

π

fR CP CI

OGMI CI_ =

×1

2π

fGMI

CCO CICI

_ =2π


22 ______________________________________________________________________________________

GMOUT

CCIGMI

ICTLCCI ROGMI

CSIP CSIN

CSI

RS2

Figure 7. CCI Loop Diagram

CCI LOOP GAINvs. FREQUENCY

FREQUENCY (Hz)

GAIN

(dB)

100k10k1 10 100 1k

-40

-20

0

20

40

60

80

100

-600.1 1M

CCI LOOP PHASEvs. FREQUENCY

FREQUENCY (Hz)

PHAS

E (D

EGRE

ES)

100k10k1k100101

-90

-75

-60

-45

-30

-15

0

-1050.1 1M

Figure 8. CCI Loop Gain/Phase vs. Frequency

the charge-current amplifier transconductance = 1µA/mV.GMIN is the DC-DC converter transconductance =3.3A/V. The CCS loop is a single-pole system with a dom-inant pole compensation set by fP_CS:


Since:

Then, the loop transfer function simplifies to:

The crossover frequency is given by:

The CCS loop dominant compensation pole:

where the GMS amplifier output impedance, ROGMS =10MΩ.

To calculate the CCI loop compensation pole, CCS:

GMS = 1µA/mV

GMIN = 3.33A/V

ROGMS = 10MΩf = 400kHz

fR CP CS

OGMS CS_ =

×1

2π

fGMS

CCO CSCS

_ =2π

LTF GMSR

sR COGMS

OGMS CS= ×

+ ×1

GMA RSIN

CSS=

×1

1

LTF GM A RS GMSR

sR CIN CSSOGMS

OGMS CS= × × × ×

+ ×1

1

fR CP CS

OGMS CS_ =

×1

2π

MA

X1

90

8/M

AX

87

24


______________________________________________________________________________________ 23

GMIN

CCSGMS

CLSCCS ROGMS

CSSP CSSN

CSS

RS1

Figure 9. CCS Loop Diagram

CCS LOOP GAINvs. FREQUENCY

FREQUENCY (Hz)

GAIN

(dB)

100k10k1 10 100 1k

-40

-20

0

20

40

60

80

100

-600.1 1M

CCS LOOP PHASEvs. FREQUENCY

FREQUENCY (Hz)

PHAS

E (D

EGRE

ES)

100k10k1k100101

-90

-75

-60

-45

-30

-15

0

-1050.1 1M

Figure 10. CCS Loop Gain/Phase vs. Frequency

MA

X1

90

8/M

AX

87

24 Choose crossover frequency fCO_CS to be 1/5th the

MAX1908/MAX8724 switching frequency:

Solving for CCS, CCS = 2nF.

To be conservative, set CCS = 10nF, which sets thecrossover frequency at:

The compensation pole, fP_CS is set at:

Component SelectionTable 2 lists the recommended components and refersto the circuit of Figure 2. The following sectionsdescribe how to select these components.

Inductor SelectionInductor L1 provides power to the battery while it isbeing charged. It must have a saturation current of atleast the charge current (ICHG), plus 1/2 the current rip-ple IRIPPLE:

ISAT = ICHG + (1/2) IRIPPLE

Ripple current varies according to the equation:

IRIPPLE = (VBATT) × tOFF / L

where:

tOFF = 2.5µs × (VDCIN – VBATT) / VDCIN

VBATT < 0.88 × VDCIN

or:

tOFF = 0.3µs

VBATT > 0.88 × VDCIN

Figure 11 illustrates the variation of ripple current vs.battery voltage when charging at 3A with a fixed inputvoltage of 19V.

Higher inductor values decrease the ripple current.Smaller inductor values require higher saturation cur-rent capabilities and degrade efficiency. Designs forripple current, IRIPPLE = 0.3 × ICHG usually result in agood balance between inductor size and efficiency.

Input CapacitorInput capacitor C1 must be able to handle the inputripple current. At high charging currents, the DC-DCconverter operates in continuous conduction. In thiscase, the ripple current of the input capacitor can beapproximated by the following equation:

where:

IC1 = input capacitor ripple current.

D = DC-DC converter duty ratio.

ICHG = battery-charging current.

Input capacitor C1 must be sized to handle the maxi-mum ripple current that occurs during continuous con-duction. The maximum input ripple current occurs at50% duty cycle; thus, the worst-case input ripple cur-rent is 0.5 × ICHG. If the input-to-output voltage ratio issuch that the DC-DC converter does not operate at a50% duty cycle, then the worst-case capacitor currentoccurs where the duty cycle is nearest 50%.

The input capacitor ESR times the input ripple currentsets the ripple voltage at the input, and should notexceed 0.5V ripple. Choose the ESR of C1 according to:

The input capacitor size should allow minimal outputvoltage sag at the highest switching frequency:

IC

dVdt

C12

1=

ESRV

ICC

11

0 5< .

I I D DC CHG12= −

fR C

HzP CSOGMS CS

_ .=×

=12

0 0016π

fGMS

nFkHzCO CS_ = =

2 1016

π

fGMS

CkHzCO CS

CS_ = =

280

π


24 ______________________________________________________________________________________

RIPPLE CURRENT vs. VBATT

VBATT (V)

RIPP

LE C

URRE

NT (A

)

14131211109

0.5

1.0

1.5

08 15 16 17 18

VDCIN = 19VVCTL = ICTL = LDO

4 CELLS

3 CELLS

Figure 11. MAX1908 Ripple Current vs. Battery Voltage

MA

X1

90

8/M

AX

87

24


______________________________________________________________________________________ 25

where dV is the maximum voltage sag of 0.5V whiledelivering energy to the inductor during the high-sideMOSFET on-time, and dt is the period at highest oper-ating frequency (400kHz):

Both tantalum and ceramic capacitors are suitable inmost applications. For equivalent size and voltage rating, tantalum capacitors have higher capacitance,but also higher ESR than ceramic capacitors. Thismakes it more critical to consider ripple current andpower-dissipation ratings when using tantalum capaci-tors. A single ceramic capacitor often can replace twotantalum capacitors in parallel.

Output CapacitorThe output capacitor absorbs the inductor ripple cur-rent. The output capacitor impedance must be signifi-cantly less than that of the battery to ensure that itabsorbs the ripple current. Both the capacitance andESR rating of the capacitor are important for its effec-tiveness as a filter and to ensure stability of the DC-DCconverter (see the Compensation section). Either tanta-lum or ceramic capacitors can be used for the outputfilter capacitor.

MOSFETs and DiodesSchottky diode D1 provides power to the load when theAC adapter is inserted. This diode must be able todeliver the maximum current as set by RS1. Forreduced power dissipation and improved dropout per-formance, replace D1 with a P-channel MOSFET (P1)as shown in Figure 2. Take caution not to exceed themaximum VGS of P1. Choose resistors R11 and R12 tolimit the VGS.

The N-channel MOSFETs (N1a, N1b) are the switchingdevices for the buck controller. High-side switch N1ashould have a current rating of at least the maximumcharge current plus one-half the ripple current andhave an on-resistance (RDS(ON)) that meets the powerdissipation requirements of the MOSFET. The driver forN1a is powered by BST. The gate-drive requirement forN1a should be less than 10mA. Select a MOSFET with alow total gate charge (QGATE) and determine therequired drive current by IGATE = QGATE × f (where f isthe DC-DC converter’s maximum switching frequency).

The low-side switch (N1b) has the same current ratingand power dissipation requirements as N1a, andshould have a total gate charge less than 10nC. N2 isused to provide the starting charge to the BST capacitor(C15). During the dead time (50ns, typ) between N1aand N1b, the current is carried by the body diode of

the MOSFET. Choose N1b with either an internalSchottky diode or body diode capable of carrying themaximum charging current during the dead time. TheSchottky diode D3 provides the supply current to thehigh-side MOSFET driver.

Layout and BypassingBypass DCIN with a 1µF capacitor to power ground(Figure 1). D2 protects the MAX1908/MAX8724 whenthe DC power source input is reversed. A signal diodefor D2 is adequate because DCIN only powers theMAX1908 internal circuitry. Bypass LDO, REF, CCV,CCI, CCS, ICHG, and IINP to analog ground. BypassDLOV to power ground.

Good PC board layout is required to achieve specifiednoise, efficiency, and stable performance. The PCboard layout artist must be given explicit instructions—preferably, a pencil sketch showing the placement ofthe power-switching components and high-current rout-ing. Refer to the PC board layout in the MAX1908 eval-uation kit for examples. Separate analog and powergrounds are essential for optimum performance.

Use the following step-by-step guide:

1) Place the high-power connections first, with theirgrounds adjacent:

a) Minimize the current-sense resistor trace lengths,and ensure accurate current sensing with Kelvinconnections.

b) Minimize ground trace lengths in the high-currentpaths.

c) Minimize other trace lengths in the high-currentpaths.

d) Use > 5mm wide traces.

e) Connect C1 to high-side MOSFET (10mm maxlength).

f) LX node (MOSFETs, inductor (15mm maxlength)).

Ideally, surface-mount power components are flushagainst one another with their ground terminalsalmost touching. These high-current grounds arethen connected to each other with a wide, filled zoneof top-layer copper, so they do not go through vias.

The resulting top-layer power ground plane is connected to the normal ground plane at theMAX1908/MAX8724s’ backside exposed pad.Other high-current paths should also be minimized,but focusing primarily on short ground and current-sense connections eliminates most PC board lay-out problems.

CI s

VC12

2 50 5

1> × ..

µ

MA

X1

90

8/M

AX

87

24


26 ______________________________________________________________________________________

Table 2. Component List for Circuit of Figure 2

DESIGNATION QTY DESCRIPTION

C1 210µF, 50V 2220-size ceramiccapacitorsTDK C5750X7R1H106M

C4 122µF, 25V 2220-size ceramiccapacitorTDK C5750X7R1E226M

C5 1

1µF, 25V X7R ceramic capacitor(1206)Murata GRM31MR71E105KTaiyo Yuden TMK316BJ105KLTDK C3216X7R1E105K

C9, C10 2

0.01µF, 16V cer am i c cap aci tor s ( 0402) Murata GRP155R71E103KTaiyo Yuden EMK105BJ103KVTDK C1005X7R1E103K

C11, C14,C15, C20

4

0.1µF, 25V X7R ceramic capacitors(0603)Murata GRM188R71E104KTDK C1608X7R1E104K

C12, C13, C16 3

1µF, 6.3V X5R ceramic capacitors(0603)Murata GRM188R60J105KTaiyo Yuden JMK107BJ105KATDK C1608X5R1A105K

D1 (optional) 110A Schottky diode (D-PAK)Diodes, Inc. MBRD1035CTLON Semiconductor MBRD1035CTL

D2 1Schottky diodeCentral SemiconductorCMPSH1–4

DESIGNATION QTY DESCRIPTION

D3 1Schottky diodeCentral Semiconductor CMPSH1-4

L1 110µH, 4.4A inductorSumida CDRH104R-100NCTOKO 919AS-100M

N1 1Dual, N-channel, 8-pin SO MOSFETFairchild FDS6990A or FDS6990S

P1 1Single, P-channel, 8-pin SO MOSFETFairchild FDS6675

R5 1 1kΩ ±5% resistor (0603)

R6 1 59kΩ ±1% resistor (0603)

R7 1 19.6kΩ ±1% resistor (0603)

R11 1 12kΩ ±5% resistor (0603)

R12 1 15kΩ ±5% resistor (0603)

R13 1 33Ω ±5% resistor (0603)

R14 1 10.5kΩ ±1% resistor (0603)

R15, R16 2 8.25kΩ ±1% resistors (0603)

R17 1 19.1kΩ ±1% resistor (0603)

R18 1 22kΩ ±1% resistor (0603)

R19, R20 2 10kΩ ±1% resistors (0603)

RS1 10.01Ω ±1%, 0.5W 2010 sense resistorVishay Dale WSL2010 0.010 1.0%IRC LRC-LR2010-01-R010-F

RS2 1

0.015Ω ±1%, 0.5W 2010 senseresistorVishay Dale WSL2010 0.015 1.0%IRC LRC-LR2010-01-R015-F

U1 1 MAX1908ETI or MAX8724ETI

Chip InformationTRANSISTOR COUNT: 3772

PROCESS: BiCMOS

2) Place the IC and signal components. Keep themain switching node (LX node) away from sensitiveanalog components (current-sense traces and REFcapacitor). Important: The IC must be no furtherthan 10mm from the current-sense resistors.

Keep the gate-drive traces (DHI, DLO, and BST)shorter than 20mm, and route them away from the

current-sense lines and REF. Place ceramicbypass capacitors close to the IC. The bulk capac-itors can be placed further away.

3) Use a single-point star ground placed directlybelow the part at the backside exposed pad of theMAX1908/MAX8724. Connect the power groundand normal ground to this node.

MA

X1

90

8/M

AX

87

24


Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27

© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to www.maxim-ic.com/packages.)

QFN

TH

IN.E

PS

D2

(ND-1) X e

e

D

C

PIN # 1 I.D.

(NE-1) X e

E/2

E

0.08 C

0.10 C

A

A1 A3

DETAIL A

0.15 C B

0.15 C A

E2/2

E2

0.10 M C A B

PIN # 1 I.D.

b

0.35x45∞

L

D/2D2/2

LC

LC

e e

LCCL

k

k

LL

E1

221-0140

PACKAGE OUTLINE16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm

DETAIL B

LL1

e

COMMON DIMENSIONS

3.353.15T2855-1 3.25 3.353.15 3.25

MAX.

3.20

EXPOSED PAD VARIATIONS

3.00T2055-2 3.10

D2NOM.MIN.

3.203.00 3.10

MIN.

E2NOM. MAX.

NE

ND

PKG.CODES

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1, T2855-3 AND T2855-6.

NOTES:

SYMBOLPKG.

N

L1

e

E

D

b

A3

A

A1

k

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

JEDEC

T1655-1 3.203.00 3.10 3.00 3.10 3.200.70 0.800.75

4.904.90

0.25

0.25

0

- -

4

WHHB

4

16

0.350.30

5.105.105.00

0.80 BSC.

5.00

0.05

0.20 REF.

0.02

MIN. MAX.NOM.

16L 5x5

3.10T3255-2 3.00 3.20 3.00 3.10 3.20

2.70T2855-2 2.60 2.602.80 2.70 2.80

E2

221-0140

PACKAGE OUTLINE16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm

L 0.30 0.500.40

- -- - --

WHHC

20

55

5.005.00

0.30

0.55

0.65 BSC.

0.45

0.25

4.904.90

0.25

0.65

--

5.105.10

0.35

20L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

- --

WHHD-1

28

77

5.005.00

0.25

0.55

0.50 BSC.

0.45

0.25

4.904.90

0.20

0.65

--

5.105.10

0.30

28L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

- --

WHHD-2

32

88

5.005.00

0.40

0.50 BSC.

0.30

0.25

4.904.90

0.50

--

5.105.10

32L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

-

40

1010

5.005.00

0.20

0.50

0.40 BSC.

0.40

0.25

4.904.90

0.15

0.60

5.105.10

0.25

40L 5x5

0.20 REF.

0.75

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

0.20 0.25 0.30

-

0.35 0.45

0.30 0.40 0.50

DOWN BONDS ALLOWED

NO

YES3.103.00 3.203.103.00 3.20T2055-3

3.103.00 3.203.103.00 3.20T2055-4

T2855-3 3.15 3.25 3.35 3.15 3.25 3.35

T2855-6 3.15 3.25 3.35 3.15 3.25 3.35

T2855-4 2.60 2.70 2.80 2.60 2.70 2.80

T2855-5 2.60 2.70 2.80 2.60 2.70 2.80

T2855-7 2.60 2.70 2.80 2.60 2.70 2.80

3.203.00 3.10T3255-3 3.203.00 3.103.203.00 3.10T3255-4 3.203.00 3.10

3.403.20 3.30T4055-1 3.20 3.30 3.40

NO

NONO

NO

NO

NO

NO

NO

YESYES

YES

YES

YES

3.203.00T1655-2 3.10 3.00 3.10 3.20 YES

MAX 8724E

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