Manoj Chacko Director Product Management Signoff Summit November 21, 2003 Physical Signoff with...
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Manoj Chacko Director Product Management Signoff Summit November 21, 2003 Physical Signoff with Cadence PVS
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Transcript of Manoj Chacko Director Product Management Signoff Summit November 21, 2003 Physical Signoff with...
Manoj ChackoDirector Product Management Signoff SummitNovember 21, 2003
Physical Signoff with Cadence PVS
2 © 2013 Cadence Design Systems, Inc. All rights reserved.
Cadence Physical Verification System
Increasing Foundry Coverage from 180nm down to 16/14N FF
Comprehensive Integration with Virtuoso, Encounter, & QRC
Advanced Node, DFM, SiP/3D-IC Integrations
Advanced Node
Timing aware Fill
Re-simulation with QRC
3D Devices/FinFET
Stacked Die and 3DIC
Layout Dependent Eff ects
100+ companies switched to PVS in past 24 monthsDrivers: Alternative to Calibre, in-design signoff, adv. node, mixed signal
In-Design Signoff
Pattern Matching
Mixed Signal
PHYSICAL VERIFICATION
SYSTEM
In-designUnique debug
Design intent
+-
+ -?
In-Design, and Full Chip Signoff
Reliability Analysis Constraint Validation
Incremental ECO Fill
3 © 2013 Cadence Design Systems, Inc. All rights reserved.
Wide Foundry Coverage
PVS Rule Deck Availability
TSMC 180 , 65, 55, 45, 40, 28nm, 20nm, 16nm decks available
GF 180nm, 130nm, 65nm and 40nm: available; 28nm, 20nm, and 14nm: ongoing.
ST 20nm, B9mw, H9A, B7RF, 28FDSOI, 14FDSOI
IBM 14nm: ongoing
SAMSUNG 20nm, 28nm and14nm: ongoing
SMIC 40nm, 28nm, 20nm, 14nm: ongoing
UMC 130nm, 110nm, 65nm and 45nm
XFAB XH018, XH035, XA035: available online; other process nodes: per request
AMS C35: available online; 2H2013: H35
Huali 55nm: available online
4 © 2013 Cadence Design Systems, Inc. All rights reserved.
Adopting to PVS as Golden Signoff 65nm - 28nm
5 © 2013 Cadence Design Systems, Inc. All rights reserved.
PRESS RELEASESource: http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=053013_pmc
PMC Adopts Cadence Physical Verification System as Signoff Technology for Large Complex SoCSAN JOSE, Calif., 30 May 2013
HIGHLIGHTS
• PMC is producing working silicon on 65- and 40-nanometer designs, and is currently deploying the product for its 28-nanometer designs.
• Technology chosen for turnaround time and ready foundry support
• Physical Verification System signoff decks certified by major foundries
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design
innovation, announced today that PMC® has adopted the Cadence® Physical Verification
System as signoff technology for its global design centers. PMC has used the Physical
Verification System for several successful tapeouts, including PMC’s DIGI 120, described as
the industry’s only single-chip processor supporting 10G, 40G and 100G speeds for OTN
transport, aggregation and switching. The device, with 200+ million gates and 180+ Mbits of
RAM, is the largest production SoC that PMC has delivered.
Presented at CDNLive2013, (www.cadence.com)
6 © 2013 Cadence Design Systems, Inc. All rights reserved.
IBM
SAMSUNG
QUALCOMM
KLA TENCOR
FUJITSU
NXP
HITACHI
JAPAN DISPLAY
STMICROELECTRONICS
RENESAS ELECTRONICS
HITTITE MICROWAVE
SHARP
RESEARCH IN MOTION
SEMTECH
TELEDYNE TECHNOLOGIES
PMC SIERRA
HONEYWELL INTERNATIONAL
MITSUBISHI
HEWLETT PACKARD
TOSHIBA
X FAB
SWINDON SILICON SYSTEMS
MURATA
TOWER SEMICONDUCTOR
SIGMA DESIGNS
CANON
ADVANTEST
RF MICRO DEVICES
MICROSEMI
MICRON TECHNOLOGY
ENTROPIC COMMUNICATIONS
INTERSIL
PEREGRINE
SEMICONDUCTOR
LUXTERA
CONEXANT SYSTEMS
OMNIVISION TECHNOLOGIES
GALAXYCORE
INTEGRATED DEVICE
TECHNOLOGY
E2V
ALTERA
NVIDIA
CLARIPHY COMMUNICATIONS
COHERENT
SPANSION
ST JUDE MEDICAL
WOLFSON
MICROELECTRONICS
TEXAS INSTRUMENTS
INFINEON
CSMC TECHNOLOGIES
FORZA SILICON
SYMMID
BIOTRONIK
PANASONIC
DE SHAW GROUP
INSIDE TECHNOLOGIES
MIET
VOLTERRA
SWATCH
TERADYNE
SPREE SILICON SYSTEM
TOUMAZ TECHNOLOGY
ALTAIR
HUAWEI TECHNOLOGIES
CORTINA SYSTEMS
INVISAGE
RF INTEGRATION
ZMD
CHRONTEL
HILIGHT SEMICONDUCTOR
AMBIQ MICRO
INPHI
CIMPACA
RAYSAT
CEITEC
GIANTEC SEMICONDUCTOR
SPREADTRUM
COMMUNICATIONS
VANGUARD INTL
SEMICONDUCTOR
LIME MICROSYSTEMS
AVAGO TECHNOLOGIES
RUSSIAN SPACE SYSTEMS
MIKRON
ZAO
GENNUM
ENPHASE ENERGY
PARROT
AMAZING MICROELECTRONIC
SMIC
SHANGHAI HUALI
MICROELECTRONICS S
SILTERRA
100+CUSTOMERS GLOBALLY
IPVS, PVSCV, PVS PERC, PVS SIGNOFF
13 TOPSEMICONDUCTOR
COMPANIES
OFTHE
Transitioning to In-Design and Signoff PVS
© 2013 Cadence Design Systems, Inc. All rights reserved.��
7 © 2013 Cadence Design Systems, Inc. All rights reserved.
Faster Path to Sign-Off with In-Design PVS
80% time spent debugging
20% onruntime
Virtuoso Custom
IC Platform
PVS Signoff
Faster Turnaround
Time
EfficientDebugging
Tight Integration
EncounterDigital
Platform
In-Design PVS
HigherProductivity
In-Design PVS
Verification Time to Tapeout
Source: Cadence
8 © 2013 Cadence Design Systems, Inc. All rights reserved.
Improved Productivity with PVS Signoff
BEST - Virtuoso IPVS Dynamic In-Design Verification, checks as you edit
Design Platform
Layout Seat
StandalonePVS signoff
Std Interfaces
Enhances Productivity of Layout Teams
PVSVerify
Design
In Memory
Dynamic
IPVS
GDSII
BETTER - PVS interactive (batch) signoff executing off Virtuoso® in-memory dataINEFFICIENT - Traditional (batch) signoff forces long loops
Live Demo in Lobby
9 © 2013 Cadence Design Systems, Inc. All rights reserved.
Coming Up - Customer experience of adopting PVS
