Making Informed Memory Choices FTF-IND-F0378 · Power Density ... • Cheapest low density Parallel...

©2014 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.

1 ©2014 Micron Technology, Inc. |

Freescale Technology Forum Jim Cooke [email protected] Mike Kim [email protected]

April 10, 2014

Making Informed Memory Choices FTF-IND-F0378

http://topyx.numonyx.com/collab/CTO-CorporateMarketing/brandassets/Product Images/Wafer and Die Shots/PCM_90nm_Alverstone_Wafer_1a.jpg

mailto:[email protected]

mailto:[email protected]


Memory Agenda

▶ Non-Volatile Memory Choices

▶ DRAM Choices

▶ Trade-offs to consider for System Design Performance – Boot Time

Power

Density

Schedule / Time to Market / Sweet spot

Product life targets

▶ - Product Longevity Program

▶ Summary


D

S

G

D

S

G

D

S

G

D

S

G

NAND Memory cells are grouped in stacks

called “strings”

Physical “contacts” to the cells are reduced resulting in better cell efficiency

NVM architectures

D

S

G

D

S

G

Direct to read circuitry

"bitline"

NOR Each memory cell can be

accessed independent of the others

Physical "contact" to each memory location

NOR Advantages ▶ Fewer litho transitions

▶ Broad portfolio (Mb-Gb)

▶ Good read performance

▶ eXecute In Place capable

▶ True random access

▶ Easier to design

▶ Lowest cost under128Mb

▶ Assumed higher quality

Direct to read circuitry

NAND Advantages ▶ Fewer litho transitions

▶ Broad portfolio (Gb – 1Tb)

▶ Good sequential performance

▶ Lowest cost at high densities

▶ Challenges to use RAW MAMD

▶ Simple when paired with a controller, like eMMC


Single Level Cell vs. Multi-Level Cell ▶ SLC

1 physical bit = 1 data bit

Cell either programmed or erased

Higher performance

SLC NAND more reliable than MLC NAND

▶ MLC

1 physical bit = 2 data bits

3 bit per cell technology for some NAND

Cells partially programmed

Lower performance

Higher density and lower cost per MB


NOR product attributes

• Simple command sets • Cost effective at low densities • Stable architectures • Value added features (XiP, security,

quality, small data, etc)

Serial • Low pin counts • Easy PCB routing • Smallest footprint • Synchronous operations • Cheapest low density

Parallel • Basic add/data interface • Asynchronous random access • Synchronous burst operations • Higher throughput • Best XiP architecture


NAND product attributes

• Low pin counts • Lowest cost/bit at high densities • Frequent conversions/migrations

required at higher densities • Fast programming

Discrete • Some processors support boot • Some standards (ONFI) • Common packages • Needs SW for file / error

management • Wide density range (128Mb-1Tb)

Managed • Standards (eMMC, USB, uSD…) • Error management onboard • OS File system (looks like drive) • Some processors support boot • Higher densities (4-64GB) • Easier conversions/migrations


NAND technology challenges

How to manage the ECC requirements? • NAND controllers with high ECC capability

• ECC NAND managed solutions

on-die ECC

• Fully managed solutions

eMMC, eUSB, others

How to manage lower Endurance?

• Understand the application and usage model

How does the file system work?

How often are you programming?

How big is the data file/s?

What is the PLC of your system?

Intersecting your project and the memory technology is key to success!

Determines PE Cycles and Density Required


eMMC interface for application that want to offload by any

NAND data management with a standard interface.

Serial NAND for application requiring high density with Serial protocol.

ECC NAND for application that do not want to change the

ECC with the NAND litho shrink.

NAND system solutions for Industry

Raw NAND for application “expert” with NAND data

management and ready to support ECC needs. Raw NAND

Host Controller I

NAND Interface LLD ECC FTL

NAND BUS

ECC NAND Host Controller II

NAND Interface LLD FTL

NAND BUS ECC

eMMC NAND

ECC

FTL

Host Controller IV

eMMC Interface LLD

MMC BUS

SPI

ECC

Host Controller III

SPI Interface LLD

SPI BUS FTL

eUSB interface for application that want to offload by any

NAND data management with a standard interface.

eUSB NAND

ECC

FTL

Host Controller V

eUSB Interface LLD

USB BUS

LLD = Low Level Driver ECC = Error Correction Code FTL = NAND Scheduling Logical Mapping, Bad Block Management, Wear Leveling


Raw NAND ECC NAND (On-Die ECC)

Fully Managed (eMMC, eUSB)

Complexity of Customer Development (NAND Management by Host)

High Med Low

New Product Qualification (Complexity & Effort)

High Med Low

Relative Cost Low Med Med +

Level of Management by NAND Solution

Level of Management by NAND solutions

Trade offs between Complexity, Qualification Effort & Cost


Optimizing Your Memory Sub-System


▶ DRAM Choices


Power

Density




▶ Summary

©2014 Micron Technology, Inc. | 11

DRAM product attributes

• Many different types • Fast read performance • Fast writes • Leading edge requires many conversions

Discrete • Common standards • Common packages • Many levels in a single system

Module • Higher density reach • Easier conversions/migrations • Standards and custom options • ECC management enabled


DRAM Selection Criteria • Which DRAM technology(ies) are supported or planned by the processor?

• Proto/Production timeframe & expected life support needs?

• How many gigabytes are needed by the app?

• What is the memory bus width?

• Is ECC required for the DRAM?

• How much bandwidth (MB/sec) is needed by the app?

• Are there any preferred packages (discrete or module)?

• Does the customer require upgrade/cost reduction path (higher density/litho transition)?


PC Speed Trend

2009 2010 2011 2012 2013 2014

High End -1333 1.5V

-1600 1.5V

-1866 1.5V

-2133 1.20V

-2400 1.20V

-2600 1.20V

Main Stream

-800/-1066 1.5V

-1333 1.5V

-1600 1.5V/1.35V

-1600 1.35V

-1600/-2133 1.35V/1.20V

-1600/-2400 1.35V/1.20V

Value -800 -1066 -1333 -1600 -1600 -1600

Technology DDR2/DDR3 DDR3 DDR3 DDR3/DDR4 DDR3/DDR4 DDR3/DDR4

Typical 1yr Speed Cadence Interrupted

Use PC trend to find price sweet spot DDR4 enables the performance and power improvement


LPDDR/DDR technology comparisons


Technical Notes

▶ Power calculator (www.micron.com/products/support/power-calc)

▶ TN-47-20 DDR2 (point to point) package sizes and layout basics.

▶ TN-47-04 Calculating Memory System Power for DDR2

▶ TN-47-01 Design guide for Two-DIMM, unbuffered systems (DDR2)

▶ TN-41-13 DDR3 point-to-point design support

▶ E0593E20 Technical Note: New function of DDR2 SDRAM – On die termination (ODT)

▶ TN-41-13 DDR3 point to point design support

▶ TN-41-08 Design guide for two DDR3-1066 UDIMM systems

▶ TN-41-01 Calculating Memory System power for DDR3

http://www.micron.com/products/support/power-calc




▶ DRAM Technologies


Power

Density




▶ Summary


Density Needs for Boot Memory

Low Density Mid Density High Density

0.5Mb 128Mb 1 Gb 2 Gb 4 Gb 8 Gb 2GB 16 GB 64GB

SPI NOR 0.5Mb to 1Gb

Parallel NOR 32Mb to 2Gb

SLC NAND Small Page 128Mb to 512mb Low Density SLC 1Gb to 4Gb

High Density SLC 8Gb to 128Gb

MLC NAND 16Gb to 512 Gb

Managed NAND eMMC 4GB to 64GB eUSB 2GB to 16 GB


Solutions for different requirements

• Shorter lifecycles • Focus on cost/GB • Expanding markets • Mostly Data Focused

• Longer lifecycles • Ease of use • Diverse products • Lower Floor cost • Code, Code+Data

Lowest Floor Cost ($)

Lowest $/GB

Serial NOR

Parallel NOR

SLC NAND

Managed NAND

MLC NAND

NOR vs. NAND

Customer Requirements Dictate the Solution


Performances consideration for system solutions


Device Throughput

Raw NAND

eMMC

ECC

FTL

On-Die ECC NAND ECC

Host Controller I

NAND Interface FTL ECC LLD

Host Controller II

NAND Interface FTL LLD

Host Controller III

eMMC Interface LLD

NAND BUS

NAND BUS

eMMC BUS

Raw NAND, ECC NAND and eMMC require different management software The correct performance evaluation is at system


Performances consideration for system solutions


Device Throughput

Raw NAND

eMMC

ECC

FTL

On-Die ECC NAND ECC

Host Controller I

NAND Interface FTL ECC LLD

Host Controller II

NAND Interface FTL LLD

Host Controller III

eMMC Interface LLD

NAND BUS

NAND BUS

eMMC BUS

Raw NAND, The evolution of eMMC 5.0 (400MT/s PHY) improves performance capabilities


Flash Architectures – Component Level

All architectures have their advantages Trend in the industry moving toward the lower pin count architectures

NOR NOR

22 | ©2014 Micron Technology, Inc. |

Performance Comparison – Small Data

23 | ©2014 Micron Technology, Inc. |

Performance Comparison – Large Data






Power

Density




▶ Summary


Micron Product Longevity Program (PLP)

▶ Micron’s PLP addresses customer needs to:

Protect their design investments by ensuring a minimum of 10 years of availability on mainstream memory devices

Provide stability to existing designs by offering a 2-year conversion timeline in the event of a part-number change (e.g. die shrink)

▶ Micron’s full product portfolio supported via normal roadmaps:

No change to standard products

PLP products are a subset of the Micron portfolio

▶ Micron’s customers now have a choice:

Buy standard products with existing service and support OR

Buy PLP products to obtain increased longevity and stability


Micron’s Product Longevity Program

▶ Micron is focused on markets requiring long lifecycles: Automotive, industrial, medical…

▶ Micron’s PLP benefits: 10-year longevity from PLP introduction date 2-year conversion timeline:

1-year LTB (last-time buy) + 1-year LTS (last-time ship) from PTN (product-termination notification) date

Automotive Industrial Multi-Market


Micron Has a Proven Track Record…

Micron has a history of supporting memory products for long periods of time…

… and we intend to continue this with PLP!


www.micron.com/plp


Line Card

▶ PLP products are …

High-volume runners

Purchased by large numbers of customers

Suitable for automotive, industrial, medical, and other applications requiring 10-year longevity

▶ PLP Line Card is a subset of the entire Micron portfolio…

Not all product families and densities are represented






Power

Density




▶ Summary


Customers 1. Understand memory usage 2. Understand true cost 3. Work with a trustworthy supplier

What’s next?

Suppliers 1. Provides technology leadership & product longevity 2. Architecture transparency 3. Systems expertise & silicon/solution standards


Automotive

Server Wireless Personal Computing Industrial

Storage Graphics / Consumer Networks

Broadest Portfolio Manufacturing Expertise/Stability ▶ Industry’s broadest portfolio ▶ Computing, server/networking,

embedded, mobile, consumer


Micron’s Product Portfolio

NAND • Discrete and managed solutions, densities 128Mb-64GB • Technology leadership on 20nm • Automotive and industrial qualified e∙MMC™ solutions • Legacy support for low density NAND

NOR • Parallel and Serial NOR product portfolios, densities 512Kb-2Gb+

• Technology leadership on 65nm and 45nm.

• Automotive and industrial qualified solutions


DRAM • Legacy SDRAM through cost/performance leading DDR3/4

offerings • Discrete and module DRAM solutions • High speed RLDDRx Options • Automotive and industrial qualified solutions

Micron’s Product Portfolio


Working with industry leaders

Architecture alignment

Reference designs

Board support package

Third-party enablement

Software solutions

Industry standards

Co-marketing

Schematic reviews

Debug services

Strategic initiatives

Micron is your trusted advisor


Tower Plug In (TWRPI)

Making Informed Memory Choices FTF-IND-F0378 · Power Density ... • Cheapest low density Parallel...

Documents

Transcript of Making Informed Memory Choices FTF-IND-F0378 · Power Density ... • Cheapest low density Parallel...