MachXO2™ Family Data Sheet - Farnell element141-3 Introduction MachXO2 Family Data Sheet...

MachXO2™ Family Data Sheet

DS1035 Version 3.3, March 2017

www.latticesemi.com 1-1 DS1035 Introduction_02.2

May 2016 Data Sheet DS1035

© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Features Flexible Logic Architecture

• Six devices with 256 to 6864 LUT4s and 18 to 334 I/Os

Ultra Low Power Devices• Advanced 65 nm low power process• As low as 22 µW standby power • Programmable low swing differential I/Os • Stand-by mode and other power saving options

Embedded and Distributed Memory• Up to 240 kbits sysMEM™ Embedded Block

RAM• Up to 54 kbits Distributed RAM• Dedicated FIFO control logic

On-Chip User Flash Memory• Up to 256 kbits of User Flash Memory• 100,000 write cycles• Accessible through WISHBONE, SPI, I2C and

JTAG interfaces • Can be used as soft processor PROM or as

Flash memory Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells• Dedicated gearing logic• 7:1 Gearing for Display I/Os• Generic DDR, DDRX2, DDRX4• Dedicated DDR/DDR2/LPDDR memory with

DQS support High Performance, Flexible I/O Buffer

• Programmable sysIO™ buffer supports wide range of interfaces:

– LVCMOS 3.3/2.5/1.8/1.5/1.2– LVTTL– PCI– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL– SSTL 25/18– HSTL 18– Schmitt trigger inputs, up to 0.5 V hysteresis

• I/Os support hot socketing• On-chip differential termination• Programmable pull-up or pull-down mode

Flexible On-Chip Clocking• Eight primary clocks• Up to two edge clocks for high-speed I/O

interfaces (top and bottom sides only)• Up to two analog PLLs per device with

fractional-n frequency synthesis– Wide input frequency range (7 MHz to

400 MHz) Non-volatile, Infinitely Reconfigurable

• Instant-on – powers up in microseconds• Single-chip, secure solution• Programmable through JTAG, SPI or I2C• Supports background programming of non-vola-

tile memory• Optional dual boot with external SPI memory

TransFR™ Reconfiguration • In-field logic update while system operates

Enhanced System Level Support• On-chip hardened functions: SPI, I2C, timer/

counter• On-chip oscillator with 5.5% accuracy• Unique TraceID for system tracking• One Time Programmable (OTP) mode• Single power supply with extended operating

range• IEEE Standard 1149.1 boundary scan• IEEE 1532 compliant in-system programming

Broad Range of Package Options• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,

fpBGA, QFN package options• Small footprint package options

– As small as 2.5 mm x 2.5 mm• Density migration supported• Advanced halogen-free packaging

MachXO2 Family Data SheetIntroduction

1-2

IntroductionMachXO2 Family Data Sheet

Table 1-1. MachXO2™ Family Selection Guide

XO2-256 XO2-640 XO2-640U1 XO2-1200 XO2-1200U1 XO2-2000 XO2-2000U1 XO2-4000 XO2-7000

LUTs 256 640 640 1280 1280 2112 2112 4320 6864

Distributed RAM (kbits) 2 5 5 10 10 16 16 34 54

EBR SRAM (kbits) 0 18 64 64 74 74 92 92 240

Number of EBR SRAM Blocks (9 kbits/block) 0 2 7 7 8 8 10 10 26

UFM (kbits) 0 24 64 64 80 80 96 96 256

Device Options: HC2 Yes Yes Yes Yes Yes Yes Yes Yes Yes

HE3 Yes Yes Yes Yes

ZE4 Yes Yes Yes Yes Yes Yes

Number of PLLs 0 0 1 1 1 1 2 2 2

Hardened Functions:

I2C 2 2 2 2 2 2 2 2 2

SPI 1 1 1 1 1 1 1 1 1

Timer/Coun-ter 1 1 1 1 1 1 1 1 1

Packages IO

25-ball WLCSP5(2.5 mm x 2.5 mm, 0.4 mm) 18

32 QFN6(5 mm x 5 mm, 0.5 mm) 21 21

48 QFN8, 9(7 mm x 7 mm, 0.5 mm) 40 40

49-ball WLCSP5(3.2 mm x 3.2 mm, 0.4 mm) 38

64-ball ucBGA(4 mm x 4 mm, 0.4 mm) 44

84 QFN7(7 mm x 7 mm, 0.5 mm) 68

100-pin TQFP (14 mm x 14 mm) 55 78 79 79

132-ball csBGA(8 mm x 8 mm, 0.5 mm) 55 79 104 104 104

144-pin TQFP(20 mm x 20 mm) 107 107 111 114 114

184-ball csBGA7(8 mm x 8 mm, 0.5 mm) 150

256-ball caBGA(14 mm x 14 mm, 0.8 mm) 206 206 206

256-ball ftBGA(17 mm x 17 mm, 1.0 mm) 206 206 206 206

332-ball caBGA(17 mm x 17 mm, 0.8 mm) 274 278

484-ball ftBGA(23 mm x 23 mm, 1.0 mm) 278 278 334

1. Ultra high I/O device.2. High performance with regulator – VCC = 2.5 V, 3.3 V 3. High performance without regulator – VCC = 1.2 V 4. Low power without regulator – VCC = 1.2 V 5. WLCSP package only available for ZE devices.6. 32 QFN package only available for HC and ZE devices.7. 184 csBGA package only available for HE devices.8. 48-pin QFN information is ‘Advanced’.9. 48 QFN package only available for HC devices.

1-3

IntroductionMachXO2 Family Data Sheet

IntroductionThe MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These fea-tures allow these devices to be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has sev-eral features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices. The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest. Similarly, the high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest. HC devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only accept 1.2 V as the external VCC supply voltage. With the exception of power supply volt-age all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati-bility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin” basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-ilar state machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increas-ing their productivity.

www.latticesemi.com 2-1 DS1035 Architecture_02.3

March 2016 Data Sheet DS1035

© 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Architecture OverviewThe MachXO2 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figure 2-1 and Figure 2-2 show the block diagrams of the various family members.

Figure 2-1. Top View of the MachXO2-1200 Device

Figure 2-2. Top View of the MachXO2-4000 Device

sysMEM EmbeddedBlock RAM (EBR)

sysCLOCK PLL

PIOs Arranged intosysIO Banks

Programmable Function Unitswith Distributed RAM (PFUs)

Embedded FunctionBlock (EFB)

User Flash Memory(UFM)

On-chip ConfigurationFlash Memory

Note: MachXO2-256, and MachXO2-640/U are similar to MachXO2-1200. MachXO2-256 has a lower LUT count and no PLL or EBR blocks. MachXO2-640 has no PLL, a lower LUT count and two EBR blocks. MachXO2-640U has a lower LUT count, one PLL and seven EBR blocks.

sysMEM EmbeddedBlock RAM (EBR)

Programmable Function Unitswith Distributed RAM (PFUs)

On-chip ConfigurationFlash Memory

sysCLOCK PLL

PIOs Arranged intosysIO Banks

EmbeddedFunction Block(EFB)

User FlashMemory (UFM)

Note: MachXO2-1200U, MachXO2-2000/U and MachXO2-7000 are similar to MachXO2-4000. MachXO2-1200U and MachXO2-2000 have a lower LUT count, one PLL, and eight EBR blocks. MachXO2-2000U has a lower LUT count, two PLLs, and 10 EBR blocks. MachXO2-7000 has a higher LUT count, two PLLs, and 26 EBR blocks.

MachXO2 Family Data SheetArchitecture

2-2

ArchitectureMachXO2 Family Data Sheet

The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimen-sional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources.

In the MachXO2 family, the number of sysIO banks varies by device. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these blocks are found in MachXO2-640/U and larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT usage.

The MachXO2 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured, the device enters into user mode with these registers SET/RESET according to the configuration set-ting, allowing device entering to a known state for predictable system function.

The MachXO2 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on MachXO2-640U, MachXO2-1200/U and larger devices. These blocks are located at the ends of the on-chip Flash block. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase rela-tionships of the clocks.

MachXO2 devices provide commonly used hardened functions such as SPI controller, I2C controller and timer/counter. MachXO2-640/U and higher density devices also provide User Flash Memory (UFM). These hardened functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also be accessed through the SPI, I2C and JTAG ports.

Every device in the family has a JTAG port that supports programming and configuration of the device as well as access to the user logic. The MachXO2 devices are available for operation from 3.3 V, 2.5 V and 1.2 V power sup-plies, providing easy integration into the overall system.

PFU BlocksThe core of the MachXO2 device consists of PFU blocks, which can be programmed to perform logic, arithmetic, distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0 to 3 as shown in Figure 2-3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs associated with each PFU block.

2-3


Figure 2-3. PFU Block Diagram

SlicesSlices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2-1 shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-select and wider RAM/ROM functions.

Table 2-1. Resources and Modes Available per Slice

Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi-tive/negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the adjacent PFU). Table 2-2 lists the signals associated with Slices 0-3.

Slice

PFU Block

Resources Modes

Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM



Slice 3 2 LUT4s and 2 Registers Logic, Ripple, ROM

Slice 0

LUT4 & CARRY

LUT4 & CARRY

FF/ Latch

FCIN FCO

D FF/

Latch

D

Slice 1

LUT4 & CARRY

LUT4 & CARRY

Slice 2

LUT4 & CARRY

LUT4 & CARRY

From Routin g

To Routin g

Slice 3

LUT4 & CARRY

LUT4 & CARRY

FF/ Latch

D FF/

Latch

D FF/

Latch

D FF/

Latch

D FF/

Latch

D FF/

Latch

D

2-4


Figure 2-4. Slice Diagram

Table 2-2. Slice Signal Descriptions

Function Type Signal Names Description

Input Data signal A0, B0, C0, D0 Inputs to LUT4

Input Data signal A1, B1, C1, D1 Inputs to LUT4

Input Multi-purpose M0/M1 Multi-purpose input

Input Control signal CE Clock enable

Input Control signal LSR Local set/reset

Input Control signal CLK System clock

Input Inter-PFU signal FCIN Fast carry in1

Output Data signals F0, F1 LUT4 output register bypass signals

Output Data signals Q0, Q1 Register outputs

Output Data signals OFX0 Output of a LUT5 MUX

Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice

Output Inter-PFU signal FCO Fast carry out1

1. See Figure 2-3 for connection details.2. Requires two PFUs.

LUT4 &Carry

Slice

Flip-flop/Latch

OFX0

F0

Q0

CI

CO

LUT4 &Carry

CI

CO

OFX1

F1

Q1

F/SUM

F/SUM D

D

FCI From Different Slice/PFU

Memory &Control Signals

FCO To Different Slice/PFU

LUT5MuxFrom

Routing

ToRouting

For Slices 0 and 1, memory control signals are generated from Slice 2 as follows: • WCK is CLK • WRE is from LSR • DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2 • WAD [A:D] is a 4-bit address from slice 2 LUT input

A0

C0D0

A1B1C1D1

CE

CLK

LSR

M1M0

FXBFXA

B0

Flip-flop/Latch

2-5


Modes of Operation Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.

Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four slices.

Ripple Mode Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following func-tions can be implemented by each slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Up/down counter with asynchronous clear

• Up/down counter with preload (sync)

• Ripple mode multiplier building block

• Multiplier support

• Comparator functions of A and B inputs — A greater-than-or-equal-to B — A not-equal-to B — A less-than-or-equal-to B

Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con-figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-ated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices.

RAM Mode In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0 and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals.

MachXO2 devices support distributed memory initialization.

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in MachXO2 devices, please see TN1201, Memory Usage Guide for MachXO2 Devices.

Table 2-3. Number of Slices Required For Implementing Distributed RAM

SPR 16x4 PDPR 16x4

Number of slices 3 3

Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM

www.latticesemi.com/dynamic/view_document.cfm?document_id=39082

2-6


ROM Mode ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration.

For more information on the RAM and ROM modes, please refer to TN1201, Memory Usage Guide for MachXO2 Devices.

RoutingThere are many resources provided in the MachXO2 devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-ments.

The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2 (spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connec-tions in the horizontal and vertical directions.

The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design.

Clock/Control Distribution NetworkEach MachXO2 device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These eight inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to drive the clock nets. When using a single ended clock input, only the PCLKT input can drive the clock tree directly.

The MachXO2 architecture has three types of clocking resources: edge clocks, primary clocks and secondary high fanout nets. MachXO2-640U, MachXO2-1200/U and higher density devices have two edge clocks each on the top and bottom edges. Lower density devices have no edge clocks. Edge clocks are used to clock I/O registers and have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads, edge clock bridge outputs and CIB sources.

The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals, MachXO2 devices also have eight secondary high fanout signals which can be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the global clock network for internally-generated global clocks and control signals.

The maximum frequency for the primary clock network is shown in the MachXO2 External Switching Characteris-tics table.

The primary clock signals for the MachXO2-256 and MachXO2-640 are generated from eight 17:1 muxes The available clock sources include eight I/O sources and 9 routing inputs. Primary clock signals for the MachXO2-640U, MachXO2-1200/U and larger devices are generated from eight 27:1 muxes The available clock sources include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs.

www.latticesemi.com/dynamic/view_document.cfm?document_id=39082www.latticesemi.com/dynamic/view_document.cfm?document_id=39082

2-7


Figure 2-5. Primary Clocks for MachXO2 Devices

Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2-6. One of the eight inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven come from internal routing. The maximum frequency for the secondary clock network is shown in MachXO2 Exter-nal Switching Characteristics table.

8 11

Clo

ck P

ads

Rou

ting

Primary Clock 0

Primary Clock 1

Primary Clock 2

Primary Clock 3

Primary Clock 4

Primary Clock 5

Primary Clock 6

8

Edg

e C

lock

D

ivid

er

Primary clocks for MachXO2-640U, MachXO2-1200/U and larger devices.

Note: MachXO2-640 and smaller devices do not have inputs from the Edge Clock Divider or PLL and fewer routing inputs. These devices have 17:1 muxes instead of 27:1 muxes.

Primary Clock 7

DynamicClock

Enable

DynamicClock

Enable

DynamicClock

Enable

DynamicClock

Enable

DynamicClock

Enable

27:1

27:1

27:1

27:1

27:1

27:1

27:1

27:1

27:1

27:1

Up to 8

PLL

Out

puts

DynamicClock

Enable

DynamicClock

Enable

DynamicClock

Enable

ClockSwitch

ClockSwitch

2-8


Figure 2-6. Secondary High Fanout Nets for MachXO2 Devices

sysCLOCK Phase Locked Loops (PLLs)The sysCLOCK PLLs provide the ability to synthesize clock frequencies. The MachXO2-640U, MachXO2-1200/U and larger devices have one or more sysCLOCK PLL. CLKI is the reference frequency input to the PLL and its source can come from an external I/O pin or from internal routing. CLKFB is the feedback signal to the PLL which can come from internal routing or an external I/O pin. The feedback divider is used to multiply the reference fre-quency and thus synthesize a higher frequency clock output.

The MachXO2 sysCLOCK PLLs support high resolution (16-bit) fractional-N synthesis. Fractional-N frequency syn-thesis allows the user to generate an output clock which is a non-integer multiple of the input frequency. For more information about using the PLL with Fractional-N synthesis, please see TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide.

Each output has its own output divider, thus allowing the PLL to generate different frequencies for each output. The output dividers can have a value from 1 to 128. The output dividers may also be cascaded together to generate low frequency clocks. The CLKOP, CLKOS, CLKOS2, and CLKOS3 outputs can all be used to drive the MachXO2 clock distribution network directly or general purpose routing resources can be used.

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 2-7.

The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock.

1 7

8:1

8:1

8:1

8:1

8:1

8:1

8:1

8:1

Clock Pads Routing

Secondary High Fanout Net 0









2-9


This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the tLOCK parameter has been satisfied.

The MachXO2 also has a feature that allows the user to select between two different reference clock sources dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table.

The MachXO2 PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are updated through the WISHBONE port the PLL may lose lock and not relock until the tLOCK parameter has been sat-isfied. The timing parameters for the PLL are shown in the sysCLOCK PLL Timing table.

For more details on the PLL and the WISHBONE interface, see TN1199, MachXO2 sysCLOCK PLL Design and Usage Guide.

Figure 2-7. PLL Diagram

Table 2-4 provides signal descriptions of the PLL block.

Table 2-4. PLL Signal Descriptions

Port Name I/O Description

CLKI I Input clock to PLL

CLKFB I Feedback clock

PHASESEL[1:0] I Select which output is affected by Dynamic Phase adjustment ports

PHASEDIR I Dynamic Phase adjustment direction

PHASESTEP I Dynamic Phase step – toggle shifts VCO phase adjust by one step.

CLKOP, CLKOS, CLKOS2, CLKOS3

REFCLK

Internal Feedback

FBKSEL

CLKOP

CLKOS

4

CLKOS2

CLKOS3

REFCLK Divider

M (1 - 40)

LOCK

ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3

RST, RESETM, RESETC, RESETD

CLKFB

CLKI

Dynamic Phase Adjust

PHASESEL[1:0]

PHASEDIR

PHASESTEP

FBKCLK Divider

N (1 - 40)

Fractional-NSynthesizer

Phase detector,VCO, and loop filter.

CLKOS3 Divider

(1 - 128)

CLKOS2 Divider

(1 - 128)

Phase Adjust

Phase Adjust

Phase Adjust/

Edge Trim

CLKOS Divider

(1 - 128)

CLKOP Divider

(1 - 128)

LockDetect

ClkEnSynch

ClkEnSynch

ClkEnSynch

ClkEnSynch

PLLDATO[7:0] , PLLACKPLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]

A0

B0

C0

D0D1

Mux

A2Mux

B2Mux

C2Mux

D2Mux

DPHSRC

Phase Adjust/

Edge TrimSTDBY

B1Mux

C1Mux


2-10


sysMEM Embedded Block RAM MemoryThe MachXO2-640/U and larger devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a 9-kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes including data buffering, PROM for the soft processor and FIFO.

sysMEM Memory BlockThe sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be used in a variety of depths and widths as shown in Table 2-5.

CLKOP O Primary PLL output clock (with phase shift adjustment)

CLKOS O Secondary PLL output clock (with phase shift adjust)

CLKOS2 O Secondary PLL output clock2 (with phase shift adjust)

CLKOS3 O Secondary PLL output clock3 (with phase shift adjust)

LOCK O PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and feed-back signals.

DPHSRC O Dynamic Phase source – ports or WISHBONE is activeSTDBY I Standby signal to power down the PLL

RST I PLL reset without resetting the M-divider. Active high reset.

RESETM I PLL reset - includes resetting the M-divider. Active high reset.

RESETC I Reset for CLKOS2 output divider only. Active high reset.

RESETD I Reset for CLKOS3 output divider only. Active high reset.

ENCLKOP I Enable PLL output CLKOP

ENCLKOS I Enable PLL output CLKOS when port is active

ENCLKOS2 I Enable PLL output CLKOS2 when port is active

ENCLKOS3 I Enable PLL output CLKOS3 when port is active

PLLCLK I PLL data bus clock input signal

PLLRST I PLL data bus reset. This resets only the data bus not any register values.

PLLSTB I PLL data bus strobe signal

PLLWE I PLL data bus write enable signal

PLLADDR [4:0] I PLL data bus address

PLLDATI [7:0] I PLL data bus data input

PLLDATO [7:0] O PLL data bus data output

PLLACK O PLL data bus acknowledge signal

Table 2-4. PLL Signal Descriptions (Continued)

Port Name I/O Description

2-11


Table 2-5. sysMEM Block Configurations

Bus Size MatchingAll of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1, and so on. Although the word size and number of words for each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM OperationIf desired, the contents of the RAM can be pre-loaded during device configuration. EBR initialization data can be loaded from the UFM. To maximize the number of UFM bits, initialize the EBRs used in your design to an all-zero pattern. Initializing to an all-zero pattern does not use up UFM bits. MachXO2 devices have been designed such that multiple EBRs share the same initialization memory space if they are initialized to the same pattern.

By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM.

Memory CascadingLarger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs.

Single, Dual, Pseudo-Dual Port and FIFO ModesFigure 2-8 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM modes, the input data and addresses for the ports are registered at the input of the memory array. The output data of the memory is optionally registered at the memory array output.

Memory Mode Configurations

Single Port

8,192 x 14,096 x 22,048 x 41,024 x 9

True Dual Port

8,192 x 14,096 x 22,048 x 41,024 x 9

Pseudo Dual Port

8,192 x 14,096 x 22,048 x 41,024 x 9512 x 18

FIFO

8,192 x 14,096 x 22,048 x 41,024 x 9512 x 18

2-12


Figure 2-8. sysMEM Memory Primitives

Table 2-6. EBR Signal Descriptions

Port Name Description Active State

CLK Clock Rising Clock Edge

CE Clock Enable Active High

OCE1 Output Clock Enable Active High

RST Reset Active High

BE1 Byte Enable Active High

WE Write Enable Active High

AD Address Bus —

DI Data In —

DO Data Out —

CS Chip Select Active High

AFF FIFO RAM Almost Full Flag —

FF FIFO RAM Full Flag —

AEF FIFO RAM Almost Empty Flag —

EF FIFO RAM Empty Flag —

RPRST FIFO RAM Read Pointer Reset —

1. Optional signals.2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respec-

tively.4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the

read port chip select, ORE is the output read enable.

DI[17:0]

CLKW

WE

FIFO RAM

DO[17:0]

RST

FULLI

AFFFFAEFEF

CLKRRE

CSR[1:0]

ORE

RPRST

CSW[1:0] EMPTYI

ROM

DO[17:0]

AD[12:0]

CLKCE

RST

CS[2:0]

OCEEBR EBR

AD[12:0]DI[8:0]

DO[8:0]

CLKCE

RSTWE

CS[2:0]

OCE

Single-Port RAM

ADA[12:0]

DIA[8:0]

CLKACEA

RSTAWEA

CSA[2:0]

DOA[8:0]OCEA

ADB[12:0]

DI[8:0]

CLKBCEB

RSTBWEBCSB[2:0]

DOB[8:0]OCEB

True Dual Port RAM

ADW[8:0]DI[17:0]

CLKWCEWRST

CSW[2:0]

ADR[12:0]

CLKR

CER

DO[17:0]

CSR[2:0]

OCER

BE[1:0]

Pseudo Dual Port RAM

EBREBREBR

2-13


The EBR memory supports three forms of write behavior for single or dual port operation:

1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths.

2. Write Through – A copy of the input data appears at the output of the same port. This mode is supported for all data widths.

3. Read-Before-Write – When new data is being written, the old contents of the address appears at the output.

FIFO ConfigurationThe FIFO has a write port with data-in, CEW, WE and CLKW signals. There is a separate read port with data-out, RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR. Table 2-7 shows the range of programming values for these flags.

Table 2-7. Programmable FIFO Flag Ranges

The FIFO state machine supports two types of reset signals: RST and RPRST. The RST signal is a global reset that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset state. The RPRST signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the FIFO.

Memory Core ResetThe memory core contains data output latches for ports A and B. These are simple latches that can be reset syn-chronously or asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with port A and port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both ports are as shown in Figure 2-9.

Flag Name Programming Range

Full (FF) 1 to max (up to 2N-1)

Almost Full (AF) 1 to Full-1

Almost Empty (AE) 1 to Full-1

Empty (EF) 0

N = Address bit width.

2-14


Figure 2-9. Memory Core Reset

For further information on the sysMEM EBR block, please refer to TN1201, Memory Usage Guide for MachXO2 Devices.

EBR Asynchronous ResetEBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-10. The GSR input to the EBR is always asynchronous.

Figure 2-10. EBR Asynchronous Reset (Including GSR) Timing Diagram

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during device wake up must occur before the release of the device I/Os becoming active.

These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR sig-nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-10. The reset timing rules apply to the RPReset input versus the RE input and the RST input versus the WE and RE inputs. Both RST and RPReset are always asynchronous EBR inputs. For more details refer to TN1201, Memory Usage Guide for MachXO2 Devices.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

QSETD

Output Data Latches

Memory Core Port A[18:0]

QSETD Port B[18:0]

RSTB

GSRN

Programmable Disable

RSTA

Reset

Clock

Clock Enable

www.latticesemi.com/dynamic/view_document.cfm?document_id=39082www.latticesemi.com/dynamic/view_document.cfm?document_id=39082www.latticesemi.com/dynamic/view_document.cfm?document_id=39082www.latticesemi.com/dynamic/view_document.cfm?document_id=39082

2-15


Programmable I/O Cells (PIC)The programmable logic associated with an I/O is called a PIO. The individual PIO are connected to their respec-tive sysIO buffers and pads. On the MachXO2 devices, the PIO cells are assembled into groups of four PIO cells called a Programmable I/O Cell or PIC. The PICs are placed on all four sides of the device.

On all the MachXO2 devices, two adjacent PIOs can be combined to provide a complementary output driver pair.

The MachXO2-640U, MachXO2-1200/U and higher density devices contain enhanced I/O capability. All PIO pairs on these larger devices can implement differential receivers. Half of the PIO pairs on the top edge of these devices can be configured as true LVDS transmit pairs. The PIO pairs on the bottom edge of these higher density devices have on-chip differential termination and also provide PCI support.

2-16


Figure 2-11. Group of Four Programmable I/O Cells

1 PIC

PIO A

Output Register Block

& Tristate Register Block

Pin A

Input Register Block

PIO B



Pin B


PIO C



Pin C


Notes:1. Input gearbox is available only in PIC on the bottom edge of MachXO2-640U, MachXO2-1200/U and larger devices.2. Output gearbox is available only in PIC on the top edge of MachXO2-640U, MachXO2-1200/U and larger devices.

PIO D



Pin D


Core Logic/Routing

InputGearbox

OutputGearbox

2-17


PIO The PIO contains three blocks: an input register block, output register block and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic.

Table 2-8. PIO Signal List

Input Register Block The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condi-tion high-speed interface signals before they are passed to the device core. In addition to this functionality, the input register blocks for the PIOs on the right edge include built-in logic to interface to DDR memory.

Figure 2-12 shows the input register block for the PIOs located on the left, top and bottom edges. Figure 2-13 shows the input register block for the PIOs on the right edge.

Left, Top, Bottom EdgesInput signals are fed from the sysIO buffer to the input register block (as signal D). If desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK). If an input delay is desired, users can select a fixed delay. I/Os on the bottom edge also have a dynamic delay, DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK) by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams.

Pin Name I/O Type Description

CE Input Clock Enable

D Input Pin input from sysIO buffer.

INDD Output Register bypassed input.

INCK Output Clock input

Q0 Output DDR positive edge input

Q1 Output Registered input/DDR negative edge input

D0 Input Output signal from the core (SDR and DDR)

D1 Input Output signal from the core (DDR)

TD Input Tri-state signal from the core

Q Output Data output signals to sysIO Buffer

TQ Output Tri-state output signals to sysIO Buffer

DQSR901 Input DQS shift 90-degree read clock

DQSW901 Input DQS shift 90-degree write clock

DDRCLKPOL1 Input DDR input register polarity control signal from DQS

SCLK Input System clock for input and output/tri-state blocks.

RST Input Local set reset signal

1. Available in PIO on right edge only.

2-18


Figure 2-12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges)

Right EdgeThe input register block on the right edge is a superset of the same block on the top, bottom, and left edges. In addition to the modes described above, the input register block on the right edge also supports DDR memory mode.

In DDR memory mode, two registers are used to sample the data on the positive and negative edges of the modi-fied DQS (DQSR90) in the DDR Memory mode creating two data streams. Before entering the core, these two data streams are synchronized to the system clock to generate two data streams.

The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-quate timing when data is transferred to the system clock domain from the DQS domain. The DQSR90 and DDRCLKPOL signals are generated in the DQS read-write block.

Figure 2-13. MachXO2 Input Register Block Diagram (PIO on Right Edge)

SCLK

INCK

Q1

Q0

INDD

D

Q0

Q1

D Q

ProgrammableDelay Cell D/L Q D Q

D Q

Q1

Q0

INDD

D

DQSR90

Q0

Q1

SCLK

S0

S1

DDRCLKPOL

ProgrammableDelay Cell D/L Q

INCK

D Q

D Q D Q

D Q D Q D Q

D Q

2-19


Output Register Block The output register block registers signals from the core of the device before they are passed to the sysIO buffers.

Left, Top, Bottom EdgesIn SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type register or latch.

In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.

Figure 2-14 shows the output register block on the left, top and bottom edges.

Figure 2-14. MachXO2 Output Register Block Diagram (PIO on the Left, Top and Bottom Edges)

Right EdgeThe output register block on the right edge is a superset of the output register on left, top and bottom edges of the device. In addition to supporting SDR and Generic DDR modes, the output register blocks for PIOs on the right edge include additional logic to support DDR-memory interfaces. Operation of this block is similar to that of the out-put register block on other edges.

In DDR memory mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge the registered D1 input is registered into the register Q1. A multiplexer running off the DQSW90 signal is used to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output.

Figure 2-15 shows the output register block on the right edge.

Output path

TQ D/L Q TD

Tri-state path

Q

D1 D Q D Q Q1

D/L QQ0

D0

SCLK

2-20


Figure 2-15. MachXO2 Output Register Block Diagram (PIO on the Right Edges)

Tri-state Register Block The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output.

The tri-state register blocks on the right edge contain an additional register for DDR memory operation. In DDR memory mode, the register TS input is fed into another register that is clocked using the DQSW90 signal. The out-put of this register is used as a tri-state control.

Input Gearbox Each PIC on the bottom edge has a built-in 1:8 input gearbox. Each of these input gearboxes may be programmed as a 1:7 de-serializer or as one IDDRX4 (1:8) gearbox or as two IDDRX2 (1:4) gearboxes. Table 2-9 shows the gearbox signals.

Table 2-9. Input Gearbox Signal List

Name I/O Type Description

D Input High-speed data input after programmable delay in PIO A input register block

ALIGNWD Input Data alignment signal from device core

SCLK Input Slow-speed system clock

ECLK[1:0] Input High-speed edge clock

RST Input Reset

Q[7:0] Output Low-speed data to device core:Video RX(1:7): Q[6:0]GDDRX4(1:8): Q[7:0]GDDRX2(1:4)(IOL-A): Q4, Q5, Q6, Q7GDDRX2(1:4)(IOL-C): Q0, Q1, Q2, Q3

D Q D1 D Q Q1

D/L QQ0

D0

DQSW90

Q

SCLK

D Q TQ D/L Q T0 TD


Tristate Register Block

2-21


These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. Figure 2-16 shows a block diagram of the input gearbox.

Figure 2-16. Input Gearbox

D Q

D

ECLK0/1 SCLK

Q21

Q0_

S2

S0 D Q

D QT2

T0 Q0

Q2

D Q

D QCE

D QCE

D QQ65

Q43

S6

S4 D Q

D QT6

T4 D Q

D QCE

D QCE

D QQ54

Q_6

S3

S5 D

DT3

T5

Q6

D Q

D QCE

D QCE

D QQ10

Q32

S1 D

T1

D Q

D QCE

Q65

Q65

Q43

Q43

Q21

Q10

Q21

Q32

Q54

Q_6

Q54

Q32

SEL0

Q4

Q5

Q1

Q3

S7 D Q

T7 D QCE

Q7

UPDATE

Q_6

2-22


More information on the input gearbox is available in TN1203, Implementing High-Speed Interfaces with MachXO2 Devices.

Output Gearbox Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2-10 shows the gearbox signals.

Table 2-10. Output Gearbox Signal List

The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the low-speed system clock. The second stage registers transfer data from the low-speed clock registers to the high-speed clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the high-speed data out to the sysIO buffer. Figure 2-17 shows the output gearbox block diagram.

Name I/O Type Description

Q Output High-speed data output

D[7:0] Input Low-speed data from device core

Video TX(7:1): D[6:0]

GDDRX4(8:1): D[7:0]

GDDRX2(4:1)(IOL-A): D[3:0]

GDDRX2(4:1)(IOL-C): D[7:4]

SCLK Input Slow-speed system clock

ECLK [1:0] Input High-speed edge clock

RST Input Reset


2-23


Figure 2-17. Output Gearbox

More information on the output gearbox is available in TN1203, Implementing High-Speed Interfaces with MachXO2 Devices.

D4

D0

D3

D1 S1T1

S0

QC

ODDRx2_A

ODDRx2_C

ODDRx2_C

ECLK0/1

Q45

Q67

S4

S6D Q

D QT4

T6D6 D Q

D QCE

D QCE

01

01

Q01

Q23

S0

S2

T0

T2

Q32

Q10

S5

S3

D Q T5

T3

CE01

D QQ76

Q54

S7D Q T7

D Q

D Q

D Q

CE01

S2

S4

GND

S7

S6

S5

S3D2

D7

D5

SCLK

01

01

01

1

01

Q34

Q56

Q67

GND

Q45

S1

Q12

SEL /0

UPDATE

Q23

Q/QA

D Q

D Q

D Q

D Q

D QD Q

D Q

D Q

D Q

D Q

D Q

0

10

10

10

10

10

CE

CE

D QCE

D QCE

01

01


2-24


DDR Memory Support Certain PICs on the right edge of MachXO2-640U, MachXO2-1200/U and larger devices, have additional circuitry to allow the implementation of DDR memory interfaces. There are two groups of 14 or 12 PIOs each on the right edge with additional circuitry to implement DDR memory interfaces. This capability allows the implementation of up to 16-bit wide memory interfaces. One PIO from each group contains a control element, the DQS Read/Write Block, to facilitate the generation of clock and control signals (DQSR90, DQSW90, DDRCLKPOL and DATAVALID). These clock and control signals are distributed to the other PIO in the group through dedicated low skew routing.

DQS Read Write Block Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock (referred to as DQS) is not free-running so this approach cannot be used. The DQS Read Write block provides the required clock alignment for DDR memory interfaces. DQSR90 and DQSW90 signals are generated by the DQS Read Write block from the DQS input.

In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the read cycle) is unknown. The MachXO2 family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used. This circuit changes the edge on which the data is registered in the synchronizing registers in the input register block. This requires evaluation at the start of each read cycle for the correct clock polarity. Prior to the read operation in DDR memories, DQS is in tri-state (pulled by termination). The DDR memory device drives DQS low at the start of the preamble state. A dedicated circuit in the DQS Read Write block detects the first DQS rising edge after the preamble state and generates the DDRCLKPOL signal. This signal is used to control the polarity of the clock to the synchronizing registers.

The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration signals (6-bit bus) from a DLL on the right edge of the device. The DLL loop is compensated for temperature, volt-age and process variations by the system clock and feedback loop.

sysIO BufferEach I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement a wide variety of standards that are found in today’s systems including LVCMOS, TTL, PCI, SSTL, HSTL, LVDS, BLVDS, MLVDS and LVPECL.

Each bank is capable of supporting multiple I/O standards. In the MachXO2 devices, single-ended output buffers, ratioed input buffers (LVTTL, LVCMOS and PCI), differential (LVDS) and referenced input buffers (SSTL and HSTL) are powered using I/O supply voltage (VCCIO). Each sysIO bank has its own VCCIO. In addition, each bank has a voltage reference, VREF, which allows the use of referenced input buffers independent of the bank VCCIO.

MachXO2-256 and MachXO2-640 devices contain single-ended ratioed input buffers and single-ended output buf-fers with complementary outputs on all the I/O banks. Note that the single-ended input buffers on these devices do not contain PCI clamps. In addition to the single-ended I/O buffers these two devices also have differential and ref-erenced input buffers on all I/Os. The I/Os are arranged in pairs, the two pads in the pair are described as “T” and “C”, where the true pad is associated with the positive side of the differential input buffer and the comp (comple-mentary) pad is associated with the negative side of the differential input buffer.

2-25


MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 devices contain three types of sysIO buffer pairs.

1. Left and Right sysIO Buffer PairsThe sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the left and right of the devices also have differential and referenced input buffers.

2. Bottom sysIO Buffer PairsThe sysIO buffer pairs in the bottom bank of the device consist of two single-ended output drivers and two sin-gle-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the bottom also have differential and referenced input buffers. Only the I/Os on the bottom banks have programmable PCI clamps and differential input termination. The PCI clamp is enabled after VCC and VCCIO are at valid operating levels and the device has been configured.

3. Top sysIO Buffer PairsThe sysIO buffer pairs in the top bank of the device consist of two single-ended output drivers and two single-ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have differ-ential and referenced I/O buffers. Half of the sysIO buffer pairs on the top edge have true differential outputs. The sysIO buffer pair comprising of the A and B PIOs in every PIC on the top edge have a differential output driver. The referenced input buffer can also be configured as a differential input buffer.

Typical I/O Behavior During Power-upThe internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 have reached VPORUP level defined in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure that all VCCIO banks are active with valid input logic levels to properly control the output logic states of all the I/O banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a weak pull-down to GND (some pins such as PROGRAMN and the JTAG pins have weak pull-up to VCCIO as the default func-tionality). The I/O pins will maintain the blank configuration until VCC and VCCIO (for I/O banks containing configura-tion I/Os) have reached VPORUP levels at which time the I/Os will take on the user-configured settings only after a proper download/configuration.

Supported StandardsThe MachXO2 sysIO buffer supports both single-ended and differential standards. Single-ended standards can be further subdivided into LVCMOS, LVTTL, and PCI. The buffer supports the LVTTL, PCI, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3 V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS, MLVDS and LVPECL output emulation is supported on all devices. The MachXO2-640U, MachXO2-1200/U and higher devices support on-chip LVDS output buffers on approximately 50% of the I/Os on the top bank. Differential receivers for LVDS, BLVDS, MLVDS and LVPECL are supported on all banks of MachXO2 devices. PCI support is provided in the bottom bank of theMachXO2-640U, MachXO2-1200/U and higher density devices. Table 2-11 sum-marizes the I/O characteristics of the MachXO2 PLDs.

Tables 2-11 and 2-12 show the I/O standards (together with their supply and reference voltages) supported by the MachXO2 devices. For further information on utilizing the sysIO buffer to support a variety of standards please see TN1202, MachXO2 sysIO Usage Guide.


2-26


Table 2-11. I/O Support Device by Device

Table 2-12. Supported Input Standards

MachXO2-256, MachXO2-640

MachXO2-640U,MachXO2-1200

MachXO2-1200UMachXO2-2000/U, MachXO2-4000, MachXO2-7000

Number of I/O Banks 4 4 6

Type of Input BuffersSingle-ended (all I/O banks)

Differential Receivers (all I/O banks)

Single-ended (all I/O banks)


Differential input termination (bottom side)

Single-ended (all I/O banks)


Differential input termination (bottom side)

Types of Output BuffersSingle-ended buffers with complementary outputs (all I/O banks)

Single-ended buffers with complementary outputs (all I/O banks)

Differential buffers with true LVDS outputs (50% on top side)

Single-ended buffers with complementary outputs (all I/O banks)

Differential buffers with true LVDS outputs (50% on top side)

Differential Output Emulation Capability All I/O banks All I/O banks All I/O banks

PCI Clamp Support No Clamp on bottom side only Clamp on bottom side only

VCCIO (Typ.)

Input Standard 3.3 V 2.5 V 1.8 V 1.5 1.2 V

Single-Ended Interfaces

LVTTL 2 2 2

LVCMOS33 2 2 2

LVCMOS25 2 2 2

LVCMOS18 2 2 2

LVCMOS15 2 2 2 2

LVCMOS12 2 2 2 2

PCI1

SSTL18 (Class I, Class II)

SSTL25 (Class I, Class II)

HSTL18 (Class I, Class II)

Differential Interfaces

LVDS

BLVDS, MVDS, LVPECL, RSDS

MIPI3

Differential SSTL18 Class I, II

Differential SSTL25 Class I, II

Differential HSTL18 Class I, II

1. Bottom banks of MachXO2-640U, MachXO2-1200/U and higher density devices only.2. Reduced functionality. Refer to TN1202, MachXO2 sysIO Usage Guide for more detail.3. These interfaces can be emulated with external resistors in all devices.


2-27


Table 2-13. Supported Output Standards

sysIO Buffer BanksThe numbers of banks vary between the devices of this family. MachXO2-1200U, MachXO2-2000/U and higher density devices have six I/O banks (one bank on the top, right and bottom side and three banks on the left side). The MachXO2-1200 and lower density devices have four banks (one bank per side). Figures 2-18 and 2-19 show the sysIO banks and their associated supplies for all devices.

Output Standard VCCIO (Typ.)

Single-Ended Interfaces

LVTTL 3.3

LVCMOS33 3.3

LVCMOS25 2.5

LVCMOS18 1.8

LVCMOS15 1.5

LVCMOS12 1.2

LVCMOS33, Open Drain —





PCI33 3.3

SSTL25 (Class I) 2.5

SSTL18 (Class I) 1.8

HSTL18(Class I) 1.8

Differential Interfaces

LVDS1, 2 2.5, 3.3

BLVDS, MLVDS, RSDS 2 2.5

LVPECL2 3.3

MIPI2 2.5

Differential SSTL18 1.8

Differential SSTL25 2.5

Differential HSTL18 1.8

1. MachXO2-640U, MachXO2-1200/U and larger devices have dedicated LVDS buffers.2. These interfaces can be emulated with external resistors in all devices.

2-28


Figure 2-18. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 Banks

Figure 2-19. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks

Bank 0

Bank 1

Bank 2Ban

k 3

Ban

k 4

Ban

k 5

VCCIO0

VCCIO2GND

GND

VCCIO1

GND

GND

GND

GND

VCCIO5

VCCIO4

VCCIO3

Bank 0

Bank 1

Bank 2

Ban

k 3

VCCIO0

VCCIO2GND

GND

VCCIO1

GND

VCCIO3

GND

2-29


Hot SocketingThe MachXO2 devices have been carefully designed to ensure predictable behavior during power-up and power-down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system. These capabilities make the MachXO2 ideal for many multiple power supply and hot-swap applica-tions.

On-chip OscillatorEvery MachXO2 device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes place:

1. Device powers up with a nominal MCLK frequency of 2.08 MHz.

2. During configuration, users select a different master clock frequency.

3. The MCLK frequency changes to the selected frequency once the clock configuration bits are received.

4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK fre-quency of 2.08 MHz.

Table 2-14 lists all the available MCLK frequencies.

Table 2-14. Available MCLK Frequencies

Embedded Hardened IP Functions and User Flash MemoryAll MachXO2 devices provide embedded hardened functions such as SPI, I2C and Timer/Counter. MachXO2-640/U and higher density devices also provide User Flash Memory (UFM). These embedded blocks interface through the WISHBONE interface with routing as shown in Figure 2-20.

MCLK (MHz, Nominal) MCLK (MHz, Nominal) MCLK (MHz, Nominal)

2.08 (default) 9.17 33.25

2.46 10.23 38

3.17 13.3 44.33

4.29 14.78 53.2

5.54 20.46 66.5

7 26.6 88.67

8.31 29.56 133

2-30


Figure 2-20. Embedded Function Block Interface

Hardened I2C IP CoreEvery MachXO2 device contains two I2C IP cores. These are the primary and secondary I2C IP cores. Either of the two cores can be configured either as an I2C master or as an I2C slave. The only difference between the two IP cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core.

When the IP core is configured as a master it will be able to control other devices on the I2C bus through the inter-face. When the core is configured as the slave, the device will be able to provide I/O expansion to an I2C Master. The I2C cores support the following functionality:

• Master and Slave operation

• 7-bit and 10-bit addressing

• Multi-master arbitration support

• Up to 400 kHz data transfer speed

• General call support

• Interface to custom logic through 8-bit WISHBONE interface

Embedded Function Block (EFB)

CoreLogic/

RoutingEFB

WISHBONE Interface

I2C (Primary)

I2C (Secondary)

SPI

Timer/Counter

PLL0 PLL1

ConfigurationLogic

UFM

I/Os for I2C (Primary)

I/Os for SPI

I/Os for I2C (Secondary)

Indicates connectionthrough core logic/routing.

PowerControl

2-31


Figure 2-21. I2C Core Block Diagram

Table 2-15 describes the signals interfacing with the I2C cores.

Table 2-15. I2C Core Signal Description

Hardened SPI IP CoreEvery MachXO2 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core is configured as a master it will be able to control other SPI enabled chips connected to the SPI bus. When the core is configured as the slave, the device will be able to interface to an external SPI master. The SPI IP core on MachXO2 devices supports the following functions:

• Configurable Master and Slave modes

• Full-Duplex data transfer

• Mode fault error flag with CPU interrupt capability

• Double-buffered data register

• Serial clock with programmable polarity and phase

• LSB First or MSB First Data Transfer

• Interface to custom logic through 8-bit WISHBONE interface

Signal Name I/O Description

i2c_scl Bi-directional

Bi-directional clock line of the I2C core. The signal is an output if the I2C core is in master mode. The signal is an input if the I2C core is in slave mode. MUST be routed directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for detailed pad and pin locations of I2C ports in each MachXO2 device.

i2c_sda Bi-directional

Bi-directional data line of the I2C core. The signal is an output when data is transmitted from the I2C core. The signal is an input when data is received into the I2C core. MUST be routed directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for detailed pad and pin locations of I2C ports in each MachXO2 device.

i2c_irqo Output

Interrupt request output signal of the I2C core. The intended usage of this signal is for it to be connected to the WISHBONE master controller (i.e. a microcontroller or state machine) and request an interrupt when a specific condition is met. These conditions are described with the I2C register definitions.

cfg_wake OutputWake-up signal – To be connected only to the power module of the MachXO2 device. The signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C Tab.

cfg_stdby OutputStand-by signal – To be connected only to the power module of the MachXO2 device. The signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I2C Tab.

EFB

SCL

SDA

ConfigurationLogic

CoreLogic/

Routing

PowerControl

I2CRegisters

EFBWISHBONE

Interface

ControlLogic

I2C Function

2-32


There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes:

• TN1087, Minimizing System Interruption During Configuration Using TransFR Technology (Appendix B)

• TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices

Figure 2-22. SPI Core Block Diagram

Table 2-16 describes the signals interfacing with the SPI cores.

Table 2-16. SPI Core Signal Description

Signal Name I/O Master/Slave Description

spi_csn[0] O Master SPI master chip-select output

spi_csn[1..7] O Master Additional SPI chip-select outputs (total up to eight slaves)

spi_scsn I Slave SPI slave chip-select input

spi_irq O Master/Slave Interrupt request

spi_clk I/O Master/Slave SPI clock. Output in master mode. Input in slave mode.

spi_miso I/O Master/Slave SPI data. Input in master mode. Output in slave mode.

spi_mosi I/O Master/Slave SPI data. Output in master mode. Input in slave mode.

ufm_sn I Slave Configuration Slave Chip Select (active low), dedicated for selecting theUser Flash Memory (UFM).

cfg_stdby O Master/SlaveStand-by signal – To be connected only to the power module of the MachXO2 device. The signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, SPI Tab.

cfg_wake O Master/SlaveWake-up signal – To be connected only to the power module of the MachXO2 device. The signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, SPI Tab.

EFBSPI Function

CoreLogic/

Routing EFB

WISHBONE Interface

SPIRegisters

ControlLogic

ConfigurationLogic

MISO

MOSI

SCK

MCSN

SCSN


2-33


Hardened Timer/CounterMachXO2 devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional, 16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter sup-ports the following functions:

• Supports the following modes of operation:— Watchdog timer— Clear timer on compare match— Fast PWM— Phase and Frequency Correct PWM

• Programmable clock input source

• Programmable input clock prescaler

• One static interrupt output to routing

• One wake-up interrupt to on-chip standby mode controller.

• Three independent interrupt sources: overflow, output compare match, and input capture

• Auto reload

• Time-stamping support on the input capture unit

• Waveform generation on the output

• Glitch-free PWM waveform generation with variable PWM period

• Internal WISHBONE bus access to the control and status registers

• Stand-alone mode with preloaded control registers and direct reset input

Figure 2-23. Timer/Counter Block Diagram

Table 2-17. Timer/Counter Signal Description

Port I/O Description

tc_clki I Timer/Counter input clock signal

tc_rstn I Register tc_rstn_ena is preloaded by configuration to always keep this pin enabled

tc_ic I Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If enabled, a rising edge of this signal will be detected and synchronized to capture tc_cnt value into tc_icr for time-stamping.

tc_int O Without WISHBONE – Can be used as overflow flagWith WISHBONE – Controlled by three IRQ registers

tc_oc O Timer counter output signal

EFB Timer/Counter

CoreLogic

RoutingPWM

EFBWISHBONE

Interface

Timer/Counter

Registers

ControlLogic

2-34


For more details on these embedded functions, please refer to TN1205, Using User Flash Memory and Hardened Control Functions in MachXO2 Devices.

User Flash Memory (UFM)MachXO2-640/U and higher density devices provide a User Flash Memory block, which can be used for a variety of applications including storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a general purpose user Flash memory. The UFM block connects to the device core through the embedded function block WISHBONE interface. Users can also access the UFM block through the JTAG, I2C and SPI interfaces of the device. The UFM block offers the following features:

• Non-volatile storage up to 256 kbits

• 100K write cycles

• Write access is performed page-wise; each page has 128 bits (16 bytes)

• Auto-increment addressing

• WISHBONE interface

For more information on the UFM, please refer to TN1205, Using User Flash Memory and Hardened Control Func-tions in MachXO2 Devices.

Standby Mode and Power Saving OptionsMachXO2 devices are available in three options for maximum flexibility: ZE, HC and HE devices. The ZE devices have ultra low static and dynamic power consumption. These devices use a 1.2 V core voltage that further reduces power consumption. The HC and HE devices are designed to provide high performance. The HC devices have a built-in voltage regulator to allow for 2.5 V VCC and 3.3 V VCC while the HE devices operate at 1.2 V VCC.

MachXO2 devices have been designed with features that allow users to meet the static and dynamic power requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings, MachXO2 devices support an ultra low power Stand-by mode. While most of these features are available in all three device types, these features are mainly intended for use with MachXO2 ZE devices to manage power con-sumption.

In the stand-by mode the MachXO2 devices are powered on and configured. Internal logic, I/Os and memories are switched on and remain operational, as the user logic waits for an external input. The device enters this mode when the standby input of the standby controller is toggled or when an appropriate I2C or JTAG instruction is issued by an external master. Various subsystems in the device such as the band gap, power-on-reset circuitry etc can be configured such that they are automatically turned “off” or go into a low power consumption state to save power when the device enters this state. Note that the MachXO2 devices are powered on when in standby mode and all power supplies should remain in the Recommended Operating Conditions.

www.latticesemi.com/dynamic/view_document.cfm?document_id=39086www.latticesemi.com/dynamic/view_document.cfm?document_id=39086www.latticesemi.com/dynamic/view_document.cfm?document_id=39086www.latticesemi.com/dynamic/view_document.cfm?document_id=39086

2-35


Table 2-18. MachXO2 Power Saving Features Description

For more details on the standby mode refer to TN1198, Power Estimation and Management for MachXO2 Devices.

Power On ResetMachXO2 devices have power-on reset circuitry to monitor VCCINT and VCCIO voltage levels during power-up and operation. At power-up, the POR circuitry monitors VCCINT and VCCIO0 (controls configuration) voltage levels. It then triggers download from the on-chip configuration Flash memory after reaching the VPORUP level specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For devices without voltage regulators (ZE and HE devices), VCCINT is the same as the VCC supply voltage. For devices with voltage regulators (HC devices), VCCINT is regulated from the VCC supply voltage. From this voltage reference, the time taken for configuration and entry into user mode is specified as Flash Download Time (tREFRESH) in the DC and Switching Characteristics section of this data sheet. Before and during configuration, the I/Os are held in tri-state. I/Os are released to user functionality once the device has finished configuration. Note that for HC devices, a separate POR circuit monitors external VCC voltage in addition to the POR circuit that monitors the internal post-regulated power supply voltage level.

Once the device enters into user mode, the POR circuitry can optionally continue to monitor VCCINT levels. If VCCINT drops below VPORDNBG level (with the bandgap circuitry switched on) or below VPORDNSRAM level (with the bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation the POR issues a reset and begins monitoring the VCCINT and VCCIO voltage levels. VPORDNBG and VPORDNSRAMare both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet.

Note that once a ZE or HE device enters user mode, users can switch off the bandgap to conserve power. When the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a mini-mal, low power POR circuit is still operational (this corresponds to the VPORDNSRAM reset point described in the paragraph above). However this circuit is not as accurate as the one that operates when the bandgap is switched on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells flip. If users are concerned about the VCC supply dropping below VCC (min) they should not shut down the bandgap or POR circuit.

Device Subsystem Feature Description

BandgapThe bandgap can be turned off in standby mode. When the Bandgap is turned off, ana-log circuitry such as the POR, PLLs, on-chip oscillator, and referenced and differential I/O buffers are also turned off. Bandgap can only be turned off for 1.2 V devices.

Power-On-Reset (POR)

The POR can be turned off in standby mode. This monitors VCC levels. In the event of unsafe VCC drops, this circuit reconfigures the device. When the POR circuitry is turned off, limited power detector circuitry is still active. This option is only recommended for ap-plications in which the power supply rails are reliable.

On-Chip Oscillator The on-chip oscillator has two power saving features. It may be switched off if it is not needed in your design. It can also be turned off in Standby mode.

PLL

Similar to the on-chip oscillator, the PLL also has two power saving features. It can be statically switched off if it is not needed in a design. It can also be turned off in Standby mode. The PLL will wait until all output clocks from the PLL are driven low before power-ing off.

I/O Bank Controller

Referenced and differential I/O buffers (used to implement standards such as HSTL, SSTL and LVDS) consume more than ratioed single-ended I/Os such as LVCMOS and LVTTL. The I/O bank controller allows the user to turn these I/Os off dynamically on a per bank selection.

Dynamic Clock Enable for Primary Clock Nets Each primary clock net can be dynamically disabled to save power.

Power Guard

Power Guard is a feature implemented in input buffers. This feature allows users to switch off the input buffer when it is not needed. This feature can be used in both clock and data paths. Its biggest impact is that in the standby mode it can be used to switch off clock inputs that are distributed using general routing resources.


2-36


Configuration and TestingThis section describes the configuration and testing features of the MachXO2 family.

IEEE 1149.1-Compliant Boundary Scan TestabilityAll MachXO2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with VCCIOBank 0 and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.

For more details on boundary scan test, see AN8066, Boundary Scan Testability with Lattice sysIO Capability and TN1087, Minimizing System Interruption During Configuration Using TransFR Technology.

Device ConfigurationAll MachXO2 devices contain two ports that can be used for device configuration. The Test Access Port (TAP), which supports bit-wide configuration and the sysCONFIG port which supports serial configuration through I2C or SPI. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532 In-System Configuration specification. There are various ways to configure a MachXO2 device:

1. Internal Flash Download

2. JTAG

3. Standard Serial Peripheral Interface (Master SPI mode) – interface to boot PROM memory

4. System microprocessor to drive a serial slave SPI port (SSPI mode)

5. Standard I2C Interface to system microprocessor

Upon power-up, the configuration SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be activated any time after power-up by sending the appropriate command through the TAP port. Optionally the de-vice can run a CRC check upon entering the user mode. This will ensure that the device was configured correctly.

The sysCONFIG port has 10 dual-function pins which can be used as general purpose I/Os if they are not required for configuration. See TN1204, MachXO2 Programming and Configuration Usage Guide for more information about using the dual-use pins as general purpose I/Os.

Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO2 devices. Use of this technology allows Lattice to provide a lower cost solution. In the unlikely event that this technol-ogy is unable to compress bitstreams to fit into the amount of on-chip Flash memory, there are a variety of tech-niques that can be utilized to allow the bitstream to fit in the on-chip Flash memory. For more details, refer to TN1204, MachXO2 Programming and Configuration Usage Guide.

The Test Access Port (TAP) has five dual purpose pins (TDI, TDO, TMS, TCK and JTAGENB). These pins are dual function pins - TDI, TDO, TMS and TCK can be used as general purpose I/O if desired. For more details, refer to TN1204, MachXO2 Programming and Configuration Usage Guide.

TransFR (Transparent Field Reconfiguration)TransFR is a unique Lattice technology that allows users to update their logic in the field without interrupting sys-tem operation using a simple push-button solution. For more details refer to TN1087, Minimizing System Interrup-tion During Configuration Using TransFR Technology for details.

www.latticesemi.com/dynamic/view_document.cfm?document_id=21638www.latticesemi.com/dynamic/view_document.cfm?document_id=21638www.latticesemi.com/dynamic/view_document.cfm?document_id=39085www.latticesemi.com/dynamic/view_document.cfm?document_id=3468www.latticesemi.com/dynamic/view_document.cfm?document_id=39085www.latticesemi.com/dynamic/view_document.cfm?document_id=39085www.latticesemi.com/dynamic/view_document.cfm?document_id=21638

2-37


When implementing background programming of the on-chip Flash, care must be taken for the operation of the PLL. For devices that have two PLLs (XO2-2000U, -4000 and -7000), the system must put the RPLL (Right-side PLL) in reset state during the background Flash programming. More detailed description can be found in TN1204, MachXO2 Programming and Configuration Usage Guide.

Security and One-Time Programmable Mode (OTP)For applications where security is important, the lack of an external bitstream provides a solution that is inherently more secure than SRAM-based FPGAs. This is further enhanced by device locking. MachXO2 devices contain security bits that, when set, prevent the readback of the SRAM configuration and non-volatile Flash memory spaces. The device can be in one of two modes:

1. Unlocked – Readback of the SRAM configuration and non-volatile Flash memory spaces is allowed.

2. Permanently Locked – The device is permanently locked.

Once set, the only way to clear the security bits is to erase the device. To further complement the security of the device, a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to erase or re-program the Flash and SRAM OTP portions of the device. For more details, refer to TN1204, MachXO2 Programming and Configuration Usage Guide.

Dual BootMachXO2 devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. If the primary bits

MachXO2™ Family Data Sheet - Farnell element141-3 Introduction MachXO2 Family Data Sheet...

Documents

Transcript of MachXO2™ Family Data Sheet - Farnell element141-3 Introduction MachXO2 Family Data Sheet...