MachXO2 Dual Sensor Interface Board · 2014-07-25 · 3 MachXO2 Dual Sensor Interface Board Lattice...
Transcript of MachXO2 Dual Sensor Interface Board · 2014-07-25 · 3 MachXO2 Dual Sensor Interface Board Lattice...
January 2012Revision: EB69_01.0
MachXO2 Dual Sensor Interface Board
User’s Guide
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
IntroductionBuilding off Lattice’s broad support for bridging image sensors to parallel buses for ISP (Image Signal Processors), Lattice has designed a new sensor interface board. There are two purposes for the MachXO2™ Dual Sensor Inter-face Board (DSIB). First, the DSIB confirms that sensor bridges can be implemented in the low cost MachXO2 device. Second, the DSIB platform demonstrates two image sensors being merged into one parallel stream for an ISP to process the combined image.
The DSIB is designed to provide users with a platform to support dual sensor designs such as 3D stereoscopic video, black box car driver recorders and other applications that require more than one sensor. The DSIB is used in conjunction with the HDR-60 Base Board and two 9MT024 Aptina 720p NanoVesta boards (see Figure 1). See EB59, HDR-60 Development Kit User’s Guide and EB63, NanoVesta Head Board User’s Guide for further informa-tion on these boards.
Figure 1. MachXO2 Dual Sensor Interface Board with Dual Sensors
HDR-60 Base Board
Optional NanoVesta Sensor #2
NanoVesta Sensor #1
MachXO2 Dual SensorInterface Board (DSIB)
Some common applications and uses for the MachXO2 Dual Sensor Interface Board include:
• 3D stereoscopic video cameras
• Aftermarket automotive black box DVR
• 3D camera for analytics in security/surveillance applications
• Traffic cameras where one sensor records video and the other sensor takes the photo
• Interfacing to the Texas Instruments (TI) IPNC DM812x, DM385 or DM385 camera base boards
• Evaluation of MachXO2 device interfacing to sub-LVDS signals
• Sensor bridges using a MachXO2 device to convert from serial sensors to parallel buses
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Features• MachXO2-4000 PLD for sensor interfacing and driving a parallel ISP bus
• LP SDRAM: 16-bit data over a 32Mb address space
• Built-in USB 2.0 download to MachXO2
• Can be configured for a flywire ispDOWNLOAD® cable connection
• HiSPi and other serial sensor interfaces can be supported
• One MEMS-based oscillator for sensor synchronization
• 36-pin flat ribbon cable connector for TI IPNC camera connections
• 3.3V, 2.5V and 1.8V voltages are possible for various MachXO2 I/O banks
• ispVM™ System programming support
The MachXO2 Dual Sensor Interface Board demonstrates a low cost solution for combining data from two image sensors to a single ISP parallel bus. A MachXO2-4000 device and an external SDRAM memory device are the key components of the solution. The two Aptina sensors are configured to output pixel data via HiSPi serial data lanes. These HiSPi lanes are sent to the MachXO2 device where it converts the serial data of each sensor to two internal buses. Finally, the MachXO2 device combines the two sensors’ data and outputs a single parallel bus. Depending on the desired output format, the external SDRAM device may be used by the MachXO2 device to store image frames and aid in output formatting. The parallel bus is typically driven to an ISP device (see Figure 2). However, when the DSIB is used with the HDR-60 Base Board, the output is sent to the LatticeECP3™ FPGA which simply accepts the parallel bus and drives the HDMI connector so an image can be seen on a LCD monitor.
Figure 2. Dual Sensor HiSPi Bridge
Sensor
HiSPi Serial Bus
Parallel Bus
Hsync, Vsync
CLKSensor
MachXO2
Low PowerSDRAM
Image SignalProcessor (ISP)
General DescriptionThe heart of the MachXO2 Dual Sensor Interface Board is the MachXO2-4000 PLD. The devices and connectors attached to the MachXO2 device provide the means to investigate applications for sensor bridging and dual sensor processing. The board also provides several different interconnects to support many devices for a variety of pur-poses. The HiSPi or other serial sensor input, low power SDRAM memory and connectors for the parallel data are useful in applications that use Lattice sensor-oriented reference designs. Resources such as updates to this docu-ment, sample applications and links to demos can be found by visiting www.latticesemi.com/dualsensorbridge, and navigating to the appropriate page for this board.
Initial Setup and HandlingThe following is recommended reading prior to removing the evaluation board from the static shielding bag and may or may not apply to your particular use of the board.
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
CAUTION: The devices on the board can be damaged by improper handling.
The devices on the MachXO2 Dual Sensor Interface Board contain fairly robust ESD (Electro Static Discharge) protection structures within them, able to withstand typical static discharges (see the “Human Body Model” specifi-cation for an example of ESD characterization requirements). Even so, the devices are static sensitive to conditions that exceed their designed-in protection. For example: higher static voltages, as well as lower voltages with lower series resistance or larger capacitance than the respective ESD specifications can potentially damage or degrade the devices on the evaluation board.
It is recommended that you wear an approved and functioning grounded wrist strap at all times while handling the evaluation board when it is removed from the static shielding bag. If you will not be using the board for an extended period of time, it is best to store it in the static shielding bag. Please save the static shielding bag and packing box for future storage of the board when it is not in use.
Before connecting the DSIB to the HDR-60 Base Board, attach a cable from chassis ground on grounded test equipment to GND on the board. Connecting the board ground to test equipment chassis ground will decrease the risk of ESD damage to the I/O on the board as the initial connections to the board are made. Likewise, when unplugging cables from the evaluation board, the last connection unplugged, should be the chassis GND connec-tion to the evaluation board GND. If you have a signal source that is floating with respect to chassis GND, attempt to neutralize any static charge on that signal source prior to attaching it to the evaluation board.
If you are holding or carrying the board when it is not in a static shielding bag, keep your finger on the corners of the board. This will keep the board at the same voltage potential as your body until you can put the board back in the static shielding bag.
Electrical, Mechanical, and Environmental SpecificationsThe nominal board dimensions are 113 mm x 65 mm (4.4375” x 2.5625”). The environmental specifications are as follows:
• Operating temperature: 0°C to 55°C
• Storage temperature: -40°C to 75°C
• Humidity: <95% without condensation
• 5V DC power
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Functional DescriptionFigure 3. MachXO2 Dual Sensor Interface Board, Top Side
MachXO2 PLDISSI SDRAM
NanoVesta Sensor #1Connectors
TI IPNCConnector
FTDIUSBLEDs
NanoVesta Sensor #2Connectors
Configuration OptionsThere are several possible configurations that the MachXO2 Dual Sensor Interface Board can support. The options are described below.
Default ConfigurationThe DSIB is shipped in a state that allows support for only one image sensor, located in sensor #1 as marked on the board. The only jumper on the DSIB is J20 which shorts pins 1 and 2. This ensures that 1.8V is sourced to the SDRAM device. The default programming file in the MachXO2 device supports bridging an Aptina 9MT024 NanoVesta board plugged into location #1. It is also possible to plug a Panasonic MN34041 NanoVesta board or an Aptina AR0331 NanoVesta board into sensor location #1. However, for either of these sensors, the MachXO2 device will need to be reprogrammed.
The configuration options described below require the user to make some modifications and changes to the MachXO2 Dual Sensor Interface Board. Use caution when making any of these changes.
Dual Image Sensor HiSPi ConfigurationThe MachXO2 Dual Sensor Interface Board supports two image sensors that can be merged to form one image. The two sensors are the 9MT024 NanoVesta boards. To support the dual sensor HiSPi format, the following modi-fications need to be made. In locations J2 and J10, zero ohm resistors tie pins 2 and 3 together. Both resistors should be removed. Once this is complete, on both J2 and J10, pins 1 and 2 should be shorted and pins 3 and 4 should be shorted. Inserting zero ohm resistors is the recommended method to do this. Once these changes are made and two 9MT024 NanoVesta boards are inserted, then the MachXO2 needs to be reprogrammed. See the Configuring/Programming the DSIB section of this document for further details.
On both 9MT024 NanoVesta boards, it is important to ensure that jumper J2 has a jumper to short pins 2 and 3. This J2 jumper ensures that the same clock is driven to both sensors. No other jumpers should be on the 9MT024 NanoVesta board.
Lastly, note that when the dual image sensor HiSPi configuration is made to the DSIB, no Panasonic MN34041 sensor can be supported. Neither sensor location can accept a Panasonic MN34041 NanoVesta board. To support
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
a Panasonic MN34041 NanoVesta board, revert the board to the default configuration on the DSIB and plug the Panasonic board into sensor location #1.
I2C Sensor Bypass ConfigurationJumpers J14, J15 and J16 can be used for the LatticeECP3 device on the HDR-60 Base Board to configure the sensor in location #1. No demo code is available to support this programming, but inserting these jumpers allows the option to bypass the MachXO2 device for I2C programming of sensor location #1 only. The bypass does not support sensor #2. The default configuration does not have these jumpers set.
MachXO2 I2C Embedded Function Block ConfigurationThe last possible configuration is one that allows a user to access the hard I2C logic resident in the MachXO2 device. This built-in I2C function is in the Embedded Function Block of the MachXO2 device. The default configura-tion on the DSIB has J21 pins 1 and 2 shorted with a zero ohm resistor. For I2C Embedded Function Block support, the resistor between pins 1 and 2 on J21 must be removed. Then pins 2 and 3 must be shorted on J21 with a zero ohm resistor. Note that when the board is modified for I2C support, sensor location #2 is not supported.
MachXO2 DeviceThis board features a MachXO2-4000 FPGA with a 1.2V DC core in a 132-ball csBGA package. The MachXO2-1200, -2000 and -4000 device densities in this package can be accommodated with no change in pin connections, although some features are not supported in the smaller density devices. A complete description of this device can be found in the MachXO2 Family Data Sheet.
Power Connections The board is supplied 5V power from the HDR-60 Base Board connectors, J7 and J8. To power the DISB, a 5V supply can be applied to TP70 (+5V) and TP90 (GND). On-board step-down switching regulators then provide the necessary supply voltages: 3.3V, 2.5V, 1.8V and 1.2V.
The on-board switching regulator output voltages can be measured at test points located around the board as shown in Table 1.
Table 1. Test Points for On-Board Regulator Voltages
SupplySwitching Regulator Test Point Feedback Resistors Comment
3.3V U10 (side 2) TP67 R46, R45
2.5V U10 (side 1) TP68 R53, R5, R56, R511.8V: jumper on J6 pins 1-22.5V: no jumper on J4 (default)3.3V: jumper on J6 pins 2-3
1.8V U11 (side 2) TP66 R57, R58, R59, R61.8V: jumper on J20 pins 1-2 (default) 2.5V: no jumper on J20 3.3V: jumper on J20 pins 2-3
1.2V U11 (side 1) TP69 R54, R52
Each of the step-down switching regulators, U10 and U11, incorporate typical resistor divider voltage feedback to divide-down the regulator output voltage and compare it against an internal reference voltage. The regulator then adjusts the output voltage higher or lower such that the resistor divided voltage matches the internal reference. By doing this, the regulator output voltage remains at a constant voltage value independent of the load driven. The regulator output voltages are set by the ratio of the feedback resistor values shown in Table 1, multiplied by the reg-ulator internal reference voltage. See the LT3508 device data sheets for additional details about these devices.
The 2.5V regulator output voltage can also be set to 1.8V or 3.3V by adding a shorting jumper on J6, as shown in Table 1. With no jumper on J6, the voltage divider is set by R53 and R5 and this divider sets up a nominal 2.5V out-put voltage. When a shorting jumper is added to J6, the R56 and R51 resistors will be placed in parallel with either R53 or R5, which then changes the resistor divider ratio, and this changes side 1 of the U10 regulator output volt-
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
age to become 1.8V or 3.3V, depending on the placement of the shorting jumper on J6. A similar configuration is supported for U11 side 2.
MachXO2 I/O Bank VoltagesMost of the bank voltages on the MachXO2 device (U8) have been hard-wired to selectable power supply values. Banks 0, 2 and 5 are normally 2.5V, but they can be modified by the location of J6. These banks interface to the parallel ISP bus and the sensor configuration pins. Banks 1, 3 and 4 are normally 1.8V, but they can be modified by the location of J20. These I/Os interface to the low power SDRAM memory, as shown in Table 2.
Table 2. MachXO2 (U8) Bank Voltage Settings
MachXO2 Bank VCCIO Voltage Comment
0, 2 and 5 2.5V Normally Parallel ISP bus, sensor configuration I/O, JTAG interface
1, 3 and 4 1.8V Normally Interface for the low power SDRAM
Crystal OscillatorsThere is one crystal oscillator and one MEMS-based oscillator on the MachXO2 Dual Sensor Interface Board (Table 3). The crystal oscillator is used for the USB port connection. The MEMS-based oscillator is 27 MHz and is delivered to the MachXO2 device as a design reference clock to provide a clock to the sensors, if desired.
Table 3. Crystal Oscillators Used on the HDR-60 Base Board
DeviceBoard
Location Frequency CommentMachXO2 Input
I/O Setting
MEMS-Based Oscillator Y1 27 MHz Used for sensor clock and to drive PLL in MachXO2 for low power SDRAM Normally 2.5V
Crystal Oscillator Y2 6 MHz USB FTD2232D U5 pin 43 —
Image Sensor ConnectorsThe board has six Hirose connectors, configured as three pairs. These are located at J1 and J5, J4 and J11, and J7 and J8. The J1 and J5 pair are for sensor #1. The J4 and J11 pair are for sensor #2. The J7 and J8 pair allow the DSIB to plug into the HDR-60 Base Board.
HiSPi Connector for Sensor #1 (J1)Bank 2 of the MachXO2 device can receive HiSPi sub-LVDS video signals from connector J1. This connector can also receive serial signals from the Panasonic MN34041. When receiving serial signals, set the MachXO2 input type to LVDS with differential 100 ohm termination. The signal connections between the MachXO2 device and the HiSPi connector are shown in Table 4.
Table 4. MachXO2 (U8) Interface to HiSPi Connector (J1)
J1 PinMachXO2 I/O
BGA Ball PolaritysysIO™
Bank Differential Signal Comment
13 M11 P 2 SLVS_0P —
11 P12 N 2 SLVS_0N —
29 P8 P 2 SLVS_1P —
27 M8 N 2 SLVS_1N —
21 P2 P 2 SLVS_2P —
19 N2 N 2 SLVS_2N —
26 M7 / P7 P 2 SLVS_3P Default for single sensor/dual sensor configuration
24 N8 / N7 N 2 SLVS_3N Default for single sensor/dual sensor configuration
17 N3 P 2 PAN_B1P Used for MN34041
15 P4 N 2 PAN_B1N Used for MN34041
22 M9 P 2 PAN_B0P Used for MN34041
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Parallel Connector for Sensor #1 (J5)The MachXO2 (U8) Bank 5 receives sensor control signals for sensor #1 from the parallel connector J5. The signal connections between the MachXO2 device and the J5 connector are shown in Table 5.
Table 5. MachXO2 (U8) Interface to Parallel Connector J5
J5 PinMachXO2 I/O
BGA Ball sysIO Bank Parallel Signal Differential Signal
9 C2 5 EXTCLK_FPGA —
25 N4 2 TRIGGER —
27 F2 5 RESET_BAR —
29 C3 5 OUTPUT_EN_BAR —
31 D1 5 STANDBY —
26 B1 5 SADDR —
28 M4 2 SCLK —
30 P13 2 SDATA —
HiSPi Connector for Sensor #2 (J4)The MachXO2 Bank 2 can also receive HiSPi sub-LVDS video signals from connector J4. It is possible to receive other serial sensors from this sensor 2 location, but dual Panasonic MN34041 sensors are not supported. MN34041 only works in sensor location #1. When receiving serial signals, set the MachXO2 input type to LVDS with differential 100 ohm termination. The signal connections between the MachXO2 device and the HiSPi connec-tor are shown in Table 6.
Table 6. MachXO2 (U8) Interface to HiSPi Connector J4
J4 PinMachXO2 I/O
BGA Ball Polarity sysIO BankDifferential
Signal Comment
13 P3 P 2 SLVS_0P —
11 M3 N 2 SLVS_0N —
29 M10 P 2 SLVS_1P —
27 P11 N 2 SLVS_1N —
21 N5 P 2 SLVS_2P —
19 M5 N 2 SLVS_2N —
26 P9 P 2 SLVS_3P —
24 N9 N 2 SLVS_3N —
18 M7 P 2 SLVS_CP Configuration for dual sensor
16 N8 N 2 SLVS_CN Configuration for dual sensor
Parallel Connector for Sensor #2 (J11)The MachXO2 (U8) receives sensor control signals for sensor #2 from the parallel connector J11. The signal con-nections between the MachXO2 device and the J11 connector are shown in Table 7. Note that some of the control signals are connected to sensor #1 J5 also.
20 N10 N 2 PAN_B0N Used for MN34041
18 N6 P 2 SLVS_CP —
16 P6 N 2 SLVS_CN —
Table 4. MachXO2 (U8) Interface to HiSPi Connector (J1) (Continued)
J1 PinMachXO2 I/O
BGA Ball PolaritysysIO™
Bank Differential Signal Comment
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Table 7. MachXO2 (U8) Interface to Parallel Connector J11
J11 PinMachXO2 I/O
BGA Ball sysIO Bank Parallel Signal Differential Signal
9 C2 5 EXTCLK_FPGA —
25 N4 2 TRIGGER —
27 F2 5 RESET_BAR —
29 C3 5 OUTPUT_EN_BAR —
31 D1 5 STANDBY —
26 E1 5 SADDR —
28 E2 5 SCLK —
30 E3 5 SDATA —
Parallel Connector to ISP Parallel Bus (J7)The MachXO2 (U8) bank 0 sends parallel CMOS signals to the ISP. The parallel bus of the ISP drives both this connector J7 and the TI connector J9. The signal connections between the MachXO2 device and the J7 connec-tor are shown in Table 8. Connections to the TI ISP connector J9 have the same MachXO2 pins as in Table 8. It is assumed that either the HDR-60 Base Board or the TI ISP connector J9 will receive the ISP parallel bus signal J7.
Table 8. MachXO2 (U8) Interface to Parallel ISP Connector J7
J7 PinMachXO2 I/O
BGA Ball sysIO Bank Parallel Signal Differential Signal
10 A11 0 PIXCLK
11 C4 0 LINE VALID
12 B7 0 FRAME VALID
13 A9 0 D6
14 A7 0 D4
15 C11 0 D2
16 C6 0 D0
17 A10 0 D7
18 B5 0 D5
19 A12 0 D3
20 B3 0 D1
21 C12 0 D10
22 A2 0 D8
23 B13 0 D11
24 B12 0 D9
26 A3 0 SADDR Only for LatticeECP3 communication
27 B9 0 D12 Only for LatticeECP3 communication
28 C9 0 SCLK Only for LatticeECP3 communication
29 A13 0 D13 Optional
30 C10 0 SDATA Only for LatticeECP3 communication
Downloading Bitstreams into the MachXO2 (U8)In order to download bitstreams into the MachXO2 device, a USB-A to USB-A cable can connect a PC (with Lattice Diamond® design software installed) to the MachXO2 Dual Sensor Interface Board. Each USB-A to USB-A cable is
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
6 feet (1.83 meters) in length. Connector J13 is the USB port. A FTD2232D USB transceiver (U5) translates the USB signals to JTAG signals and is able to drive the MachXO2 device. Given this, the ispVM System software can download bitstreams directly into the MachXO2 SRAM, or bitstreams can be downloaded into the MachXO2 Flash memory.
LEDs There are two LEDs on the MachXO2 Dual Sensor Interface Board that are used for general purpose signals, as described in Table 9.
Table 9. LEDs
LED MachXO2 Pin Color Function
LED1 J14 Green Indicate Line Valid and Frame Valid activityLED2 J12 Red
Low Power SDRAM MemoryThe MachXO2 Dual Sensor Interface Board is equipped with a 54-ball BGA low power SDRAM device, such as the IS42VM16400K in location U1. This provides memory resources with 16 bits of data width that span a 32M address space. The memory is powered by an on-board 1.8V regulator. The memory connects to the MachXO2 device on Banks 1, 3 and 4.
Table 10. MachXO2 Interface to Low Power SDRAM
Signal Name MachXO2 Pin (U8) sysIO Bank SDRAM Pin (U1)
SDRAM_DQ0 C14 1 A8
SDRAM_DQ1 D12 1 B9
SDRAM_DQ2 E12 1 B8
SDRAM_DQ3 E14 1 C9
SDRAM_DQ4 E13 1 C8
SDRAM_DQ5 F12 1 D9
SDRAM_DQ6 F13 1 D8
SDRAM_DQ7 F14 1 E9
SDRAM_DQ8 J13 1 E1
SDRAM_DQ9 K12 1 D2
SDRAM_DQ10 K13 1 D1
SDRAM_DQ11 K14 1 C2
SDRAM_DQ12 L14 1 C1
SDRAM_DQ13 M13 1 B2
SDRAM_DQ14 M12 1 B1
SDRAM_DQ15 M14 1 A2
SDRAM_BA0 B14 1 G7
SDRAM_BA1 C13 1 G8
SDRAM_CAS_N G12 1 F7
SDRAM_RAS_N G14 1 F8
SDRAM_WE_N N13 1 F9
SDRAM_CS_N N14 1 G12
SDRAM_LDQM G13 1 E8
SDRAM_UDQM H12 1 F1
SDRAM_A0 J3 3 H7
SDRAM_A1 K2 3 H8
SDRAM_A2 K1 3 J8
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Configuring/Programming the DSIBRequirements
• PC with Lattice Diamond design software version 1.3 (or later) installed with a USB driver. Note: An option to install this driver is included as part of the Diamond setup.
For a complete discussion of the MachXO2 configuration and programming options, refer to TN1204, MachXO2 Programming and Configuration Usage Guide.
Download ProceduresThe download instructions below describe how to download JEDEC files into the MachXO2 Flash memory using the Diamond Programmer software. Bitstream downloads are done via a USB cable from a PC to the DSIB.
Note that the first download procedure shows the menus as viewed on a Windows XP operating system. The download procedures are very similar and do not show the menus.
The MachXO2 can be configured easily using the Diamond Programmer software to download a bitstream via a standard USB-A to USB-A cable.
1. Plug the MachXO2 Dual Sensor Interface Board into the HDR60 Base Board and power it up.
2. Connect the USB-A to USB-A cable from your PC’s USB connector to the USB port on J13 of the DSIB.
3. Start the Diamond Programmer software. Create a new Project from a scan as shown in Figure 4. Alternatively, if Diamond Programmer is open, click the Scan button .
SDRAM_A3 K3 3 J7
SDRAM_A4 L3 3 J3
SDRAM_A5 M1 3 J2
SDRAM_A6 M2 3 H3
SDRAM_A7 F1 4 H2
SDRAM_A8 F3 4 H1
SDRAM_A9 H2 4 G3
SDRAM_A10 H1 4 H9
SDRAM_A11 H3 4 G2
SDRAM_CLK J1 4 F2
SDRAM_CKE J2 4 F3
SDRAM_NC_G1 G3 4 G11
1. SDRAM pin G1 is connected in case a larger memory size is desired in the future.
Table 10. MachXO2 Interface to Low Power SDRAM (Continued)
Signal Name MachXO2 Pin (U8) sysIO Bank SDRAM Pin (U1)
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 4. Diamond Programmer Project Options
4. Under Device, select LCMXO2-4000HE from the pull-down menu (Figure 5).
Figure 5. Diamond Programmer New Scan Configuration Setup
5. Next, double-click under the filename tab. Browse to the JEDEC programing file (*.jed) and click OK.
Figure 6. Select JEDEC File for Programming
6. Click the Program button and wait for programming to complete.
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 7. Bitstream Download Operation Successful
Ordering Information
Description Ordering Part NumberChina RoHS Environment-Friendly
Use Period (EFUP)
MachXO2 Dual Sensor Interface Board LCMXO2-4000HE-DSIB-EVN
Technical Support AssistanceHotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)e-mail: [email protected]: www.latticesemi.com
Revision HistoryDate Version Change Summary
January 2012 01.0 Initial release.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Appendix A. SchematicsFigure 8. Block Diagram
55
44
33
22
11
DD
CC
BB
AA
27MHz CLK
OSCILLATOR
Bank5
Top Sensor-1
Parallel Connector
Bank1
Voltage
Regulators
LATTIC
E XO
2132 ball
Bank0
Bank2
XO2 B
LOC
K D
IAG
RA
M
Top Sensor-2
Parallel Connector
High Speed Connector
Top Sensor-1 High Speed Connector
Top Sensor-2
Bottom ECP3 High SPIConnector
Bottom ECP3 ParallelConnector
FTDI
CHIP
PROG UPPER USB /
6 MHz Crystal /
EEPROM (1Kb - 2MHZ)
JTAG
HEADER (JTAG)
Bank3
Bank4
ISSI
SDR
(Sheet 5)
(Sheet 3)
(Sheet 4)
(Sheet 6)
(Sheet 6)
(Sheet 6)
(Sheet 9)
(Sheet 6)
(Sheet 8)
(Sheet 10)
(Sheet 9)
(Sheet 9)
(Sheet 9)
(Sheet 5) (Sheet 5)
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)4 teehS(
(Sheet 3) (Sheet 3)
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MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 9. Top Connections – 1
55
44
33
22
11
DD
CC
BB
AA
TOP
- HIG
H S
PI to S
ENS
OR
1C
ON
NEC
TOR
1
TOP
- HIG
H S
PI to S
ENS
OR
2C
ON
NEC
TOR
2
BA
NK
2
TOP C
ON
N C
ON
NEC
TION
S-1
Default -2 &
3 shorted for 1 HiS
Pi or 1 Panasonic
Short 1 &
2 and 3 & 4 for 2 H
iSPi sensors
Note for J2
, J10
:
Note for J2
1
Default -1 &
2 SH
ORT W
ITH 0/0603 R
esistor
SLV
S_0N
_1S
LVS
_0P_1
SLV
S_2N
_1S
LVS
_2P_1
SLV
S_1N
_1S
LVS
_1P_1
HIS
PI_LE
D_1
SLV
S_3N
_1S
LVS
_3P_1
SLV
S_0N
_2S
LVS
_0P_2
SLV
S_2N
_2S
LVS
_2P_2
SLV
S_1N
_2S
LVS
_1P_2
HIS
PI_LE
D_2
SLV
S_3N
_2S
LVS
_3P_2
PA
NA
SO
NIC
_B1N
PA
NA
SO
NIC
_B1P
PA
NA
SO
NIC
_B0N
PA
NA
SO
NIC
_B0P
SLV
S_C
P_1
SLV
S_C
N_1
SLV
S_C
P_2
SLV
S_C
N_2
HIS
PI_LE
D_1
SLV
S_C
P_1
SLV
S_C
N_1
SLV
S_3P
_M7
SLV
S_3N
_N8
SLV
S_3P
_P7
SLV
S_3N
_N7
SLV
S_0N
_1S
LVS
_0P_1
SLV
S_1P
_1S
LVS
_1N_1
SLV
S_2N
_1S
LVS
_2P_1
PA
NA
SO
NIC
_B1N
PA
NA
SO
NIC
_B1P
PA
NA
SO
NIC
_B0N
PA
NA
SO
NIC
_B0P
SLV
S_3P
_P7
SLV
S_3P
_1
SLV
S_3P
_M7
SLV
S_3N
_N8
SLV
S_C
P_2
SLV
S_C
N_2
SLV
S_3N
_N7
SLV
S_3N
_1
SLV
S_3N
_2S
LVS
_3P_2
SLV
S_0N
_2
SLV
S_1N
_2S
LVS
_1P_2
SLV
S_2N
_2S
LVS
_2P_2
SIG
NA
L_TRIG
GE
RS
CLK
_1
SD
ATA
_1
SLV
S_0P
_2
SA
DD
R_1
V5P
0GN
DG
ND
V5P
0
V5P
0GN
DG
ND
V5P
0
V2P
5
V2P
5
GN
D
SIG
NA
L_TRIG
GE
R{4}
SC
LK_1
{4}
SD
ATA
_1{4}
SLV
S_0P
_2{3}
SA
DD
R_1
{4}
HIS
PI_LE
D_2
{4}S
LVS
_0P_2
{3}
Title
veR
reb
muN t
nemu
coD
ezi
S
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S:e
taD
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oD< XO
2 IN
TERFA
CE B
OA
RD
B
310
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
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S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
310
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
310
Tuesday, Septem
ber 13, 2011
J10
4PIN
_SM
D_0603
Install 0/0603 Resitor
J10
4PIN
_SM
D_0603
Install 0/0603 Resitor
1
2
3
4
C2
100NF-0201SMT
C2
100NF-0201SMT
C220100NF-0201SMT
C220100NF-0201SMT
C1
100NF-0201SMT
C1
100NF-0201SMT
BA
NK
2M
AC
HX
02
-40
00
U8C
MachX
O2-4000
BA
NK
2M
AC
HX
02
-40
00
U8C
MachX
O2-4000
CS
SP
IN_P
B4A
_TP
3
MC
LK_C
CLK
_PB
9A_T
M4
PB
10A_T
N5
PB
10B_C
M5
PB
13A_P
CLK
T2_0_TN
6
PB
13B_P
CLK
C2_0_C
P6
PB
15A_T
P7
PB
15B_C
N7
PB
20A_P
CLK
T2_1_TM
7
PB
20B_P
CLK
C2_1_C
N8
PB
21A_T
P8
PB
21B_C
M8
PB
23A_T
P9
PB
23B_C
N9
PB
24A_T
M9
PB
24B_C
N10
PB
27A_T
M10
PB
27B_C
P11
PB
29A_T
M11
PB
29B_C
P12
PB
3A_T
P2
PB
3B_C
N2
PB
4B_C
M3
PB
7A_T
N3
PB
7B_C
P4
SI_S
ISP
I_PB
30B_C
P13
SN
_PB
30A_T
N12
SO
_SP
ISO
_PB
9B_C
N4
VC
CIO
2_1M
6
VC
CIO
2_2N
11
VC
CIO
2_3P
1
HRS-DF12A-(3.0)-40D*-0.5V**
J4
DF12__-40D
S-0.5V
_RE
CE
PTA
CLE
PA
RT_N
UM
BE
R = D
F12(4.0)-40DS
-0.5VM
anufacturer = HIR
OS
E
HRS-DF12A-(3.0)-40D*-0.5V**
J4
DF12__-40D
S-0.5V
_RE
CE
PTA
CLE
PA
RT_N
UM
BE
R = D
F12(4.0)-40DS
-0.5VM
anufacturer = HIR
OS
E
PIN
11
PIN
22
PIN
33
PIN
44
PIN
55
PIN
66
PIN
77
PIN
88
PIN
99
PIN
1010
PIN
1111
PIN
1212
PIN
1313
PIN
1414
PIN
1515
PIN
1616
PIN
1717
PIN
1818
PIN
1919
PIN
2020
PIN
2121
PIN
2222
PIN
2323
PIN
2424
PIN
2525
PIN
2626
PIN
2727
PIN
2828
PIN
2929
PIN
3030
PIN
3131
PIN
3232
PIN
3333
PIN
3434
PIN
3535
PIN
3636
PIN
3737
PIN
3838
PIN
3939
PIN
4040
SH
IELD
_1S
HIE
LD1
SH
IELD
_2S
HIE
LD2
HRS-DF12A-(3.0)-40D*-0.5V**
J1
DF12__-40D
S-0.5V
_RE
CE
PTA
CLE
PA
RT_N
UM
BE
R = D
F12(4.0)-40DS
-0.5VM
anufacturer = HIR
OS
E
HRS-DF12A-(3.0)-40D*-0.5V**
J1
DF12__-40D
S-0.5V
_RE
CE
PTA
CLE
PA
RT_N
UM
BE
R = D
F12(4.0)-40DS
-0.5VM
anufacturer = HIR
OS
E
PIN
11
PIN
22
PIN
33
PIN
44
PIN
55
PIN
66
PIN
77
PIN
88
PIN
99
PIN
1010
PIN
1111
PIN
1212
PIN
1313
PIN
1414
PIN
1515
PIN
1616
PIN
1717
PIN
1818
PIN
1919
PIN
2020
PIN
2121
PIN
2222
PIN
2323
PIN
2424
PIN
2525
PIN
2626
PIN
2727
PIN
2828
PIN
2929
PIN
3030
PIN
3131
PIN
3232
PIN
3333
PIN
3434
PIN
3535
PIN
3636
PIN
3737
PIN
3838
PIN
3939
PIN
4040
SH
IELD
_1S
HIE
LD1
SH
IELD
_2S
HIE
LD2
J21
3PIN
_SM
D_0603
J21
3PIN
_SM
D_0603
1
2
3
J24PIN
_SM
D_0603
Install 0/0603 Resitor
J24PIN
_SM
D_0603
Install 0/0603 Resitor
1
2
3
4
16
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 10. Top Connections – 2
55
44
33
22
11
DD
CC
BB
AA
TOP
- PA
RA
LLEL UP
to SEN
SO
R1
TOP
- PA
RA
LLEL UP
to SEN
SO
R2
BA
NK
5
TOP C
ON
N C
ON
NEC
TION
S-2C
ON
NEC
TOR
1
CO
NN
ECTO
R 2
BY
PA
SS
OP
TION
-2 P
IN JP
R
SA
DD
R_1
RE
SE
T_BA
RS
CLK
_1O
UTP
UT_E
N_B
AR
SD
ATA
_1
EX
TCLK
_FPG
A
STA
ND
BY
SA
DD
R_2
RE
SE
T_BA
RS
CLK
_2O
UTP
UT_E
N_B
AR
SD
ATA
_2
EX
TCLK
_FPG
A
STA
ND
BY
RE
SE
T_BA
R
OU
TPU
T_EN
_BA
R
EX
TCLK
_FPG
AS
TAN
DB
Y
SA
DD
R_1
SA
DD
R_2
SC
LK_2
SD
ATA
_2SA
DD
R_1
EC
P3_P
RL_S
AD
DR
EC
P3_P
RL_S
CLK
SD
ATA
_1E
CP
3_PR
L_SD
ATA
SC
LK_1
SIG
NA
L_TRIG
GE
R
SIG
NA
L_TRIG
GE
R
HIS
PI_LE
D_2
RE
SE
T_PB
GN
D
V5P
0
GN
D
V5P
0
GN
D
V5P
0
GN
D
V5P
0
V2P
5
GN
D
V2P
5
SA
DD
R_2
{7}S
CLK
_2{7}
SD
ATA
_2{7}
RE
SE
T_BA
R{7}
EC
P3_P
RL_S
CLK
{5,7}
EC
P3_P
RL_S
DA
TA{5,7}
EC
P3_P
RL_S
AD
DR
{5}
SIG
NA
L_TRIG
GE
R{3}
HIS
PI_LE
D_2
{3}
RE
SE
T_PB
{8}
SA
DD
R_1
{3}S
CLK
_1{3}
SD
ATA
_1{3}
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
410
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
410
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
410
Tuesday, Septem
ber 13, 2011
J15
2 PIN
JPR
J15
2 PIN
JPR
12
J16
2 PIN
JPR
J16
2 PIN
JPR
12
MA
CH
X0
2-4
00
0B
AN
K 5
U8F
MachX
O2-4000
MA
CH
X0
2-4
00
0B
AN
K 5
U8F
MachX
O2-4000
PL3A
_L_GP
LLT_FB_T
B1
PL3B
_L_GP
LLC_FB
_CB
2
PL4A
_L_GP
LLT_IN_T
C1
PL4B
_L_GP
LLC_IN
_CC
3
PL6A
_PC
LKT5_0_T
C2
PL6B
_PC
LKC
5_0_CD
1
PL7A
_TE
1
PL7B
_CE
2
PL8A
_TE
3
PL8B
_CF2
VC
CIO
5D
3
HRS-DF12A(3.0)-40D*-0.5V**
J11
DF12(4.0)-40D
P-0.5V
_HE
AD
ER
PA
RT_N
UM
BE
R = D
F12(4.0)-40DP
-0.5VM
anufacturer = HIR
OS
E
HRS-DF12A(3.0)-40D*-0.5V**
J11
DF12(4.0)-40D
P-0.5V
_HE
AD
ER
PA
RT_N
UM
BE
R = D
F12(4.0)-40DP
-0.5VM
anufacturer = HIR
OS
E
PIN
11
PIN
22
PIN
33
PIN
44
PIN
55
PIN
66
PIN
77
PIN
88
PIN
99
PIN
1010
PIN
1111
PIN
1212
PIN
1313
PIN
1414
PIN
1515
PIN
1616
PIN
1717
PIN
1818
PIN
1919
PIN
2020
PIN
2121
PIN
2222
PIN
2323
PIN
2424
PIN
2525
PIN
2626
PIN
2727
PIN
2828
PIN
2929
PIN
3030
PIN
3131
PIN
3232
PIN
3333
PIN
3434
PIN
3535
PIN
3636
PIN
3737
PIN
3838
PIN
3939
PIN
4040
SH
IELD
_1S
HIE
LD1
SH
IELD
_2S
HIE
LD2
C221100NF-0201SMT
C221100NF-0201SMT
J14
2 PIN
JPR
J14
2 PIN
JPR
12
HRS-DF12A(3.0)-40D*-0.5V**
J5
DF12(4.0)-40D
P-0.5V
_HE
AD
ER
PA
RT_N
UM
BE
R = D
F12(4.0)-40DP
-0.5VM
anufacturer = HIR
OS
E
HRS-DF12A(3.0)-40D*-0.5V**
J5
DF12(4.0)-40D
P-0.5V
_HE
AD
ER
PA
RT_N
UM
BE
R = D
F12(4.0)-40DP
-0.5VM
anufacturer = HIR
OS
E
PIN
11
PIN
22
PIN
33
PIN
44
PIN
55
PIN
66
PIN
77
PIN
88
PIN
99
PIN
1010
PIN
1111
PIN
1212
PIN
1313
PIN
1414
PIN
1515
PIN
1616
PIN
1717
PIN
1818
PIN
1919
PIN
2020
PIN
2121
PIN
2222
PIN
2323
PIN
2424
PIN
2525
PIN
2626
PIN
2727
PIN
2828
PIN
2929
PIN
3030
PIN
3131
PIN
3232
PIN
3333
PIN
3434
PIN
3535
PIN
3636
PIN
3737
PIN
3838
PIN
3939
PIN
4040
SH
IELD
_1S
HIE
LD1
SH
IELD
_2S
HIE
LD2
17
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 11. Bottom Connections
55
44
33
22
11
DD
CC
BB
AA
Fitting & Boss have no electrical function, can be used as vias
BO
TTOM
- HIG
H S
PI to EC
P3
BO
TTOM
- PA
RA
LLEL to ECP
3
Fitting & Boss have no electrical function, can be used as vias
BA
NK
0
BO
TTOM
CO
NN
CO
NN
ECTIO
N
EC
P3_H
ISP
I_LED
EC
P3_LIN
E_V
ALID
ECP3_D
OU
T6
EC
P3_P
IXC
LK
ECP3_D
OU
T2EC
P3_DO
UT7
ECP3_D
OU
T8EC
P3_DO
UT1
ECP3_D
OU
T9
EC
P3_P
RL_S
DA
TA
ECP3_D
OU
T0EC
P3_DO
UT5
EC
P3_P
RL_S
AD
DR
EC
P3_P
RL_S
CLK
ECP3_D
OU
T10EC
P3_DO
UT3
ECP3_FR
AM
E_VALID
ECP3_D
OU
T4
ECP3_D
OU
T11
EC
P3_H
ISP
I_LED
EC
P3_P
RL_S
AD
DR
EC
P3_P
RL_S
DA
TA
EC
P3_P
RL_S
CLK
ECP3_D
OU
T4
EC
P3_LIN
E_V
ALID
ECP3_D
OU
T6
ECP3_D
OU
T7
ECP3_D
OU
T11
ECP3_D
OU
T1
CLK
_27MH
z
EC
P3_D
OU
T12_OP
TION
EC
P3_D
OU
T13_OP
TION
EC
P3_D
OU
T12_OP
TION
EC
P3_D
OU
T13_OP
TION
EC
P3_P
IXC
LK
ECP3_D
OU
T0
ECP3_D
OU
T3
ECP3_FR
AM
E_VALID
ECP3_D
OU
T5
ECP3_D
OU
T8
ECP3_D
OU
T10
ECP3_D
OU
T9
ECP3_D
OU
T2
GN
D
V5P
0V
5P0G
ND
V1P
8
GN
D
V5P
0V
5P0G
ND
V1P
8
GN
D
V2P
5
V2P
5
EC
P3_S
LVS
_0N{7}
EC
P3_S
LVS
_0P{7}
EC
P3_S
LVS
_7N{7}
EC
P3_S
LVS
_7P{7}
EC
P3_P
IXC
LK{7}
EC
P3_S
LVS
_5N{7}
EC
P3_S
LVS
_5P{7}
EC
P3_S
LVS
_3N{7}
EC
P3_S
LVS
_2N{7}
EC
P3_S
LVS
_2P{7}
EC
P3_S
LVS
_4N{7}
EC
P3_S
LVS
_4P{7}
EC
P3_S
LVS
_8N{7}
EC
P3_S
LVS
_9N{7}
EC
P3_S
LVS
_9P{7}
CLK
_27MH
z{8}
EC
P3_P
RL_S
AD
DR
{4}E
CP
3_PR
L_SC
LK{4,7}
EC
P3_P
RL_S
DA
TA{4,7}
EC
P3_D
OU
T12_OP
TION
{7}
EC
P3_D
OU
T13_OP
TION
{7}
Title
veR
reb
muN t
nemu
coD
ezi
S
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S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
510
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
510
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
510
Tuesday, Septem
ber 13, 2011
R84
33R
8433
R79
33R
7933
R80
33R
8033
R85
33R
8533
C224100NF-0201SMT
C224100NF-0201SMT
R81
33R
8133
Hirose DF12 Series
J8DF12(4.0)-40D
P-0.5V
_HE
AD
ER
PA
RT_N
UM
BE
R = D
F12(4.0)-40DP
-0.5VM
anufacturer = HIR
OS
E
Hirose DF12 Series
J8DF12(4.0)-40D
P-0.5V
_HE
AD
ER
PA
RT_N
UM
BE
R = D
F12(4.0)-40DP
-0.5VM
anufacturer = HIR
OS
E
PIN
11
PIN
22
PIN
33
PIN
44
PIN
55
PIN
66
PIN
77
PIN
88
PIN
99
PIN
1010
PIN
1111
PIN
1212
PIN
1313
PIN
1414
PIN
1515
PIN
1616
PIN
1717
PIN
1818
PIN
1919
PIN
2020
PIN
2121
PIN
2222
PIN
2323
PIN
2424
PIN
2525
PIN
2626
PIN
2727
PIN
2828
PIN
2929
PIN
3030
PIN
3131
PIN
3232
PIN
3333
PIN
3434
PIN
3535
PIN
3636
PIN
3737
PIN
3838
PIN
3939
PIN
4040
FITTING
1FITTIN
G1
FITTING
2FITTIN
G2
BO
SS
1B
OS
S1
BO
SS
2B
OS
S2
C222100NF-0201SMT
C222100NF-0201SMT
R82
33R
8233
R88
33R
8833
R71
33R
7133
C6
100NF-0201SMT
C6
100NF-0201SMT
R89
33R
8933
R73
33R
7333
R72
33R
7233
R11
10_0K1%
R11
10_0K1%
R83
33R
8333
Hirose DF12 Series
J7DF12_40D
S-0.5V
_RE
CE
PTA
CLE
PA
RT_N
UM
BE
R = D
F12(4.0)-40DS
-0.5VM
anufacturer = HIR
OS
E
Hirose DF12 Series
J7DF12_40D
S-0.5V
_RE
CE
PTA
CLE
PA
RT_N
UM
BE
R = D
F12(4.0)-40DS
-0.5VM
anufacturer = HIR
OS
E
PIN
11
PIN
22
PIN
33
PIN
44
PIN
55
PIN
66
PIN
77
PIN
88
PIN
99
PIN
1010
PIN
1111
PIN
1212
PIN
1313
PIN
1414
PIN
1515
PIN
1616
PIN
1717
PIN
1818
PIN
1919
PIN
2020
PIN
2121
PIN
2222
PIN
2323
PIN
2424
PIN
2525
PIN
2626
PIN
2727
PIN
2828
PIN
2929
PIN
3030
PIN
3131
PIN
3232
PIN
3333
PIN
3434
PIN
3535
PIN
3636
PIN
3737
PIN
3838
PIN
3939
PIN
4040
FITTING
1FITTIN
G1
FITTING
2FITTIN
G2
BO
SS
1B
OS
S1
BO
SS
2B
OS
S2
R74
33R
7433
R12
10_0K1%
R12
10_0K1%
R75
33R
7533
BA
NK
0M
AC
HX
02
-40
00
U8A
MachX
O2-4000 B
AN
K 0
MA
CH
X0
2-4
00
0
U8A
MachX
O2-4000
DO
NE
_PT28D
_CA
13IN
ITN_P
T28C_T
B13
JTAG
EN
B_P
T23C_T
B9
PR
OG
RA
MN
_PT23D
_CC
10
PT11A
_T_LVD
SA
3
PT11B
_C_LV
DS
C4
PT14A
_T_LVD
SB
5
PT14B
_C_LV
DS
C6
PT18A
_PC
LKT0_1_T_LV
DS
A7
PT18B
_PC
LKC
0_1_C_LV
DS
B7
PT21A
_T_LVD
SC
9
PT21B
_C_LV
DS
A9
PT24A
_T_LVD
SA
10
PT24B
_C_LV
DS
C11
PT25A
_T_LVD
SA
11
PT25B
_C_LV
DS
B12
PT27A
_T_LVD
SC
12
PT27B
_C_LV
DS
A12
PT9A
_T_LVD
SA
2
PT9B
_C_LV
DS
B3
SC
L_PC
LKT0_0_P
T20C_T
C8
SD
A_P
CLK
C0_0_P
T20D_C
B8
VC
CIO
0_1A
8
VC
CIO
0_2B
10
VC
CIO
0_3C
5
R76
33R
7633
R77
33R
7733
R78
33R
7833
18
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 12. SDR-FPGA Connections
55
44
33
22
11
DD
CC
BB
AA
BA
NK
1B
AN
K 3
BA
NK
4
SDR
-FPGA
CO
NN
ECTIO
N
SD
RFor VDDQ
For VDD
SD
RA
M_D
Q0
SD
RA
M_D
Q1
SD
RA
M_D
Q2
SD
RA
M_D
Q3
SD
RA
M_D
Q4
SD
RA
M_D
Q5
SD
RA
M_D
Q6
SD
RA
M_D
Q7
SD
RA
M_LD
QM
SD
RA
M_A
0S
DR
AM
_A1
SD
RA
M_A
2S
DR
AM
_A3
SD
RA
M_A
4S
DR
AM
_A5
SD
RA
M_A
6S
DR
AM
_A7
SD
RA
M_A
8S
DR
AM
_A9
SD
RA
M_A
11S
DR
AM
_A10
SD
RA
M_B
A0
SD
RA
M_B
A1
SD
RA
M_C
AS
_N
SD
RA
M_R
AS
_N
SD
RA
M_W
E_N
SD
RA
M_C
LK
SD
RA
M_C
KE
SD
RA
M_A
0S
DR
AM
_A1
SD
RA
M_A
2S
DR
AM
_A3
SD
RA
M_A
4
SD
RA
M_A
5S
DR
AM
_A6
SD
RA
M_A
7S
DR
AM
_A8
SD
RA
M_C
LKS
DR
AM
_CK
E
SD
RA
M_C
S_N
SD
RA
M_D
Q2
SD
RA
M_D
Q3
SD
RA
M_D
Q4
SD
RA
M_D
Q5
SD
RA
M_D
Q6
SD
RA
M_D
Q7
SD
RA
M_D
Q0
SD
RA
M_D
Q1
SD
RA
M_LD
QM
SD
RA
M_A
11
SD
RA
M_A
9
SD
RA
M_A
10
SD
RA
M_N
C_G
1
SD
RA
M_N
C_G
1
SD
RA
M_B
A0
SD
RA
M_B
A1
SD
RA
M_C
AS
_NS
DR
AM
_RA
S_N
SD
RA
M_D
Q8
SD
RA
M_D
Q9
SD
RA
M_D
Q10
SD
RA
M_D
Q11
SD
RA
M_D
Q12
SD
RA
M_D
Q13
SD
RA
M_D
Q14
SD
RA
M_D
Q15
SD
RA
M_D
Q8
SD
RA
M_D
Q10
SD
RA
M_D
Q9
SD
RA
M_D
Q11
SD
RA
M_D
Q12
SD
RA
M_D
Q13
SD
RA
M_D
Q14
SD
RA
M_D
Q15
SD
RA
M_U
DQ
MS
DR
AM
_UD
QM
SD
RA
M_W
E_N
SD
RA
M_C
S_N
V1P
8V
1P8
V1P
8
V1P
8
V1P
8
V1P
8
V1P
8
GN
DG
ND
V1P
8
GN
D
V1P
8
V1P
8
GN
D
V1P
8
GN
D
XO
2_PIN
_J14_GR
EE
N_LE
D{8}
XO
2_PIN
_J12_RE
D_LE
D{8}
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
610
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
610
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
610
Tuesday, Septem
ber 13, 2011
C331100NF-0201SMT
C331100NF-0201SMT
U1IS42V
M16400K
-75BLI
U1IS42V
M16400K
-75BLI
A0
H7
A1
H8
A10
H9
A11
G2
A2
J8
A3
J7
A4
J3
A5
J2
A6
H3
A7
H2
A8
H1
A9
G3
BA
0G
7
BA
1G
8
CA
S_N
F7
CK
EF3
CLK
F2
CS
_NG
9
DQ
0A
8
DQ
1B
9
DQ
10D
1
DQ
11C
2
DQ
12C
1
DQ
13B
2
DQ
14B
1
DQ
15A
2
DQ
2B
8
DQ
3C
9
DQ
4C
8
DQ
5D
9
DQ
6D
8
DQ
7E
9
DQ
8E
1
DQ
9D
2
LDQ
ME
8
NC
_1G
1
NC
_2E
2
RA
S_N
F8U
DQ
MF1
VD
D_1
E7
VD
D_2
A9
VD
D_3
J9V
DD
Q_1
B3
VD
DQ
_2D
3
VD
DQ
_3A
7
VD
DQ
_4C
7
VS
S_1
A1
VS
S_2
J1
VS
S_3
E3
VS
SQ
_1A
3V
SS
Q_2
C3
VS
SQ
_3B
7V
SS
Q_4
D7
WE
_NF9
BA
NK
4M
AC
HX
02
-40
00
U8E
MachX
O2-4000
BA
NK
4M
AC
HX
02
-40
00
U8E
MachX
O2-4000
PL10C
_PC
LKT4_0_T
G3
PL10D
_PC
LKC
4_0_CH
2
PL13A
_TH
1
PL13B
_CH
3
PL14A
_TJ1
PL14B
_CJ2
PL9A
_TF1
PL9B
_CF3
VC
CIO
4G
1
C226100NF-0201SMT
C226100NF-0201SMT
C58
100NF-0201SMTC
58100NF-0201SMT
C227100NF-0201SMT
C227100NF-0201SMT
C333100NF-0201SMT
C333100NF-0201SMT
C332100NF-0201SMT
C332100NF-0201SMT
C59
100NF-0201SMT
C59
100NF-0201SMT
C228100NF-0201SMT
C228100NF-0201SMT
C61
100NF-0201SMT
C61
100NF-0201SMT
BA
NK
1M
AC
HX
02
-40
00
U8B
MachX
O2-4000
BA
NK
1M
AC
HX
02
-40
00
U8B
MachX
O2-4000
PR
10A_P
CLK
T1_0_DQ
0_TG
13
PR
10B_P
CLK
C1_0_D
Q0_C
H12
PR
13A_D
QS
1_TJ12
PR
13B_D
QS
1N_C
J14
PR
14A_D
Q1_T
J13
PR
14B_D
Q1_C
K12
PR
15A_D
Q1_T
K13
PR
15B_D
Q1_C
K14
PR
16A_D
Q1_T
L14
PR
16B_D
Q1_C
M13
PR
18A_D
Q1_T
M12
PR
18B_D
Q1_C
M14
PR
19A_D
Q1_T
N13
PR
19B_D
Q1_C
N14
PR
2A_R
_GP
LLT_FB_D
Q0_T
B14
PR
2B_R
_GP
LLC_FB
_DQ
0_CC
13
PR
3A_R
_GP
LLT_IN_D
Q0_T
C14
PR
3B_R
_GP
LLC_IN
_DQ
0_CD
12
PR
5A_D
Q0_T
E12
PR
5B_D
Q0_C
E14
PR
6A_D
Q0_T
E13
PR
6B_D
Q0_C
F12
PR
8A_D
Q0_T
F13
PR
8B_D
Q0_C
F14
PR
9A_D
QS
0_TG
12
PR
9B_D
QS
0N_C
G14
VC
CIO
1_1D
14
VC
CIO
1_2H
14
VC
CIO
1_3L12
MA
CH
X0
2-4
00
0B
AN
K 3
U8D
MachX
O2-4000
MA
CH
X0
2-4
00
0B
AN
K 3
U8D
MachX
O2-4000
PL16A
_TJ3
PL16B
_CK
2
PL17A
_PC
LKT3_0_T
K1
PL17B
_PC
LKC
3_0_CK
3
PL19B
_CL3
PL20A
_TM
1
PL20B
_CM
2
VC
CIO
3L1
C60
100NF-0201SMT
C60
100NF-0201SMT
C62
100NF-0201SMT
C62
100NF-0201SMT
C330100NF-0201SMT
C330100NF-0201SMT
R2610K
R2610K
19
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 13. Texas Instruments Interface Connections
55
44
33
22
11
DD
CC
BB
AA
XO2 C
ON
NEC
TOR
(BO
TTOM
- PAR
ALLEL) to TI IN
TERFA
CE C
ON
NEC
TOR
EC
P3_P
RL_S
DA
TAE
CP
3_PR
L_SC
LK
EC
P3_LIN
E_V
ALID
ECP3_FR
AM
E_VALID
ECP3_D
OU
T3
ECP3_D
OU
T5
ECP3_D
OU
T7
ECP3_D
OU
T9
ECP3_D
OU
T11
ECP3_D
OU
T2
ECP3_D
OU
T4
ECP3_D
OU
T6
ECP3_D
OU
T8
ECP3_D
OU
T10
ECP3_D
OU
T1EC
P3_DO
UT0
EC
P3_P
IXC
LK
EC
P3_D
OU
T12_OP
TION
EC
P3_D
OU
T13_OP
TION
V3P
3
GN
D
V5P
0
EC
P3_P
RL_S
DA
TA{4,5}
EC
P3_P
RL_S
CLK
{4,5}
EC
P3_S
LVS
_0N{5}
EC
P3_S
LVS
_4N{5}
EC
P3_S
LVS
_0P{5}
EC
P3_S
LVS
_7P{5}
EC
P3_S
LVS
_2P{5}
EC
P3_S
LVS
_8N{5}
EC
P3_S
LVS
_3N{5}
EC
P3_S
LVS
_5P{5}
EC
P3_S
LVS
_4P{5}
EC
P3_S
LVS
_9P{5}
EC
P3_S
LVS
_7N{5}
EC
P3_S
LVS
_2N{5}
EC
P3_S
LVS
_9N{5}
EC
P3_S
LVS
_5N{5}
EC
P3_P
IXC
LK{5}
SC
LK_2
{4}
RE
SE
T_BA
R{4}
SA
DD
R_2
{4}
SD
ATA
_2{4}
EC
P3_D
OU
T13_OP
TION
{5}E
CP
3_DO
UT12_O
PTIO
N{5}
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
710
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
710
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
710
Tuesday, Septem
ber 13, 2011
R30
DN
LR
30D
NL
R29
DN
LR
29D
NL
J9BL112-36S
PA
RT_N
UM
BE
R = B
L112-36SM
anufacturer = SW
ITCH
TEC
H
J9BL112-36S
PA
RT_N
UM
BE
R = B
L112-36SM
anufacturer = SW
ITCH
TEC
H
VC
C3.3_1
1
VC
C3.3_2
2
VC
C3.3_3
3
VC
C5.5_1
4
VC
C5.5_2
5
GN
D1
6
EX
T_CLK
7
GN
D2
8
AFE
_CLK
9
GN
D3
10
AFE
_VD
11
AFE
_HD
12
AFE
_D13
13
AFE
_D12
14
AFE
_D11
15
AFE
_D10
16
AFE
_D9
17
AFE
_D8
18
AFE
_D7
19
AFE
_D6
20
AFE
_D5
21
AFE
_D4
22
AFE
_D3
23
AFE
_D2
24
GN
D4
25
GN
D5
26
AFE
_D1
27
AFE
_D0
28
I2C_S
CLK
29
I2C_S
DA
TA30
SP
I_SD
O31
SP
I_SC
LK32
AFE
_RE
SE
T33
SP
I_EN
34
AFE
_D14
35
AFE
_D15
36
ME
CH
137
ME
CH
238
20
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 14. MachXO2 Power, Ground and Miscellaneous
55
44
33
22
11
DD
CC
BB
AA
FOR
VC
C
XO
2 FP
GA
PW
R,G
ND
& M
isc
Place R
28 near Y1
Place Y1 near U8
OS
CILLA
TOR
-27
MH
Z
LED IN
DIC
ATIO
N
RES
ET-SW
ITCH
RE
SE
T_PB
V1P
2
GN
D
V1P
2
V3P
3V
3P3
V2P
5
GN
DG
ND
V2P
5
CLK
_27MH
z{5}
XO
2_PIN
_J12_RE
D_LE
D{6}
XO
2_PIN
_J14_GR
EE
N_LE
D{6}
RE
SE
T_PB
{4}
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
810
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
810
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
810
Tuesday, Septem
ber 13, 2011
C11
100NF-0201SMT
C11
100NF-0201SMT
C225
0.1uFC
2250.1uF
12
R16
1KR
161K
SW
14P
BS
witch
PART_NUMBER = KSR251GLFSManufacturer = C & K COMPONENTS
SW
14P
BS
witch
PART_NUMBER = KSR251GLFSManufacturer = C & K COMPONENTS
AB
C10
100NF-0201SMT
C10
100NF-0201SMT
R14
180R
0402
R14
180R
0402
Y1
27 MH
ZD
IP
art Num
ber = DS
C1001A
E2-27.0000
Manufacturer = D
ISC
ER
A
Y1
27 MH
ZD
IP
art Num
ber = DS
C1001A
E2-27.0000
Manufacturer = D
ISC
ER
A
VC
C4
OU
T3
GN
D2
EN
1
LED
2
LED
Manufacturer = A
VA
GO
PA
RT_N
UM
BE
R = H
SM
H-C
190
LED
2
LED
Manufacturer = A
VA
GO
PA
RT_N
UM
BE
R = H
SM
H-C
190
21
R87
301KR
87301K
R28
27R
2827
R86
100
R86
100
Q2
MM
BT3904T
Q2
MM
BT3904T
C334
1 uF
C334
1 uF
C12
100NF-0201SMT
C12
100NF-0201SMT
FB1
BLM
21AG
601SN
1D
FB1
BLM
21AG
601SN
1D
R15
1KR
151K R
150
4_7K
R150
4_7K
R13
180R
0402
R13
180R
0402
C13
100NF-0201SMT
C13
100NF-0201SMT
LED
1
LED
Manufacturer = A
VA
GO
PA
RT_N
UM
BE
R = H
SM
G-C
190
LED
1
LED
Manufacturer = A
VA
GO
PA
RT_N
UM
BE
R = H
SM
G-C
190
21
Q1
MM
BT3904T
Manufacturer = Fairchild
PA
RT_N
UM
BE
R = M
MB
T3904T
Q1
MM
BT3904T
Manufacturer = Fairchild
PA
RT_N
UM
BE
R = M
MB
T3904T
Pow
erM
AC
HX
02
-40
00
U8G
MachX
O2-4000
Pow
erM
AC
HX
02
-40
00
U8G
MachX
O2-4000
GN
D1
A5
GN
D10
P10
GN
D2
B11
GN
D3
D2
GN
D4
D13
GN
D5
G2
GN
D6
H13
GN
D7
L2
GN
D8
L13
GN
D9
P5
NC
C7
VC
C1
A1
VC
C2
A14
VC
C3
N1
VC
C4
P14
C9
1uFC
91uF
21
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 15. USB Download
55
44
33
22
11
DD
CC
BB
AA
(Upper U
SB
)PR
OG
Local JTAG header (ispVM)
TMS
TCKDONEINITn
+V3P3
TDI
GND
TDO
PROGRAMn
6 MH
z
18pF = 12pF + Ground Plane ( 6pF )
FOR JTAG HDR
FOR LT
JTAG
HEA
DER
US
B C
ON
NEC
TION
S
US
B1_C
S
US
B1_S
K
US
B1_D
US
B1_Q
US
B_TD
I
US
B_TM
SU
SB
_TCK
US
B_TD
O
US
B_TD
I
US
B_TM
S_2P
5
US
B_TC
K_2P
5
US
B_TD
I_2P5
US
B_TD
O_2P
5U
SB
_TDO
US
B_TM
S
US
B_TC
K
V3P
3V
5P0
V5P
0V
3P3
V5P
0
SH
IELD
_GN
D_U
SB
V5P
0
V3P
3
V3P
3
V2P
5
V2P
5
V3P
3
V3P
3V
3P3
V2P
5
Title
veR
reb
muN t
nemu
coD
ezi
S
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S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
910
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
910
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
910
Tuesday, Septem
ber 13, 2011
R109
330RR
109330R
C53
100nF
C53
100nF
R116
10k
R116
10k
R106
0RR
1060R
C191
100nF
C191
100nF
C30
0.01uf
C30
0.01uf
C195
12pFD
I
C195
12pFD
I
U7
M93C
46-WM
N6TP
PA
RT_N
UM
BE
R = M
93C46-W
MN
6TPM
anufacturer = STM
icroelectronics
U7
M93C
46-WM
N6TP
PA
RT_N
UM
BE
R = M
93C46-W
MN
6TPM
anufacturer = STM
icroelectronics
CS
1
CLK
2
DIN
3
QO
UT
4V
SS
5O
RG
6N
.C.
7V
CC
8
C189
12pFD
I
C189
12pFD
I
R151
10K
R151
10K
TP71
TP_LO
OP
_RE
D
TP71
TP_LO
OP
_RE
D
1
R114
2_2KD
IR
1142_2K
DI
R126
27R
12627
C190
33nF C190
33nF
C21
100nF
C21
100nF
VCC
GND
TDO
TDI
ispEN_N
NC
TMS
TCK
DONE
INITN
J3HE
AD
ER
10
DN
I
VCC
GND
TDO
TDI
ispEN_N
NC
TMS
TCK
DONE
INITN
J3HE
AD
ER
10
DN
I
123456
7
8910
R125
27R
12527
C216
100nF
C216
100nFR
1280 / D
NI
R0805
R128
0 / DN
I
R0805
R112
10kR
11210k
R3
4_7kR
34_7k
C188
100nF
C188
100nF
R110
1MDI
R110
1MDI
R113
1KDI
R113
1KDI
R2
4_7kR
24_7k
TXB0104DR
U4
TXB0104DR
U4
VC
CA
1
A1
2
A2
3
A3
4
A4
5
NC
16
GN
D7
OE
8
NC
29
B4
10B
311
B2
12B
113
VC
CB
14
C3
100NF-0603SMT
C3
100NF-0603SMT
R27
1k5R
271k5
J13
US
B-TY
PE
A
Manufacturer = FC
IP
AR
T_NU
MB
ER
= 87520-0010BLF
J13
US
B-TY
PE
A
Manufacturer = FC
IP
AR
T_NU
MB
ER
= 87520-0010BLF
VB
US
1
D-
2
D+
3
GN
D4
SH
15
SH
26
R1
1_0kR
11_0k
R101
0RR
1010R
R4
4_7kR
44_7k
C212
33pF C212
33pF
C211
33pF C211
33pF
U5
FTD2232D
PA
RT_N
UM
BE
R = FT2232D
Manufacturer = FTD
I CH
IP
U5
FTD2232D
PA
RT_N
UM
BE
R = FT2232D
Manufacturer = FTD
I CH
IP
3V3O
UT
6
US
BD
M8
US
BD
P7
NO
T_RS
TOU
T5
NO
T_RS
TIN4
XTIN
43
XTO
UT
44
EE
CS
48
EE
SK
1
EE
DA
TA2
TES
T47
SI/W
UB
26B
CB
US
327
BC
BU
S2
28B
CB
US
129
BC
BU
S0
30B
DB
US
732
BD
BU
S6
33B
DB
US
535
BD
BU
S4
36B
DB
US
337
BD
BU
S2
38B
DB
US
139
BD
BU
S0
40
SI/W
UA
10A
CB
US
311
AC
BU
S2
12A
CB
US
113
AC
BU
S0
15A
DB
US
716
AD
BU
S6
17A
DB
US
519
AD
BU
S4
20A
DB
US
321
AD
BU
S2
22A
DB
US
123
AD
BU
S0
24
NO
T_PW
RE
N41
AGND45
DGND_99
DGND_1818
DGND_2525
DGND_3434
VCCIOB31VCCIOA14DVCC_4242DVCC_33
AVCC46
JTAG
MA
CH
X0
2-4
00
0
U8H
MachX
O2-4000
JTAG
MA
CH
X0
2-4
00
0
U8H
MachX
O2-4000
TDO
_PT13C
_TA
4TD
I_PT13D
_CB
4TC
K_TE
ST_C
LK_P
T15C_T
B6
TMS
_PT15D
_CA
6
C193
100nF
C193
100nF
R104
0RR
1040R
C29
0.01uf
C29
0.01uf
R102
0RR
1020R
Y2
ATS
060SM
-1 HC
-49/US
-SM
DI
Y2
ATS
060SM
-1 HC
-49/US
-SM
DI
12
22
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Figure 16. Register Connections
55
44
33
22
11
DD
CC
BB
AA
+1.8v1.1 A
Short 1-2: 1.806vShort 2-3: 3.298v
1.2v/ms
1.2v/ms
1.2v/ms
1.2v/ms
+3.3 v1.35 A
+1.2 v1.35 A
+2.5 v1.1 A
Vout = 0.8 * (R54/R52 + 1) = 1.21 v
Vout = 0.8 * (R53/R5 + 1) = 2.52 v
Vout = 0.8 * (R46/R45 + 1) = 3.28 v
Short 1-2: 1.806vShort 2-3: 3.298v
REG
ULA
TOR
CO
NN
ECTIO
NS
V5P
0
V3P
3
V2P
5
V3P
3
V3P
3
V5P
0
V1P
2
V3P
3V
3P3
V1P
8
Title
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reb
muN t
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coD
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S
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S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
1010
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
1010
Tuesday, Septem
ber 13, 2011
Title
veR
reb
muN t
nemu
coD
ezi
S
teeh
S:e
taD
of
A>c
oD< XO
2 IN
TERFA
CE B
OA
RD
B
1010
Tuesday, Septem
ber 13, 2011
C63
10pF
C63
10pF
TP70
TP_LO
OP
_RE
D
TP70
TP_LO
OP
_RE
D
1
C80
10uF,25VC1206
C80
10uF,25VC1206
L44.7uH
SUMIDA
L44.7uH
SUMIDA
D3
DFLS
220LD
3D
FLS220L
12
R56
8_06K-0603S
MT
R56
8_06K-0603S
MT
L34.7uH
SUMIDA
L34.7uH
SUMIDA
C65
150pFC
65150pF
D1
DFLS
220LD
1D
FLS220L
12
R47
51kR
4751k
PP
2P
P2
12R
5321_5K
1%R
5321_5K
1%
R49
51kR
4951k
C79
22uF,6.3VC0805
C79
22uF,6.3VC0805
D4
DFLS
220LD
4D
FLS220L
12TP
90
TP_LO
OP
_BLA
CK
TP90
TP_LO
OP
_BLA
CK
1
R51
22_1K-0603S
MT
R51
22_1K-0603S
MT
C85
22uF,6.3VC0805
C85
22uF,6.3VC0805
R57
8_06K-0603S
MT
R57
8_06K-0603S
MT
C5
10uF,25VC1206
C5
10uF,25VC1206
C83
0.22uF16V
C83
0.22uF16V
C7
22uF,6.3VC0805
C7
22uF,6.3VC0805
C4
22uF,6.3VC0805
C4
22uF,6.3VC0805
R54
5_11K1%
R54
5_11K1%
D7
1N4448W D
71N
4448W
21
J6
HD
R3_100M
IL
J6
HD
R3_100M
IL
123
D5
1N4448W
D5
1N4448W
21
R59
21_5K1%
R59
21_5K1%
R45
11.5k1% R
4511.5k1%
C69
1000pFC
691000pF
C82
22uF,6.3VC0805
C82
22uF,6.3VC0805
R6
10k1% R
610k1%
R42
51kR
4251k
R52
10_0K1% R
5210_0K1%
U10
LT3508EU
FU
10LT3508E
UF
FB2
18
VC
219
PG
220
RT/S
YN
C22
SHDN21
FB1
1
TRA
CK
/SS
12
BO
OS
T17
SW
18
VIN19
VC
124
VIN210
PG
123
SW
211
BO
OS
T212
TRA
CK
/SS
217
GND525
GND613
GND714
GND46 GND35 GND24 GND13
GND815
GND916
L26.8uH
SUMIDA
L26.8uH
SUMIDA
C75
1000pFC
751000pF
R50
51kR
5051k
R44
51kR
4451k
D6
1N4448W
D6
1N4448W
21
D2
DFLS
220LD
2D
FLS220L
12
R58
22_1K-0603S
MT
R58
22_1K-0603S
MT
C81
0.22uF16V
C81
0.22uF16V
TP69
TP_LO
OP
_RE
D
TP69
TP_LO
OP
_RE
D
1
C84
22uF,6.3VC0805
C84
22uF,6.3VC0805
TP66
TP_LO
OP
_RE
D
TP66
TP_LO
OP
_RE
D
1
C66
10pF
C66
10pF
J20
HD
R3_100M
IL
J20
HD
R3_100M
IL
123
C77
22uF,6.3VC0805
C77
22uF,6.3VC0805
PP
1P
P1
12
C78
1000pFC
781000pF
R46
35.7k1%
R46
35.7k1%
R5
10_0K1%
R5
10_0K1%
C76
22uF,6.3VC0805
C76
22uF,6.3VC0805
U11
LT3508EU
FU
11LT3508E
UF
FB2
18
VC
219
PG
220
RT/S
YN
C22
SHDN21
FB1
1
TRA
CK
/SS
12
BO
OS
T17
SW
18
VIN19
VC
124
VIN210
PG
123
SW
211
BO
OS
T212
TRA
CK
/SS
217
GND525
GND613
GND714
GND46 GND35 GND24 GND13
GND815
GND916
R48
63.4k
1%
Freq = 625 KHz
R48
63.4k
1%
Freq = 625 KHz
TP68
TP_LO
OP
_RE
D
TP68
TP_LO
OP
_RE
D
1
C74
0.22uF16V
C74
0.22uF16V
PP
4P
P4
12C
64
150pF
C64
150pF
C68
10pF
C68
10pFP
P3
PP
3
12
C8
22uF,6.3VC0805
C8
22uF,6.3VC0805
TP91
TP_LO
OP
_BLA
CK
TP91
TP_LO
OP
_BLA
CK
1
C70
150pF
C70
150pF
TP67
TP_LO
OP
_RE
D
TP67
TP_LO
OP
_RE
D
1
D8
1N4448W
D8
1N4448W
21
R41
51kR
4151k
C67
1000pFC
671000pFC
71
10pF
C71
10pF
C72
150pFC
72150pF
C73
0.22uF16V
C73
0.22uF16V
L16.8uH
SUMIDA
L16.8uH
SUMIDA
R43
34k
1%
Freq = 1.0 MHz
R43
34k
1%
Freq = 1.0 MHz
23
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Appendix B. Programming Using JTAG Flywire ConnectionsThe MachXO2 Dual Sensor Interface Board includes provision for the flywire-connected programming header J3. The pins for the J3 header are not installed, as typical use of the board is through the USB download. To use a fly-wire JTAG connection rather than the built-in USB download at J13, the user will need to first acquire the flywire download cable and connect it to J3. The pinout for J3 is provided in Table 11.
Important Note: The board must be un-powered when connecting, disconnecting or reconnecting an ispDOWN-LOAD cable or USB cable. Always connect an ispDOWNLOAD cable’s GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP3 FPGA and ren-der the board inoperable.
Table 11. JTAG Flywire Programming Header
J3 Function
1 3_3V
2 TDO
3 TDI
4 NC
5 NC
6 TMS
7 GND
8 TCK
9 NC
10 NC
Requirements:
• PC with Lattice Diamond design software version 1.3 (or later), installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option to install these drivers is included as part of the ispVM System setup.
• Any ispDOWNLOAD or Lattice USB Cable (pDS4102-DL2x, HW7265-DL3x, HW-USB-2x, etc.).
24
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
Appendix C. Bill of MaterialsTable 12. MachXO2 Dual Sensor Interface Board Bill of Materials
Item Qty Reference Part PCB Footprint Part Number Manufacturer Description
1 23 C1, C2, C6, C10, C11, C12, C13, C58, C59, C60, C61, C62, C220, C221, C222, C224, C226, C227, C228, C330, C331, C332, C333
100NF-0201SMT C0201 LMK063BJ104KP-F Taiyo Yuden CAP CER .10UF 10V X5R 0201
2 2 C189, C195 12pF C0603 C1608C0G1H120J TDK CAP CER 12PF 50V C0G 5% 0603
3 1 C190 33nF C0402 ECJ-0EB1A333K Panasonic - ECG CAP 33000PF 10V CERAMIC X5R 0402
4 1 C21 100nF C0201 LMK063BJ104KP-F Taiyo Yuden CAP CER .10UF 10V X5R 0201
5 2 C211, C212 33pF C0402 ECJ-0EC1H330J Panasonic - ECG CAP 33PF 50V CERAMIC 0402 SMD
6 1 C225 0.1uF C0402 GRM155F51E104ZA01D Murata CAP - CER, 0.1uF, 0402, 25VDC, Y5V
7 2 C29, C30 0.01uf C0402 C1005X8R1E103K TDK CAP CER 0.01UF 25V X8R 10% 0402
8 1 C3 100NF-0603SMT C0603 0603YC104JAZ2A AVX CAP CER .10UF 16V X7R 5% 0603
9 1 C334 1 uF C0603 C1608X7R1C105K TDK CAP CER 1.0UF 16V X7R 10% 0603
10 9 C4, C7, C8, C76, C77, C79, C82, C84, C85
22uF, 6.3V C0805 C2012X5R1C226K TDK CAP CER 22UF 16V X5R 10% 0805
11 2 C5, C80 10uF, 25V C1206 TMK316B7106KL-TD Taiyo Yuden CAP CER 10UF 25V X7R 10% 1206
12 5 C53, C188, C191, C193, C216
100nF C0402 ECJ-0EB1A104K Panasonic - ECG CAP 0.1UF 10V CERAMIC X5R 0402
13 4 C63, C66, C68, C71 10pF C0402 04025U100FAT2A AVX CAP CERM 10PF 50V NP0 RF 0402
14 4 C64, C65, C70, C72 150pF C0402 C1005C0G1H151J TDK CAP CER 150PF 50V C0G 5% 0402
15 4 C67, C69, C75, C78 1000pF C0402 GRM155R71H102KA01D Murata CAP 1000PF 50V CERAMIC X7R 0402 SMD
16 4 C73, C74, C81, C83 0.22uF C0402 GRM155R71C224KA12D Murata CAP CER .22UF 16V X7R 0402
17 1 C9 1uF C0402 ECJ-0EB0J105K Panasonic CAP CERAMIC 1UF 6.3V X5R 0402
18 4 D1, D2, D3, D4 DFLS220L POWERDI123-KS DFLS220L-7 Diodes Inc DIODE SCHOTTKY 2A 20V PWRDI 123
19 4 D5, D6, D7, D8 1N4448W SOD123 1N4448W-7-F Diodes Inc DIODE SWITCH 75V 400MW SOD123
20 1 FB1 BLM21AG601SN1D FB0805 BLM21AG601SN1D Murata FERRITE CHIP 600 OHM 200MA 0805
21 2 J1, J4 DF12__-40DS-0.5V_RECEPTACLE
HRS-DF12A-RECEPTACLE-
CENTER
DF12(4.0)-40DS-0.5V Hirose CONN RECEPT 40POS 0.5MM GOLD SMD
22 1 J13 USB-TYPE A 87520-0010BLF 87520-0010BLF FCI CONN RCPT USB TYPE A R/A PCB
23 3 J14, J15, J16 2 PIN JPR 2PIN_JPR_100MIL — — —
24 2 J2, J10 4PIN_SMD_0603 4PIN_JPR_0603 — — —
25 1 J21 3PIN_SMD_0603 3PIN_SMD_0603 — — —
26 1 J3 HEADER 10 HD10x1 — — —
27 2 J5, J11 DF12(4.0)-40DP-0.5V_HEADER
HRS-DF12A-HEADER DF12(4.0)-40DP-0.5V Hirose CONN HEADER 40POS 4MM SMD 0.5MM
28 2 J6, J20 HDR3_100MIL HDR3_100MIL — — —
29 1 J7 DF12_40DS-0.5V_RECEPTACLE
HIROSE-DF12_40DS-0_5V
DF12(4.0)-40DS-0.5V Hirose CONN RECEPT 40POS 0.5MM GOLD SMD
30 1 J8 DF12(4.0)-40DP-0.5V_HEADER
HIROSE-DF12_40DP-0_5V
DF12(4.0)-40DP-0.5V Hirose CONN HEADER 40POS 4MM SMD 0.5MM
31 1 J9 BL112-36S BL112-36S BL112-36S SWITCHTECH 36PIN TI INTERFACE CON-NECTOR
32 1 L1 6.8uH L-CDRH3D18 CDRH3D18NP-6R8N Sumida 4 x 4 x 2 mm, 6.8uH Power inductor
33 1 L2 6.8uH L-CDRH4D18C CDRH4D18CNP-6R8P Sumida 5.1x5.1x2.0 mm, 6.8uH Power inductor
34 1 L3 4.7uH L-CDRH3D18 CDRH3D18NP-4R7N Sumida 4 x 4 x 2 mm, 4.7uH Power inductor
35 1 L4 4.7uH L-CDRH4D18C CDRH4D18CNP-4R7P Sumida 5.1x5.1x2.0 mm, 4.7uH Power inductor
36 1 LED1 LED LED0603 HSMG-C190 Avago LED 570NM GREEN DIFF 0603 SMD
25
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
37 1 LED2 LED LED0603 HSMH-C190 Avago LED 660NM RED DIFF 0603 SMD
38 4 PP1, PP2, PP3, PP4 PROBEPOINT probepoint — — —
39 2 Q1, Q2 MMBT3904T SOT-523F_MMBT MMBT3904T Fairchild TRANS NPN 40V 200MA SOT-523F
40 1 R1 1_0k R0603 ERJ-3EKF1001V Panasonic - ECG RES 1.00K OHM 1/10W 1% 0603 SMD
41 4 R101, R102, R104, R106 0R R0603 ERJ-3GEY0R00V Panasonic - ECG RES 0.0 OHM 1/10W 0603 SMD
42 1 R109 330R R0603 ERJ-3GEYJ331V Panasonic - ECG RES 330 OHM 1/10W 5% 0603 SMD
43 1 R110 1M R0603 RC0603FR-071ML Yageo RES 1.00M OHM 1/10W 1% 0603 SMD
44 2 R112, R116 10k R0603 RNCS0603BKE10K0 Stackpole RES 1/16W 10K OHM 0.1% 0603
45 1 R113 1K R0603 ERJ-3EKF1001V Panasonic - ECG RES 1.00K OHM 1/10W 1% 0603 SMD
46 1 R114 2_2K R0603 ERJ-3EKF2201V Panasonic - ECG RES 2.20K OHM 1/10W 1% 0603 SMD
47 1 R128 0 / DNI R0805 — — —
48 2 R13, R14 180 R0402 CRCW0402180RFKED Vishay RES 180 OHM 1/16W 1% 0402 SMD
49 2 R15, R16 1K R0402 CRCW04021K00FKED Vishay RES 1.00K OHM 1/16W 1% 0402 SMD
50 1 R150 4_7K R0402 MCR01MZPJ472 Rohm RES 4.7K OHM 1/16W 5% 0402 SMD
51 3 R2, R3, R4 4_7k R0603 ERJ-3EKF4701V Panasonic - ECG RES 4.70K OHM 1/10W 1% 0603 SMD
52 2 R26, R151 10K R0402 ERJ-2RKF1002X Panasonic RES 10.0K OHM 1/10W 1% 0402 SMD
53 1 R27 1k5 R0603 ERJ-3EKF1501V Panasonic - ECG RES 1.50K OHM 1/10W 1% 0603 SMD
54 3 R28, R125, R126 27 R0603 ERJ-3GEYJ270V Panasonic - ECG RES 27 OHM 1/10W 5% 0603 SMD
55 2 R29, R30 DNL R0603 — — —
56 6 R41, R42, R44, R47, R49, R50
51k R0402 ERJ-2RKF5102X Panasonic RES 51.0K OHM 1/10W 1% 0402 SMD
57 1 R43 34k R0402 ERJ-2RKF3402X Panasonic RES 34.0K OHM 1/10W 1% 0402 SMD
58 1 R45 11.5k R0402 ERJ-2RKF1152X Panasonic RES 11.5K OHM 1/10W 1% 0402 SMD
59 1 R46 35.7k R0402 ERJ-2RKF3572X Panasonic RES 35.7K OHM 1/10W 1% 0402 SMD
60 1 R48 63.4k R0402 ERJ-2RKF6342X Panasonic - ECG RES 63.4K OHM 1/10W 1% 0402 SMD
61 4 R5, R11, R12, R52 10_0K R0402 ERJ-2RKF1002X Panasonic RES 10.0K OHM 1/10W 1% 0402 SMD
62 2 R51, R58 22_1K-0603SMT R0603 ERJ-3EKF2212V Panasonic - ECG RES 22.1K OHM 1/10W 1% 0603 SMD
63 2 R53, R59 21_5K R0402 ERJ-2RKF2152X Panasonic RES 21.5K OHM 1/10W 1% 0402 SMD
64 1 R54 5_11K R0402 ERJ-2RKF5111X Panasonic RES 5.11K OHM 1/10W 1% 0402 SMD
65 2 R56, R57 8_06K-0603SMT R0603 CRCW06038K06FKEA Vishay RES 8.06K OHM 1/10W 1% 0603 SMD
66 1 R6 10k R0402 ERJ-2RKF1002X Panasonic RES 10.0K OHM 1/10W 1% 0402 SMD
67 17 R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R88, R89
33 R0402 ERA-2AKD330X Panasonic RES 33 OHM 1/16W .5% 0402 SMD
68 1 R86 100 R0402 ERA-2AEB101X Panasonic RES 100 OHM 1/16W .1% 0402 SMD
69 1 R87 301K R0402 ERJ-2RKF3013X Panasonic RES 301K OHM 1/10W 1% 0402 SMD
70 1 SW14 PBSwitch PUSHBUTTON_KSR251
KSR251GLFS C & K COMPONENTS SWITCH TACT SILVR 450GF GULLWING
71 6 TP66, TP67, TP68, TP69, TP70, TP71
TP_LOOP_RED TP_RED_5000 5000 Keystone TEST POINT PC MINI .040"D RED
72 2 TP90, TP91 TP_LOOP_BLACK TP_BLACK_5001 5001 Keystone TEST POINT PC MINI .040"D BLACK
73 1 U1 IS42VM16400K-6BLI
54_FBGA_IS42VM16400G IS42VM16400K-6BLI ISSI 1M x 16Bits x 4Banks Mobile Synchronous DRAM
Table 12. MachXO2 Dual Sensor Interface Board Bill of Materials (Continued)
Item Qty Reference Part PCB Footprint Part Number Manufacturer Description
26
MachXO2 Dual Sensor Interface BoardLattice Semiconductor User’s Guide
74 2 U10, U11 LT3508EUF QFN24UF-4X4 LT3508EUF#PBF Linear Technology IC REG 1.4A DUAL MONO 24-QFN
75 1 U4 LT_TXB0104DR SOIC14_TXB0104DR
TXB0104DR Texas Instruments SOIC,14pins,4bit, Bidirectional, Voltage Level translator
76 1 U5 FTD2232D LQFP48 FT2232D FTDI Chip Dual USB to serial UART/FIFO IC
77 1 U7 M93C46-WMN6TP
SO-08NARROW_150MIL M93C46-WMN6TP STMicroelectronics IC EEPROM 1KBIT 2MHZ 8SOIC
78 1 U8 MachXO2-4000 132_CSBGA_MACHX02_4000
LCMXO2-4000HE-6MG132C Lattice Semiconductor MachXO2-4000 in the 132csBGA package
79 1 Y1 27 MHZ DSC1001-CE-27_000
DSC1001AE2-27.0000 DISCERA OSC 27.0000 MHZ 1.7-3.6V SMD
80 1 Y2 ATS060SM-1 HC-49/US-SM
ATS060SM ATS060SM-1 CTS-Frequency Controls CRYSTAL 6.0000MHZ SMD
81 1 X02_INTERFACE_BOARD PCB
— — 305-PD-11-0678 Pactron —
Table 12. MachXO2 Dual Sensor Interface Board Bill of Materials (Continued)
Item Qty Reference Part PCB Footprint Part Number Manufacturer Description
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information: Lattice:
LCMXO2-4000HE-DSIB-EVN