Machine Learning for Electronic Design Automation: A Survey...Machine Learning for Electronic Design...
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Machine Learning for Electronic Design Automation: A Survey Prof. Yu Wang (汪玉) Reporter: Xuefei Ning (宁雪妃) Co-worked with students from course Computer-Aided Design of Digital Circuits and Systems (2020 Spring): Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Chaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong Thanks for the help/suggestions from: Bei Yu, Haoyu Yang, Yuzhe Ma, CSE, CUHK 2020.08.29
Transcript of Machine Learning for Electronic Design Automation: A Survey...Machine Learning for Electronic Design...
Machine Learning for Electronic Design Automation: A Survey
Prof. Yu Wang (汪玉)Reporter: Xuefei Ning (宁雪妃)
Co-worked with students from course Computer-Aided Design of Digital Circuits and Systems (2020 Spring):Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Chaoyang Shen, Juejian Wu,
Yuanfan Xu, Hengrui Zhang, Kai ZhongThanks for the help/suggestions from: Bei Yu, Haoyu Yang, Yuzhe Ma, CSE, CUHK
2020.08.29
Menu
• Background• From EDA perspective: stage by stage• From ML perspective: role by role
IC design challenge
IC design flow
https://en.wikipedia.org/wiki/Transistor_count
The IC design flow is still slow,how can machine learning help?
Number of transistors on IC chips (1971-2018)
Architectural Design
Logic Design (RTL)
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
ML for EDA: Industry Efforts
• https://www.cadence.com/en_US/home/solutions/machine-learning.html• https://news.synopsys.com/2020-03-04-Samsung-Adopts-Synopsys-Machine-Learning-Driven-IC-Compiler-II-for-its-Next-Generation-5nm-Mobile-SoC-Design• https://www.synopsys.com/implementation-and-signoff/resources/articles/machine-learning-everywhere.html
CadenceSynopsys
Used in Samsung’s 5nm mobile SoC production
Mentor
ML for EDA: Industry Efforts
DARPA MAGESTIC project: Cadence, NVIDIA, CMU(Machine-learning driven Automatic Generation of Electronic Systems Through Intelligent Collaboration)
• https://eri-summit.darpa.mil/docs/ERIPoster_Designs_IDEA_Cadence.pdf
ML development
Model
Learning paradigm
Supervised learning Unsupervised learning Reinforcement learningActive learning …
Data with label Data w.o. label Initially unlabeled,actively query label
Reward of sequential decisions
SVM
Random forest
CNN GCNNeural Networks
Invited talk, Jure Leskovec, WWW 2020
MLP
Handle different types of input data
RNN
Menu
• Background• From EDA perspective: stage by stage• From ML perspective: role by role
High-level synthesis
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
Prediction(static dataset)
Timing and resource usage• [Dai et. al., FCCM 2018]• [Makrani et. al., FPL 2019]• [Liu et. al., FPL 2015]
Routing congestion prediction• [Maarouf et. al., FPL 2018]• [Li et. al., TCAD 2017]• [Zhao et. al., 2019]
Cross platform prediction• [Makrani et. al., 2019] Predict speedup
estimation for target FPGA over ARMModelsLinear Regression, MLP, SVM,
Decision Tree, Random Forest, Gaussian Process…Or ensemble/stack of these models
High-level synthesis
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesisPredictor-based search
(Active explored dataset)
Active learning paradigmPredict pareto frontier• TED [Liu et. al., DAC 2013]
Select a representative set to train the learning model• PAL [Zuluaga et. al., ICML 2013]
Gaussian process to predict perf with uncertainty, sample those on pareto• ATNE [Meng et. al., DATE 2016]
Instead of focusing on absolute perf value, focus on the ranking. And eliminate non-pareto-optimal designs incrementally
Other• STAGE [Kim et. al., ICCAD 2018]
Find good initial point with predictor[Liu et. al., DAC 2013]
Logic Synthesis
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
Choose appropriate synthesis algorithmLSOracle [Neto et. al., ICCAD 2019]
• IT is the first work using DNN to guide mixed logic synthesis.
• LSOracle achieves the better area-delay trade-off than MIG or AIG
optimization.
Logic Synthesis
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
Extract features
Wire length
Performance prediction[Hyun et. al., DATE 2019]
• Wirelength Prediction using various ML models
• The average prediction error is 7% compared to actual wirelength
Physical Design
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
1. Choose appropriate placer: PADE [Ward et. al., DAC 2012] Extract datapath logic from random logic, and use datapath-aware placer for datapath logic
2. lithography-aware detailed routing
Lithographic hotspot prediction[Ding et. al., DAC 2011, Yang et. al., TCAD 2018, Ying et. al., TCAD 2019]
High bit-wise parallelism
Physical Design
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesisRouting congestion/Routability prediction[Alawieh et. al., ASPDAC 2020, Liang ISPD 2020]
wire length, area, timing prediction[Barboza et. al., DAC 2019, Cheng et. al., ISNE 2018]
3. Routing-aware placement
• Only output congestion number• Output congestion location (Often an Image-to-Image problem)
[Liang et. al., ISPD 2020]
Physical Design
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
4. ML-learned model that outputs placement decision [Mirhoseini et. al., 2020]
GCN to embed netlist and macro features
FC to embed meta dataGive out the placement decisionof one macro each time
Learned with Reinforcement Learning (RL)
Mask Optimization
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
1. Choose appropriate OPC method [Yang et. al., ASP-DAC 2020]• Inverse lithography technique (ILT)-based OPC• Model-based OPC
2. GAN-OPC [Yang et. al., DAC 2018](a) Train a generator to map the desired resist pattern to the mask(b) In the pretrain stage, an ILT-based litho-simulator is used as the discriminator
Mask Optimization
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
4. Lithography Simulation• Input: mask• Output: resist pattern
[Ye et. al, DAC 2019]
3. ML-aided SRAF insertion • [Xu et. al., ISPD 2016]• [Geng et. al., ASP-DAC 2019]
Testing
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis[Liu, et. al., ITC 2019]
1. Test set redundancy reduction
1 2 3 4
r1 r2 r3 r4
Uniqueness/testability of this test point?
Test points
Test results
[Pan, et. al., DATE 2018]
Qualified or not?
[Stratigopoulos et. al., TVLSI 2010]
Then use the accuracy as the rewardto evolve the test set
Get rid of redundant test points
Get rid of redundant test pointsby predicting from other results
Testing
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
1. Test set redundancy reduction
Active learning paradigm, choose the test point with largest variance
[Hu et. al., DAC 2018]
Testing
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
2. Test fidelity reduction (Analog/RF testing)
3. Observation point design
netlist
Use low-fidelity measurements to predict
Expensive specification testing
Not confident enough
• Module 1 unobservable• Module 2 uncontrollable
Observation point inserted
Where to insert least observation pointto maximize fault coverage?
GCN
[Ma et. al., DAC 2019]
[Stratigopoulos et. al., TCAD 2008]
Other related studies
DREAMPlace [Lin et. al., DAC 2019]Acceleration with auto-differentation deep learning engine
ML for SAT solver
• Restart strategy [Haim et. al., SAT 2009]• Branching/variable selection heuristics
[Moskewicz et. al., DAC 2001; Liang et. al., AAAI 2016]
Choose strategy/Tune parametersw= (x, y) is the cell locations to be optimized
Analogy between NN training and analytical placement
Analog Design
Application• Nature signal processing• High speed I/O• Drive electronics
Challenges• Analog design lacks hierarchy, hard to
decouple• Analog signals are more susceptible to
noise and PVT variations• Analog circuits have larger exploration
space in device sizing and topology selection
Analog Design
Architectural Design
SystemConcept
SimulationVerification
CellDesign
CellLayout
Architectural Layout
SystemLayout
SimulationVerification
SimulationVerification
SimulationVerification
SimulationVerification
Topology Selection
Device Sizing
[Rotman, ICASSP 2020]
[Wang, NIPS 2018]
• Performance prediction• Usually combine search method to optimize in the
design space• Decision making (topology decision / sizing decision)
• Use reinforcement learning (RL) to learn the controller• Topology selection from existing library
Menu
• Background• From EDA perspective: stage by stage• From ML perspective: role by role
What role does the ML model plays?
• Prediction (Most use cases are cross-stage prediction)• The ML model takes the description in one stage as the inputs, predict the outputs of following
stages• Many studies utilize the prediction model to optimize in the input space by various searching
methods• Decision making
• The ML model directly output the design/decision• Integrate with existing/traditional tools
• Use ML model to choose which traditional tool to use for which data/part of data• MISC
• Acceleration with DL engine• ML for SAT solver, and then SAT solver for EDA
Prediction (mostly cross-stage ones)
Challenges1. Accurate simulation of lower hierarchies is slow2. Design space is large
Layer-wise constrained optimizationArchitectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
Modeling oflower hierarchies
Static
Search/design space
Accurate simulation results
Estimated outputsof lower hierarchies
Minimize error
Prediction (mostly cross-stage ones)
Accurate Simulation
Search strategyModeling of
lower hierarchies
Search/design space expensive
Machine learning based modeling
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis Challenges1. Accurate simulation of lower hierarchies is slow2. Design space is large
Layer-wise constrained optimization
Active learning paradigm: Usually targeted at optimize the design in the input space
Decision Making
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
Mask synthesis: GAN-OPC [Yang et. al., DAC 2018]Train a generator to map the desired resist pattern to the mask
Mask synthesis: ML-aided SRAF insertion [Xu et. al., ISPD 2016]
Decision Making
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
Physical design: Macro placement with GCN+RL [Mirhoseini et. al., 2020]
Decision Making
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
Testing: Observation point insert decision [Ma et. al., DAC 2019]
netlist
Uniqueness?testability?
2
Testing: Test point uniqueness/testability prediction [Liu, et. al., ITC 2019]
Integrate with existing/traditional tools
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesis
Use ML model to choose which traditional tool to use for which data/part of data
Logic synthesis Physical designChoose appropriate placer: PADE
• Extract datapath logic: use SAPT datapath-aware placer• Random logic: use HPWL-based placer
Integrate with existing/traditional tools
Architectural Design
Logic Design
Logic Synthesis
Physical Design
Verification
Fabrication
Packaging & Testing
High-level synthesisMask synthesis Choose appropriate OPC method [Yang et. al., ASP-DAC 2020]• Inverse lithography technique (ILT)-based OPC• Model-based OPC
Use ML model to choose which traditional tool to use for which data/part of data
See https://github.com/thu-nics/awesome_ai4eda for references, and a more complete paper list on ML for EDA
Thank you for listening!
Contact us [email protected] (Yu Wang)[email protected] (Xuefei Ning)
