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M31 MIPI M-PHY v3.1 IP for Mobile Applications · 2017. 9. 12. · M31 MIPI M-PHY v3.1 IP for...
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M31 MIPI M-PHY v3.1 IP for Mobile Applications Flyer Version no. M31708 M31 MIPI M-PHY v3.1 IP Overview MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin counts combined with excellent power efficiency. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides a silicon-proven and low-power M-PHY in different process nodes. The M-PHY IP follows MIPI M-PHY v3.1 spec and supports full range of high-speed (HS) and low-speed (LS) data transfer. It is compliant to the RMMI interface which allows a seamless integrations with upside UNIPRO controllers. The M-PHY IP is designed for wide Type-I applications and is optimized for UFS (Universal Flash Storage). It not only supports a very short sync length for TX/RX sync length but also supports a unique reference-less mode during LS operation. Meanwhile, M31 also provides various lane configurations for the M-PHY IP to meet different requirements of transmitter and receiver bandwidth. Highlights Supports RMMI interface for Type-I applications like UNIPRO protocol (UFS, CSI-3, DSI-2), and LLI High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B, with scalable power consumptions Provides hibernate mode to meet mobile device requirement Burst mode CDR with short sync length ( < 16SI ) Low speed PWM Gears from G1 to G4 with ultra-low power consumptions Supports reference-less function during low-speed operation Common lane configuration facilitates the lane scalability Low latencies to switch to/from different power states Supports multiple signal amplitudes Supports strong BIST functions to ease the mass production tests Available in 16nm (2017 Q3), 28nm, 40nm, and 55nm process TX Eye Diagram (HS-G3B: 5.8Gbps @28nm)
Transcript of M31 MIPI M-PHY v3.1 IP for Mobile Applications · 2017. 9. 12. · M31 MIPI M-PHY v3.1 IP for...
M31 MIPI M-PHY v3.1 IP for Mobile Applications
Flyer Version no. M31708
M31 MIPI M-PHY v3.1 IP
Overview
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is
particularly developed for mobile applications to obtain low pin counts combined with
excellent power efficiency. As a MIPI Alliance contributor and leading Interface IP
provider, M31 provides a silicon-proven and low-power M-PHY in different process
nodes. The M-PHY IP follows MIPI M-PHY v3.1 spec and supports full range of
high-speed (HS) and low-speed (LS) data transfer. It is compliant to the RMMI
interface which allows a seamless integrations with upside UNIPRO controllers. The
M-PHY IP is designed for wide Type-I applications and is optimized for UFS (Universal
Flash Storage). It not only supports a very short sync length for TX/RX sync length but
also supports a unique reference-less mode during LS operation. Meanwhile, M31
also provides various lane configurations for the M-PHY IP to meet different
requirements of transmitter and receiver bandwidth.
Highlights
Supports RMMI interface for Type-I applications like UNIPRO protocol (UFS,
CSI-3, DSI-2), and LLI
High speed gears, HS-G1A/B, HS-G2A/B and HS-G3A/B, with scalable power
consumptions
Provides hibernate mode to meet mobile device requirement
Burst mode CDR with short sync length ( < 16SI )
Low speed PWM Gears from G1 to G4 with ultra-low power consumptions
Supports reference-less function during low-speed operation
Common lane configuration facilitates the lane scalability
Low latencies to switch to/from different power states
Supports multiple signal amplitudes
Supports strong BIST functions to ease the mass production tests
Available in 16nm (2017 Q3), 28nm, 40nm, and 55nm process
TX Eye Diagram(HS-G3B: 5.8Gbps @28nm)
like the M31 galaxy, inspiring unlimited imagination and bringing us a brighter future
Flyer Version no. M31708
Copyright© 2017 M31 Technology Corporation. All rights reserved. The information and material included in this flyer are
provided by M31 Technology Corporation as a service to its customer. The material is to be used for information purposes only.M31 Technology Corporation www.m31tech.com
M31 Headquarters | M31 Technology USA Inc. | M31 Technology (Shanghai), Inc.
[email protected] | [email protected]
RX Jitter Tolerance Test Result(HS-G3B: 5.8Gbps)
Jitte
r A
mp
litu
de
[m
UI]
Jitter Frequency [MHz]
0
150
300
450
600
750
900
1050
1200
1350
1500
1 10 100 1000
Max Generator Capability
Total Jitter inc. ISI
Set Total Jitter
UN
IPR
O C
on
tro
ller
Deserilizer
Clock
Multiplying
Units
SerializerTXDP
TXDM
RXDP
RXDM
REFCLK
(19.2/26/
38.4/52 MHz)
EQ/CDR
PWM RX
TX DriverTX Logic M
U
XPattern
Generator
8b/10bEncoder
RX [email protected] MHz
8b/10bDecoder
PatternChecker
RMMI Control/ Status
M_TX_Attribute
M_RX_Attribute
Block Diagram
