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MIPI DevCon 2016: Accelerating UFS and MIPI UniPro Interoperability Testing
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Transcript of MIPI DevCon 2016: Accelerating UFS and MIPI UniPro Interoperability Testing
Accelerating UFS and MIPI UniPro®
Interoperability Testing
Rui Terra, Synopsys, Inc.
Agenda • Mobile storage market landscape
• Achieving UFS device interoperability and compliance success
• Accelerating your UFS design development and verification
• Summary
Mobile Storage Market Landscape
Embedded
eMMCissuccessfullyusedinmainstreamlow-endmarkets
eMMCv5.xwithHigh-Speed(HS)400modeisseeingwideadopEon
UFSisseeninhigh-endsmartphonesduetopower,performanceadvantagesalongwithsecurityfeatures
Removable
SD(UHS-I)dominatesmainstreamandlow-endmarket
SD4.0(UHS-II):Higherspeed,backwardscompaEbletoSDCardbutrequiresPHY
NewlyannouncedUFSRemovableCardsexpectedtobewidelyadopted
Evolution of Embedded Solutions
Source:JEDECMobileForum,SamsungPresentaEon
2014-15
UFS3.0(tentaEve)
UFS2.x
2016-1720132012201120102009
Evolution of Removable Solutions • SD cards
• Used in variety of applications • UHS-II has low adoption due to increased complexity and niche use in high-
end cameras • New UFS cards
• Expected to be widely adopted due to increased performance and capacity • Expected to be available and widely used by early 2017
• Transition from SD card to UFS card enabled by combo socket or card extension use model
HostCPU
e-
Ini.alMarketComboSocketDesign
UFSpadsposiEonedtoallowforComboSocketimplementaEons
HostCPU
e-
Poten.alMarketEvolu.on
HostCPU
e-
HostCPU
e-
Agenda • Mobile storage market landscape
• Achieving UFS device interoperability and compliance success
• Accelerating your UFS design development and verification
• Summary
Interoperability Testing and Certification is Necessary
ReleaseoftheCTMisthefirststeptowardsafullindustrycer.fica.onandlogoprogramforUFS.Thisprogramwillbecomecri.callyimportantasUFScardsentertheretailmarketwhereconsumersexpectthataUFScardwillautomaEcallybecompa.blewiththeirelectronicdevice.
Bring-Up and Interoperability Tests • Link Start-up Sequence • Power Mode Change • DME access • Generate UPIU • Access to the CPort directly
• (send/receive data through CPort) • Perform specific SCSI commands
• (read/write) • Generate pattern transfers
• Small/Large amplitude • PWM/HS • AUTO-MODE/NON-AUTO-MODE
• Hibernation entry and exit
UFS
SCSIcommands
CPort
UniPro
M-PHY
UPIU
UFS
Link Startup Sequence • An UniPro sequence to establish initial link
communication between UFS host and device • Extensive procedure • Includes multiple bidirectional handshakes
• After Link Startup Sequence the host and device are ready to communicate
Link Startup Sequence
10
DMEReset
DMEEnable
LinkStartup.req
DMEReset
DMEEnable
LinkStartup.indTRGPa\ern
TRGPa\ernTRGPa\ern
DEVICEHOST
CAPCAP
LinkStartup.cnfLinkStartup.cnf
Hibern8Exit
Hibern8Exit LinkStartup.req
LINERESET
LINERESET
Link Startup Sequence • Extensive complex procedure that can fail for multiple
reasons • Failing in the sequence
• Hibernate exit • LINE RESET • Out of order TRG_UPRx patterns • Capability Exchange failures • Incorrect timeout timers
• Failing due to prototyping • Integration • Interface Timing
11
UFS Compliance Test Matrix (CTM) • UFSA CTM
• Is a reduced matrix • Provides a clear definition of
the tests that are needed to demonstrate compliance with the UFS specification
• References the necessary procedures required to access UFS compliance
• Therefore ensuring interoperability with other UFS designs
ExampleofComplianceTestMatrix
CTM Hibernate Tests with UFS Prototyping System – Definition
1. Enable communication between Tester and DUT 2. Change default values of some attributes which need to be retained
during hibernate 3. Get the value of all the attributes that need to be retained during
hibernate 4. The Tester sends a DME_HIBERNATE_ENTER.req() request 5. Analyze the PACP exchange 6. Check on Tester and DUT if all connected lanes are in
HIBERNATE_STATE 7. Tester generates DME_Hibernate_EXIT.req() 8. Verify that all required DUT Attributes have been retained by
reading the Attributes with DME_PEER_GET.req() and verifying them with the values that have been read before entering Hibernate
This procedure is then executed in multiple power modes
Test Sec.on1,Group3:Hibernate Status
1.3.1 Hibernate INF
NotinH8state
H8ExitUnsuccessful
Wronga\ributevalue
ExampleFailurePoints
Immediate Productivity for HW and SW Engineers: IP Prototyping Kits
ReferenceSWforIP
RunsLinuxOS
FPGAreadyIPreference
design
InterfacePHYIP
SoCintegraEonlogic
Immediate Productivity for HW and SW Engineers: IP Prototyping Kits
• Included: • M-PHY card (2 TX + 2 RX) • HAPS FPGA Prototyping platform • All the necessary interface cables • IP Reference Design • Reference driver • SW Application – commands to enable
compliance ready devices
• Multiple interfaces • Supports 1 and 2 lanes RX/TX • Supports up to Gear 3 Rate B
CTM Tests with UFS Prototyping System – Implementation
1. Enable communication between Tester and DUT 2. Change default values of some attributes which need to be retained
during hibernate 3. Get the value of all the attributes that need to be retained during
hibernate 4. The Tester sends a DME_HIBERNATE_ENTER.req() request 5. Analyze the PACP exchange 6. Check on Tester and DUT if all connected lanes are in
HIBERNATE_STATE 7. Tester generates DME_Hibernate_EXIT.req() 8. Verify that all required DUT Attributes have been retained by
reading the Attributes with DME_PEER_GET.req() and verifying them with the values that have been read before entering Hibernate
• dme_reset
• dme_enable
• dme_linkstartup
• dme_get <attr_id>
• dme_peer_get <attr_id>
• dme_set <attr_id> <attr_value>
• dme_peer_set <attr_id> <attr_value>
• dme_hibernate_enter
• dme_hibernate_exit
Test Sec.on1,Group3:Hibernate Status
1.3.1 Hibernate INF
IPPrototypingKitSoLwareCommands
CTM Tests with UFS Prototyping System – UFS_UPIU_01 Testing
CTM Tests with UFS Prototyping System - Implementation
• #./dwc_ufs_testdm_testnopout31• #./dwc_ufs_testget_ucd31===================nopin_UPIU[31]======================trans_type:0x20flags:0x00task_tag:0x20tot_ehs_len:0x00data_seg_len:0x0000
DW[00]:20000020DW[01]:00000000DW[02]:00000000DW[03]:00000000DW[04]:00000000DW[05]:00000000DW[06]:00000000DW[07]:00000000
• Transaction type
• Flags
• Response
• Device information
• Data Segment Length
SuccessfulUFS_UPUI_01TestDuetoUsingIPPrototypingKitReferenceDesign
SK Hynix: First-Silicon Success • Completed successful
interoperability by using JEDEC- and MIPI-compliant IP
• Integrated IP in two weeks & accelerated design schedule by six months
• Met stringent power & performance requirements with Synopsys’ Mobile Solutions IP
“Weneededtoquicklydeliverahigh-performanceandpower-efficientUFS2.0soluEonformobiledevices.WewereabletointegratetheIPintwoweeks,speedourdesignschedulebysixmonthsandachievevolumeproducEon.”
—J.W.Park,SeniorEngineer,SKHynix
Agenda • Mobile storage market landscape
• Achieving UFS device interoperability and compliance success
• Accelerating your UFS design development and verification
• Summary
APB
PCIe AXI
PCS
P
H
Y
PIPE
APB
CLOCK RESET
RAM
APB(Common Interface)+ Bridge
PCIe Subsystem
APB Interconnect
S/S Registers
DWC PCIe PHY DWC PCIe Controller IP
External
RAM RAM
RAM
Custom IP Blocks (OPTIONAL)
IP Prototyping Schedule Can Be Lengthy
Create IP Reference
Design
Validate Reference Design
Explore IP Configuration
Firmware, Driver, Bootcode
Development
Create Board & PHY Daughter
Card
Accelerate UFS Design Development and Verification
Explore IP
Firmware, driver, bootcode
development IP Prototyping Kits’ Schedule Benefit
Eliminate Shift Left! Eliminate 10 to 12 weeks
Create IP Reference
Design
Validate Reference
Design
Explore IP Configuration
Firmware, Driver, Bootcode
Development
Create Board & PHY Daughter
Card
Interoperability & Compliance Testing
Move on to
Accelerate Development with Pre-Verified UFS Reference Design
• Learn about protocol • Explore IP configurations • Test different products for
interoperability • Debug system level logic
• Learn about protocol • Develop firmware, driver,
bootcode, application • Test different products and
connectivity
HardwareDesigners SoLwareDesigners
ReferenceDesign! DocumentaEon! PrototypeverilogdesignsourceRTL! CoreconfiguraEonandbuildenvironment! SimulaEontestbench! ProtoCompiler-DXsynthesisscripts! Pre-builtFPGAimage
SoLwareSourcecode! ReferenceLinuxOSDriver! ApplicaEonexample! CompilaEonscripts
Example of Pre-Verified UFS Reference Design
Agenda • Mobile storage market landscape
• Achieving UFS device interoperability and compliance success
• Accelerating your UFS design development and verification
• Summary
Proven Interoperability Reduces Risk
Synopsys is an active participant in JEDEC & UFSA Working Groups
• JEDEC JC64
• UFSA Compliance & Marketing
SynopsysM-PHY
SynopsysUFS+UniPro
VisittheSynopsysBoothtoSeeOurDemoToday!
Summary • UFS is growing
• First UFS phone hit the market in 2015 • First UFS cards announced in 2016
• Developing devices with seamless interoperability and compliance is difficult • Takes a long time to have a functional setup (using
a market controller) • Extensive and difficult processes from scratch
• DesignWare UFS Host IP Prototyping Kits accelerate product development • Complete reference design working out of the box • Fast Iteration Flow with easily modified design/
build scripts • Explore best configuration with real-world I/O • Reference SW provides early SW bring-up, debug
and test with out-of-the-box support for Linux
Explore IP
Firmware, driver, bootcode
development
Interoperability & Compliance Testing
Move on to
Thank You!
Synopsys’broadporiolioofDesignWareMIPIIPsoluEonssynopsys.com/mipi