M. S. Engineering College, Bangalore 1 Final Project Presentation Design and ASIC Implementation of...

M. S. Engineering College, Bangalore 1

Final Project Presentation

Design and ASIC Implementation of Low-Power

Viterbi Decoder for WLAN Applications

Academic Guide 1: Academic Guide 2:

Student Name USN


Aim and Objectives of the Project

AIM :

To design and implement a low power Viterbi decoder for WLAN applications in ASIC using 130nm CMOS technology

Objectives•To review the literature on low power Viterbi decoder, WLAN and low power ASIC design algorithms and architecture.

•To arrive at design specifications of Viterbi decoder based on applications and to identify the suitable architecture.

•To develop a software reference model of the Viterbi decoder based on the derived specification

•To develop a hardware module of the Viterbi decoder based on the derived specification.

•To implement the Viterbi decoder using ASIC flow.

•To verify the completed design to meet the specifications.


Introduction

• Problem of digital communication

– Transmit much data via a noisy channel

– Detect and correct errors

• WLANs are flexible data communication systems implemented as the extensions or alternative to the wired LAN.

• The 802.11a uses OFDM technique .

802.11a Receiver Block Diagram[1]


Introduction

•A convolutional coding is a class of error correcting codes which are widely used as channel coder in today’s digital communication systems.•Viterbi Decoder is commonly used in decoding convolutional codes for wireless communication.•VDs are widely used as forward error correction (FEC) blocks in many digital communication applications such as mobile phones, video and audio broadcasting receiver, modems and WLANs.•Viterbi algorithm was devised by Andrew J. Viterbi in 1967.

N-state TrellisConvolutional Encoder [9]


Literature Review (Summary)

• Basic Architecture of the VD has 3 major building blocks: BMU (branch metric Unit), ACSU (add-compare-select Unit), (SMU) Survivor Memory Unit

• 64 add-compare-select (ACS) operations

• There are no comparisons and selections to be made for the first 6 stages.

• Trace back length => 4 or 5 x K [4]

• The free distance Dfree = 10 for K=7

• ACS unit consumes most power and area [1].

• There are two ways of implementing the SMU: Register exchange and trace back method.

• Traceback method consumes less area and power but has high design complexity

Basic Architecture of Viterbi decoder [1]


Literature Review

Specifications

Parameter Symbol Value

Constraint Length

K 7

Code Rate R 1/2

Generator Polynomials

G G0 = 1718,

G1 = 1338

Traceback Length

TL 32

VD Decision Type

-- Hard

SMU Type -- Trace back

Specifications of the Viterbi decoder are as given below:


Matlab Simulation Results

Matlab Simulation results obtained are as shown below:` Input Data: 0001110011100010010000100001111010010101100000000

Decoded DataOriginal Data

Encoded data with noise


Design Procedure

Block Diagram of Architecture of Viterbi Decoder

BMU ACS

CTRL

CLOCK

TBU

MMURAM

Survivor

Control & Clock Signals Bus

Distance LowestState

Survivors

Add

ress

Data

Address

D

ata

RAMMetric

Pat

hMet

ric

Add

ress

Code

Reset

Active

Clock

Decoded output


Design Procedure continued . .

• The BMU calculates the distance between the received symbols and code words on the branches.

• The ACS units perform comparison among candidate paths to determine survivors and compute the corresponding path metrics.

Adder

Adder

C omp

Adder

Adder

C omp

(sa,S0)

BM i

PM i- 1

BM i

BM i

PM i- 1

BM i

(sa)

(sb,S1)

(sb)

(sa,S1)

(sb,S0)

M i

M i

(S0)

(S1)

Conventional ACSU architecture Low power ACSU(CSA) architecture



•The memory management unit (MMU) governs the operations of SMU

•The clock and control unit are used to generate the clock and control signal respectively•The trace back algorithm implemented could be described as follows :

1. At time t when TB_EN=1 get the lowest state from ACS.2. From the survivor memory, get survivor value of those node.3. Concatenate the lowest state and survivor bit and shift.4. Traceback the shortest path to obtain the decoded output

MMU Control Signals



Design of Hardware Model

• Hardware modeling of Viterbi Decoder is done in Verilog HDL using ModelSim.

• Design of sub-blocks – ACS unit, Branch metric unit and Survivor Memory unit.

• Design of Controller unit and Clock unit to provide control signals and clock signals for all the above sub-blocks.

• Integration of all the above sub-blocks to complete the Viterbi decoder block.

• Apart from the decoder design, a convolutional encoder was also designed for testing the viterbi decoder for different test cases


Hardware Design Flow Chart

Synthesis, Optimization

Static Time Analysis

Floor planning and Power planning

Place and Route

Physical verification

GDSII Generation

Scan insertion

Formality

Timing metNo Yes

HDL coding



• Schematic of Viterbi Decoder obtained in DC

Decoded output

Code

ActiveReset

Clock

Control Unit

Clock Gen Unit

ACSUBMU TBU MMU

RAM



• Test Bench Setup

ViterbiDecoder

Convolutional Encoder

Testbench

Input Data Code Word

Decoded Output

Input Data : 0001110011100010010000100001111010010101100000000 Code word : 1110110001111010010101110110110001010000011000011100010010010000 0010110000100111110010101001101011011001011000111001000110110000


Simulation Results continued . .

Encoder O/P & Decoder output

VD O/P with no error at input

Input Data: 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000

Input Data : 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000 Encoder out : 1110110001111010010101110110110001010000011000011100010010010000 0010110000100111110010101001101011011001011000111001000110110000Decoded Output : 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000



VD O/P with 4-bit error (near-by error) at input

VD O/P with 4-bit error (Far-away error) at input

Input Data : 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000 Code word : 1110110001111010010101110110111000000010011000011100010010010000 0010110000100111110010101001101011011001011000111001000110110000Decoded Output : 00011 10011 10001 00101 00100 00111 10100 10101 10000 0000

Code word : 1110110001111010010101110110110000000000011000011101010010010000 0010110000100110110010101001101011011001011010111001000110110000



VD O/P with 6-bit error at input

Input Data : 00011 10011 10001 00100 00100 00111 10100 10101 10000 0000Code word : 1110110001111010010101110110110001010000011000011100010010010000 0010110000100110110010001000100011010001011000011101000110110000

Decoded Output : 00011 10011 10001 00100 00110 01111 01001 01011 00000 0000


Design Synthesis

Parameter Value

Technology 130 nm

Libraries MVt TSMC CMOS

No. of Cells 3537

No. of Ports 7

Area 163974µm2

Clock period 20ns

Total Power 2.363mW

The synthesis results are as shown below:


Physical Design Results

Total number of cell instances: 9999Total number of nets: 12103Total number of ports: 9

Core Width = 503.7 mm2

Core Height = 503.3 mm2

CTSPlacement


Routing IRDrop

Physical Design Results

Power ReportTotal switching power = 5.677 mW Total internal power = 3.40231 mWTotal short-circuit power = 20.2082 mWTotal leakage power = 0.4688 mW Total power = 29.7567 mW

IR DropMax voltage drop (mV) = 2.896 (VDD)


My contribution

• A convolutional encoder was designed based on the 802.11a specification

• Reduced the total no ACS units from 64 to 4 ACS, thereby power reduction was achieved.

• An ACS unit was designed with a parallel architecture.

• Clock gating was used for reducing the power.


Conclusion

• Usage of CSA architecture lowers down hardware complexity as well as power dissipation to 29.75 mW which is a reduction of 44% when compared to the reference design

• Reducing the number of ACS units to 4 from that used in other Viterbi Decoders reduces the area by 94%

• The width of the RAM influences the Data rate, the current width of 8 results in data rate of 1.56Mbps

• Changing the RAM size makes the design compatible for any constraint length with very few minor modifications

• The design not only considers the error correction capability, but also provides a power-efficient solution


Suggestions for future work

• Design of soft decision Viterbi decoder

• Design of a puncturing unit to achieve higher coding rates

• Implementation of parallel processing blocks to increase the throughput of the system


Literature

• Journals

1. C. C. Lin, Y. H. Shih, H. C. Chang and C. Y. Lee, “Design of a power reduction Viterbi decoder for WLAN application”, IEEE Trans. on Circuits and Systems-I, vol.52, no.6, pp.1148–1156, June 2005

2. D. A. El-dib and M. I. Elmasry, “Modified register exchange Viterbi decoder for low-power wireless communications”, IEEE Trans. Circuits Systems-I, vol.51, no.2, pp.371–378, February 2004


Literature (cont..)

• Conference Papers

3. Maharatna, K, Troya, A, Kristic, M and Grass E, “On the implementation of a Low-Power IEEE 802.11a compliant Viterbi Decoder”, in 19th VLSI Design Conference, Hyderabad, India, pp.613-618, April 2006

4. C.-C. Lin, C.-C. Wu, and C.-Y. Lee, “A low power and high speed Viterbi Decoder chip for WLAN applications”, in Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC'03), Lissabon, Portugal, pp.723–726, September 2003


Literature (cont..)

• Books

4. Bernard Sklar, “Digital Communications - Fundamentals and Applications”, 2nd Edition, Pearson Education, ISBN:81-7808-

373-6, 2004

5. Simon Haykin “Communication Systems”, John Wiley & Sons, 4th Edition, ISBN: 9971-51-305-6, 2004

6. Samir Palnitkar, “Verilog HDL – A Guide to Design and Synthesis”, Prentice Hall, ISBN: 0-13-044911-5, 2003


Literature (cont..)

• Websites ( accessed as on Aug. 2008)

7. http://home.netcom.com/~chip.f/viterbi/tutorial.html

(A Tutorial on Convolutional Coding with Viterbi Decoding)

8. Synopsys Online Documentation


Literature (cont..)

9. IEEE 802.11a WLAN physical layer specifications document

10. H.L. LOU, “Implementing the Viterbi Algorithm,” IEEE Signal processing Magazine, pp.42-52, Sept. 1995


Thank You

M. S. Engineering College, Bangalore 1 Final Project Presentation Design and ASIC Implementation of...

Documents

Transcript of M. S. Engineering College, Bangalore 1 Final Project Presentation Design and ASIC Implementation of...