Scientific Committee

Gennadi Bersuker, Sematech, USA Wen-Ting Chu, TSMC, Taiwan Pei-Ying Du, Macronix, Taiwan

Fukuzumi Yoshiaki, Toshiba, Japan Damien Deleruyelle, Aix-Marseille University

Dieny Bernard, CEA-Spintec, France Hyeonsoo Kim, SK-Hynix, Korea

Isamu Asano, Micron, Japan H.-S. Philip Wong, Stanford University, USA

Alessandro Baiano, NXP Semiconductors, Netherlands Mark Randolph, Spansion, USA

Gabriel Molas, CEA LETI, France Chandu Gorla, Sandisk, USA Craig Swift, Freescale, USA

Takashi Kobayashi, Hitachi, Japan Gill Lee, Applied Materials, USA

Gutman Micha, TowerJazz, Israel Akira Goda, Micron, USA

Knobloch Klaus, Infineon, Germany Ken Takeuchi, Chuo University, Japan Geert Van den bosch, IMEC, Belgium

Advisory Committee

Jungdal Choi, Korea Pranav Kalavade, Intel, USA

Tamer San, Texas Instrument, USA

Sunday, 5/17 Registration 8:00AM – 4:30PM Tutorial on System– 1st part 9:00AM – 11:50PM Lunch Break (provided) 11:50PM – 2:00PM Tutorial on 3D-Memory – 2nd part 2:00PM – 4:30PM

Monday, 5/18 Registration 7:00AM – 6:00PM Opening remarks 8:00AM – 8:20AM Session #1 8:20AM – 11:50AM Committee Luncheon 12:00PM – 2:00PM Lunch (on your own) Session #2 2:00PM – 3:40PM Panel discussion 4 :00PM – 5:30PM Poster Session 6:00PM – 8:30PM Reception 6:00PM – 8:30PM

Tuesday, 5/19 Registration 7:00AM – 5:00PM Session #3 8:00AM – 9:40AM Session #4 10:05AM –12:10PM Lunch Break (on your own) 12:10PM – 2:00PM Session #5 2:00PM – 3:40PM Session #6 4:10PM – 5:00PM Banquet (provided) 7:00PM – 9:00PM

Wednesday, 5/20 Registration 7:00AM – 2:00PM Session #7 8:00AM – 9:40AM Session #8 10:05AM – 11:45AM Lunch (provided) 11:45AM – 2:00PM Session #9 2:00PM – 3:40PM Closing Remarks 4:05PM – 4:45PM

7th International Memory Workshop

May 17th – 20th 2015

Hyatt Regency Hotel, Monterey, CA

Poster Session Monday May 18th, 2015 6:00 PM – 8:30 PM POSTER PAPERS 1)  L. Crespi, Politecnico di Milano, “Modeling of Atomic Migration Phenomena in Phase

Change Memory Devices” 2)  Z. Jiang, Stanford University, “Performance Prediction of Large-Scale 1S1R Resistive

Memory Array Using Machine Learning” 3)  N. D. Lu, Chinese Academy of Sciences, “A Novel Approach to Identify the Carrier

Transport Path and Its Correlation to the Current Variation in RRAM”

4)  J. Bartoli, Aix-Marseille Université /STMicroelectronics, “Optimization of the ATW non-volatile memory for connected smart objects"

5)  Roger Lo, Macronix InternationalCo.,Ltd / National Chiao Tung University, “A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance”

6)  B. L. Ji , SUNY Polytechnic Institute/SEMATECH, “In-Line-Test of Variability and Bit-Error-Rate of HfOx-Based Resistive Memory”

7)  Nhan Do, Silicon Storage Technology (Microchip), “A 55 nm Logic-Process-Compatible, Split-Gate Flash Memory Array Fully Demonstrated at Automotive Temperature with High Access Speed and Reliability”

8)  Carmine Miccoli, Micron, “Characterization and Modeling of Advanced Placement Algorithms for NAND Flash Arrays ”

9)  Kwang-Il. Choi, SK-Hynix, “Improved Lateral Coupling Cell for a Standard Logic Process eNVM Application”

10) Hao Wang, RPI, “Efficiently Realizing Weak Cell Aware DRAM Error Tolerance for Sub-20nm Technology Nodes ”

11) F. Merrikh-Bayat ,UCSB, “Memory Technologies for Neural Networks” 12) Kosuke Suzuki, Fujitsu Laboratories Ltd./UCSD, “A Survey of Trends in Non-Volatile

Memory Technologies: 2000–2014”

Finance Chair Randy Koval Intel USA

Technical Chair Jing Li UW-Madison USA

General Chair Sung-Yong Chung SK-Hynix Korea

Sunday May 17th, 2015 Tutorial Registration on site: 8:00AM – 4:30PM

Tutorial on Technology-System Interactions 9:00AM – 11:50AM Session Chair: Pei-Ying Du (Macronix) 9:00AM Introduction Session chair 9:10AM Introduction to the Reliability of flash based Todd Marquart, Micron Fellow solid-state-Drives

10:40AM Break (Refreshments Provided)

11:00AM Database Technologies for Non-Volatile RAM Sang-Won Lee, SKKU

11:50AM Lunch break (Provided) Tutorial on 3D Memory 2:00PM – 4:30PM Session Chair: Pei-Ying Du (Macronix) 2:00PM Three Dimensional Dynamic Random Access Memory Toshiaki Kirihata, IBM 2:50PM Current Progress and Challenge in ReRAM Zhiqiang Wei, Panasonic 3:40PM 3D Vertical NAND Flash Revolutionary or Evolutionary? Betty Prince, Memory Strategies International

Publicity Chair Agostino Pirovano Micron Italy

Conference location: Hyatt Regency Hotel, Monterey, CA

Hyatt Regency Monterey Hotel & Spa on Del Monte Golf Course 1 Old Golf Course Road, Monterey, California, USA 93940-4908 Tel: +1 831 372 1234 Fax: +1 831 375 3960

Monday May 18th, 2015 Registration 7:00 AM - 6:00 PM

Session #1 8:00 AM – 12:00 PM Invited Talk Chairs: Sung-Yong Chung, SK-Hynix, Korea

Jing Li, UW-Madison, USA 8:00 AM Sung-Yong Chung, Opening Remarks 8:20 AM Sung-Kye Park, SK-Hynix, “Technology scaling challenges and

Future prospects of DRAM and NAND Flash memory” 8:50 AM Will Akin, Micron, “Understanding NAND’s intrinsic characteristics

critical role in Solid State Drive (SSD) design: A key enabler for Enterprise Data Center applications”

9:20 AM Dale Juenemann and Prasad Allur, Intel, “Accelerating NVM adoption in PCs: A system study to identify the enablers”

9:50 AM Break (Refreshments Provided) 10:20 AM Barbara desalvo, CEA-LETI, “From memory in our brain to

future Silicon-based memory technologies” 10:50 AM Thomas Jew, Freescale, "Embedded Microcontroller Memories:

Application Memory Usage” 11:20 AM Shinobu Fujita, Toshiba, ”Technology trends and near-future

applications of embedded STT-MRAM” 11:50 PM Lunch Break (on your own) 12:00 PM Committee Luncheon Session #2 2:00 PM – 3:40 PM RRAM-1 Chair: Knobloch Klaus, Infineon, Germany Steve Heinrich-Barna, Texas Instrument, USA

2:00 PM B. Govoreanu, IMEC, “Thin-Silicon Injector (TSI): an All-Silicon

Engineered Barrier, Highly Nonlinear Selector for High Density Resistive RAM Applications”

2:25 PM A, Schönhals, RWTH Aachen University, " Critical ReRAM Stack Parameters Controlling Complimentary versus Bipolar Resistive Switching"

2:50 PM S. Lee, POSTECH, “Comprehensive Methodology for ReRAM and Selector Design Guideline of Cross-point Array”

3:15 PM X. Huang, Tsinghua University, “Optimization of TiN/TaOx/HfO2/TiN RRAM Arrays for Improved Switching and Data Retention”

3:40 PM Break (Refreshments Provided) Panel discussion 4:00 PM – 5:30 PM Future of Memory: Application-driven or Technology-driven, which will dominate in the new era of computing? Panelists: Will Akin, Micron Thomas Coughlin, Coughlin Associates Barbara De Salvo, CEA-LETI Dale Juenemann, Intel Ming Liu, IMECAS Joseph Wang, Qualcomm Moderator : Jing Li, UW-Madison, USA Poster Session : 6:00 PM – 8:30 PM Chair: Gill Lee, Applied Materials, USA 6:00 PM Poster Introduction (See the front page for the list of poster papers) Reception 6:00 PM - 8:30 PM Sponsor: Applied Materials, Inc., USA

Tuesday May 19th, 2015 Registration 7:00 AM - 5:00 PM

Session #3 8:00 AM – 9:40 AM RRAM-2 Chairs: Steve Heinrich-Barna, Texas Instrument, USA 8:00 AM M. Kudo, Hokkaido University, “Visualization of Conductive Filament during Write

and Erase Cycles on Nanometer-scale ReRAM Achieved by in-situ TEM” 8:25 AM J. Baek, SKKU, “A Reliable Cross-Point MLC ReRAM with Sneak Current

Compensation” 8:50 AM A. Grossi, Universita` di Ferrara, “Relationship among current fluctuations during

forming, cell-to-cell variability and reliability in RRAM arrays” 9:15 AM J. Tranchant , Université de Nantes, “From resistive switching mechanisms in

AM4Q8 Mott insulators to Mott memories” 9:40 AM Break (Refreshments Provided)

Session #4 10:05 AM – 12:10 AM NAND Chairs: Ken Takeuchi , Chuo University, Japan Geert Van den bosch, IMEC, Belgium 10:05 AM L. Breuil , IMEC, “Optimization of Ru based Hybrid Floating Gate For Planar

NAND Flash” 10:30 AM W. Kueber, Micron, “A Highly Reliable and Cost Effective 16nm Planar NAND Cell

Technology” 10:55 AM E. Capogreco, IMEC, “Integration and electrical evaluation of epitaxially grown Si

and SiGe channels for vertical NAND Memory applications” 11:20 AM D. Oh, SK-Hynix, “TCAD Simulation of Data Retention Characteristics of Charge

Trap Device for 3-D NAND Flash Memory” 11:45AM P. Khayat, Micron, “Performance Characterization of LDPC Codes for Large-

Volume NAND Flash Data” 12:10 PM Lunch Break (on your own)

Session #5 2:00 PM – 3:40 PM DRAM/Oxide RAM/ZRAM/SRAM Chairs: Fukuzumi Yoshiaki, Toshiba, Japan

2:00 PM K. Min, SK Hynix, “Study on the Sub-threshold Margin Characteristics of the

Extremely Scaled 3-D DRAM Cell Transistors” 2:25 PM T. Matsuzaki, Semiconductor Energy Laboratory Co. Ltd., “A 16-Level-Cell

Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET” 2:50 PM S. Dutta, IIT Bombay, “A Bulk Planar SiGe Quantum-Well based ZRAM with Low

VT Variability” 3:15 PM Y. Ma, Intellectual Ventures, “Novel Multi-bit Non-Volatile SRAM Cells For

Runtime Reconfigurable Computing” 3:40 PM Break (Refreshments Provided) Session #6 4:10 PM – 5:00 PM MRAM/FRAM Chairs: Scott Summerfelt, Texas Instrument, USA Knobloch Klaus, Infineon, Germany 4:10 PM H. Saito, FUJITSU, “A Triple Protection Structured COB FRAM with 1.2-V

Operation and 10^17 Endurance” 4:35 PM H. Koike, Tohoku University, “1T1MTJ STT-MRAM Cell Array Design with an

Adaptive Reference Voltage Generator for Improving Device Variation Tolerance” 5:00PM W. Kang, Beihang University, “Dynamic Reference Sensing Scheme for Deeply

Scaled STT-MRAM”

Banquet 7:00 PM - 9:00 PM (provided) Special Event: IEEE Reynold B. Johnson Information Storage Systems Award

Wednesday May 20th, 2015 Registration 7:00 AM - 2:00 PM

Session #7 8:00 AM – 9:40 AM Solid State Disk Chairs: Akira Goda, Micron, USA 8:00 AM T. Iwasaki , Chuo University, “Machine Learning Prediction for 13× Endurance

Enhancement in ReRAM SSD System” 8:25AM C. Matsui, Chuo University, “3x Faster Speed Solid-State Drive with a Write

Order based Garbage Collection Scheme” 8:50 AM S. Okamoto, Chuo University, “Application Driven SCM&NAND Flash Hybrid

SSD Design for Data-Centric Computing System” 9:15 AM Lorenzo Zuolo, Universtià degli Studi di Ferrara, “LDPC Soft Decoding with

Reduced Power and Latency in 1X-2X NAND Flash-Based Solid State Drives”

9:40 AM Break (Refreshments Provided) Session #8 10:05 AM – 11:45AM eNVM/New App. Chairs: Akira Goda, Micron, USA Craig Swift, Freescale, USA 10:05 AM L. Luo, GLOBALFOUNDRIES, “Functionality Demonstration of a High-Density

1.1V Self-Aligned Split-Gate NVM Cell Embedded Into LP 40 nm CMOS for Automotive and Smart Card Applications”

10:30 AM S. Park, SK-Hynix, “Single-Poly Embedded NVM Solution For Analog Trimming And Code Storage Applications”

10:55 AM A. Baiano, NXP, “Junction optimization for embedded 40nm FN/FN flash memory”

11:20 AM P. Amato, Micron, “An Analytical Model of e•MMC Key Performance Indicators”

11:45 AM Lunch (provided)

Session #9 2:00 PM – 3:40 PM CBRAM/PCM Chairs: Takashi Kobayashi, Hitachi, Japan 2:00 PM W.S.Khwa, Macronix “A Procedure to Reduce Cell Variation in Phase Change

Memory for Improving Multi-Level-Cell Performances” 2:25 PM N. Ciocchin, Politecnico di Milano, Universal thermoelectric characteristic in

phase change memories 2:50 PM M. Barci, CEA LETI, “Bilayer Metal-Oxide CBRAM technology for improved

window margin and reliability” 3:15 PM A. Belmonte, IMEC, “Fast and Stable sub-10µA Pulse Operation in W/SiO2/

Ta/Cu 90nm 1T1R CBRAM devices” 3:40 PM Break (Refreshments Provided) 4:05 PM – 4:45 PM Closing Remarks & Adjourn 2: