Low-Power Multipliers with Data Wordlength Reduction Kyungtae Han ([email protected]) Brian L....
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Low-Power Multipliers with Data Wordlength Reduction Kyungtae Han ([email protected]) Brian L. Evans ([email protected]) Earl E. Swartzlander, Jr. ([email protected]) Dept. of Electrical and Computer Engineering The University of Texas at Austin Austin, TX 78712 USA Asilomar Conference on Signals, Systems & Computers November 2nd, 2005
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Transcript of Low-Power Multipliers with Data Wordlength Reduction Kyungtae Han ([email protected]) Brian L....
Low-Power Multipliers withData Wordlength Reduction
Kyungtae Han ([email protected]) Brian L. Evans ([email protected])
Earl E. Swartzlander, Jr. ([email protected])
Dept. of Electrical and Computer EngineeringThe University of Texas at Austin
Austin, TX 78712 USA
Asilomar Conference on Signals, Systems & Computers November 2nd, 2005
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Outline
• Introduction
• Wordlength reduction
• Power consumption
• Analysis in switching expectation
• FPGA dynamic power estimation
• Conclusion
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Introduction
• Minimize power dissipation due to limited battery power and cooling system
• Multipliers often a major source of power consumption in typical DSP applications
• Multi-precision multipliers can select smaller multipliers (8, 16 or 24 bits) to reduce power consumption
• Wordlength reduction to select any word size [Han, Evans, and Swartzlander 2004]
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Wordlength Reduction in Multiplication
• Input data wordlength reduction– Smaller bits enough to
represent, e.g. π x π ≈ 9
• Truncation
• Signed right shift– Move toward the least
significant bit (LSB)
– Signed bit extended for arithmetic right shift
0001 0010 0011 01001101 1100 1010 1001
(a) Original Multiplication
0001 0010 0000 00001101 1100 0000 0000
(b) Reduction by Truncation
0000 0000 0001 00101111 1111 1101 1100
(c) Reduction by Signed Right Shift
Sign bit
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Power Reduction via Wordlength Reduction
• Power dissipation – Switching power consumption– Static power consumption
• Switching power consumption– Switching activity parameter, α– Reduce α by wordlength
reduction
clkddLswitching fVCP 2
What is relationship between wordlength and switching parameter, α, in power consumption?
CL Load capacitance
Vdd Operating voltage
fclk Operating frequency
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Switching Activity in Multipliers
• Logic delay and propagation cause glitches• Proposed analytical method
– Hard to estimate glitches in closed form– Analyze switching activity w/r to input data wordlength– Does not consider multiplier architecture
• Simulation method– Count all switching activities
(transition counts in logic)– Power estimation (Xilinx XPower)– Considers multiplier architecture
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Analytical Method• Consider stream of data for one of the multiplicands• Compare two adjacent numbers in stream after
reduction• Expectation of bit
switching, x, withprobability Px
– L-bit input data– Truncate input data
to M bits (N bits areremoved)
– N-bit signed rightshift in L-bit input(Y is sign bit)
2)(
LXEL
22)(
MNLXEtr
2
)1|(2
1)0|(
2
1)(
L
YXEYXEXErs
L
xX xPxXE
0
)()(
S … …
L bits
M bits N bits
S … …
S S … SS …
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Analytical Method
)1|(2
1)0|(
2
1)( YXEYXEXErsX has binomial
distribution
Always L/2 (independent on M and N)
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Analytical Method
Input Switching expectation
Full length used
L/2
Truncate N bits
M/2
N-bit signed
right shift
L/2
Wordlength (L) = 16
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Wallace vs. Booth Multipliers
Tree dot diagram in 4-bit Wallace multiplier
Radix-4 multiplier based on Booth’s recoding (Χ ● a = P)
Asymmetric (one operand
recoded)
Symmetric
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Dynamic Power Consumption for Wallace Multiplier (1MHz)
Reduction(56%)
16-bit x 16-bit multiplier (Simulated on XC3S200-5FT256 FPGA)
Swapping(recode,nonrecode)
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Dynamic Power Consumption for Radix-4 Modified Booth Multiplier (1MHz)
Reduction(31%)
Sensitive(13%)
Swapping(recode,nonrecode)
16-bit x 16-bit multiplier (Simulated on XC3S200-5FT256 FPGA)
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Conclusion• Truncation to 8 bits reduces est. power consumption
by 56% in Wallace and 31% in Booth 16-bit multipliers
• Signed right shift exhibits no est. power reduction in Wallace multiplier (for any shift) and 25% reduction in Booth multipliers (for 8-bit shift)
• Power consumption in tree-based multiplier– Highly depends on input data– Simulation of all switching activity matches analysis of
switching activity in reduced multiplicands in Wallace mult.
• Operand swapping can reduce power consumption– In Booth multiplier, non-recoded operand 13% more sensitive
in power consumption
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Thank You!
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Backup Slides
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Dynamic Power Consumption
• 16-bit x 16-bit multiplier (Simulated on XC3S200-5FT256 FPGA)
Wallace multiplier (1 MHz) Radix-4 modified Booth multiplier (1 MHz)
56%31%
Swapping
