Calibration Techniques in Nyquist AD Converters (2006)_Van Der Ploeg & Nauta
Low Power CMOS AD Converters
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AACD-1994, PRG SLIDE 1
Design Considerations for High-Speed, Low-Power CMOS A/D
Converters
Introduction: Technology and ArchitectureConsiderations Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers
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AACD-1994, PRG SLIDE 2
o e o na og nter acesin VLSI Electronic Systems
VLSI Digital
Physical sensors
Audio I/OStorage media
TransmissionMedia
Imagers andSystem
and Actuators
Displays
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AACD-1994, PRG SLIDE 3
High vs. Low Integration level in A/DInterface Systems
Low-Integration Interface
High-Integration Interface
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AACD-1994, PRG SLIDE 4
Key Problems in ADCImplementations
Must be compatible with high-integration solutions,quasi-digital technology
Drive to lower supplies complicates all aspects ofdesign
ADC Performance can be optimized for systemapplication
Drive toward digital solutions tends to increase ADCperformance requirements
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AACD-1994, PRG SLIDE 5
Example Applications for High-SpeedCMOS ADCs
Wireless LAN Data Channel (1-50MS/s, 6-10b) Magnetic Storage Read Channel(50-200MS/s,6-8b) ADSL data channel (3-10MS/sec, 12-16b) Digital Multi-standard TV Baseband ADC(20MS/sec,8-10b) Digital Video Camera ADC(20MS/sec, 8-12b) CATV Decoder Modem ADC(10-20MS/s,8-10b)A HDTV, various apps, (50-75MS/s, 10b)
Digital-IF for Multi-standard Broadcast TV rcvr(100-200Mb/sec, 8-12b)
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AACD-1994, PRG SLIDE 6
1 10 100 1000 10000
2
4
6
8
10
12
14
Clock Cycles per output sample
Bits
of Resol
ution
Flash,
Pipeline
Succs.
Approx
Serial
2nd order
Sigma-delta
1-bit
t=2(0.4n+1)
t=2(n)
t-nt=1
Qualitative Comparison of ADC
Techniques
Key point: For Video Rates, only candidates are flash, multistep, and pipeline
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AACD-1994, PRG SLIDE 7
Where does Power go in a High Speed ADC?
Precision comparators
Resistor string
Op amps, etc.
Key Aspects of Architecture Selection:
Minimum Number of precision comparators
No R-string
Low power op amp
=>Promising Approach: Power-Optimized Pipeline
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AACD-1994, PRG SLIDE 8
Parallel A/D Converter
High Speed- 10MS/sec->500MS/sec Complex- requires 2N Comparators, High Power Used mainly for very high-speed signal acquisition
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AACD-1994, PRG SLIDE 9
Two-step Flash ADCs
S/H ADC DAC ADCinput
Coarse result
Fineresult
+
-
Advantages: Much less hardware than flash
Disadvantages:
No gain in path- requires precision
comparators
Requires at least three full clocks Usually requires R-string
Exponential hardware growth with resolution
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AACD-1994, PRG SLIDE 10
+
Gvin vo
ADC
Stage1InputS/H Stagei StageNs
Output Register
Input
k-bit
k bits
... ...
00 01 10 11
k bits k bits
DAC
k-bitvin
vo
S/H
Quantized Feedforward ADCs
Advantages:
Same throughput as flash
Much less hardware than flash
Disadvantage:
Requires fastinterstage processing
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AACD-1994, PRG SLIDE 11
Design Considerations for High-Speed, Low-Power CMOS A/D
Converters
Introduction: Technology and ArchitectureConsiderations
Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers
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AACD-1994, PRG SLIDE 12
Design of Low-Power Pipeline ADCs
Some Basic Pipeline Concepts Low-Power Interstage Gain Blocks Dynamic Comparator Implementation
Bootstrapped Clock Driver Design Capacitor Size Optimization Experimental Results
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AACD-1994, PRG SLIDE 13
Pipelined ADC Stage-Typical CMOS Implementation
CS
CI
+
-
-
+
CICS
Reference LevelGenerator
Analog
Mux
Comps
Decode
Logic
DAC
k bits
vin
vin
vo
vo
+
+
vDAC+ vDAC
Bias
Clocks
0
1
1
11
0
0
1
0
0
0
0
0
0
0
100
Ref: C. Conroy, VLSI92
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AACD-1994, PRG SLIDE 14
Typical Implementation: Capacitive DAC
VIN
VOUT
ADC
CS1
CI
CP
+
-
VREF
CS2
CS3
Code
.
.
.
.
.
.
ADC usually R-string flash or Cap-based flash.
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AACD-1994, PRG SLIDE 15
Power Minimization in Switched-Capacitor Gain Blocks
(Telescopic)Folded Cascode Unfolded Cascode
First consider simplest amplifiers:
Cs
Cf
Cl
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AACD-1994, PRG SLIDE 16
Key Issue: What is the fastestattainable settling?
Simplest possible op amp:
Cs
Cf
Cl
Cs
Cgs
Cl Cp
Cf+Cgd=Cft
Cl+Cp =CLtThis is a single-time-constant circuit!
1
gm
Cs
Cg s
+( ) 1 1C
F t
Cg s
Cs
++
CL t
CF t
+=
1
2 ft
1
Cs
Cg s
+
1 1
CF t
Cg s
Cs
++
CL t
CF t
+=
1
2 ft
1
CL t
CF t
+=
Device Width and Drain Current
Fixed Vgs-Vt
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AACD-1994, PRG SLIDE 17
Max Attainable Speed, ContdWhat is the best achievable speed as a functon of technology and charge
gain?
m in
1
2 ft
1
CL t
CF t
+=
m in
1
2 ft
1 Aq
( )+=Where Aq = Charge Gain of circuit
1.0u 1.5u 3u
0.1ns0.2ns
0.5ns
Assumptions:1. Square law applies
2. No slewing
3. Vgs-Vt = 0.5V
4. Neglects all second order device
effects.
5. Aq = 1, Cl=Cf
0.8u
m in
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AACD-1994, PRG SLIDE 18
What is the Minimum Obtainable Power?
Cg s o p t( ) C S
CF
CL
CF
CL
++=
22 f
T
1
CL
CF
+( ) 2m i n
= =
Po p t
8 Vd d
1
2
1 Aq
+( ) 2 CS
CF
CL
CF
CL
++ L 2
2 =
1g
m
Cs
Cg s
+( ) 1 1C
F t
Cg s
Cs
++
CL t
CF t
+=
Minimize:
Result:
Id
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AACD-1994, PRG SLIDE 19
Observations:
Optimum Cgs is equal to Cequiv Power is very sensitive to charge gain- use low gain/stage in pipelines
Power drops rapidly with technology line width Analysis says pwr goes as square of speed, channellength, but actually it is more like linear because ofSlew Rate, Velocity Saturation.
Leff,Microns
DesiredTime
Const.
kT/C noise for1/6 lsb, Vswing=1V
Cs Cf ClPower,Vdd=3V
0.8 400ps 8bits, 600uVRMS 10fF 5fF 5fF 72uW
0.8 400ps 10bits, 150uVRMS 160fF 80fF 80fF 1.1mW
0.8 400ps 12bits, 37uVRMS 2.5pF 1.25pF 1.25pF 18mW
0.8 400ps 14bits, 9uVRMS 40pF 20pF 20pF 200mW
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AACD-1994, PRG SLIDE 20
More Practical AmplifierConfigurations
Design Issues with FC, Telescopic:
Poor voltage gain-settling time trade-off
Poor voltage swing-settling time trade-off Barely usable at 3V, not usable at 1.5V
Alternative Approaches:
Add broadband input stage to telescopic Two-stage Miller compensated w/one stagecascoded
Multi-stage Nested Miller amplifier
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AACD-1994, PRG SLIDE 21
C3 C4
Vin+ Vin-
Vout+ Vout-
Vdd = 3.3V
Vdd = 3.3V
Vdd = 3.3V
C1 C2
Gain-BoostAmplifier
Bias 4
Bias1
Bias2
Bias3
Bias4
Bias1
Bias3
sw1 sw2
Bias1
Telescopic Amplifier with Gain
Boost Stage
ts = 17ns(0.1%)
Cs = 0.39pF
Cf = 0.39pF
Cl = 1.8pFPd = 4.1mW
Vdd=3.3V
Av>60dB
Swing = +/1VoltP-P
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AACD-1994, PRG SLIDE 22
Dynamic Comparators in PipelineADCs
Conventional Comparator Design:
Broadband, Low-offset preamp
Latch
Clk
Vin dout
Key Goal:
Get rid of preamp with its power dissipation, usedynamic latch as comparator
Key Question:
How much comparator offset can be tolerated?
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AACD-1994, PRG SLIDE 23
Gain and Offset Errors in Pipelines
OffsetError
GainError
S/H
OffsetError
GainError
S/H
OffsetError
GainError
S/H
n1bitADC
n1bitDAC n2bitADC n2bitDAC
n3bitADC
n1 bits n2 bits
n3 bits
+
-
+
-
Vin
Error: Effect on Linearity:
Input Gain None
Other Gains Reduced by 1st stg gain
Offsets None
Effect of ADC Nonlinearity Errors
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AACD-1994, PRG SLIDE 24
Effect of ADC Nonlinearity Errors
2-bit example:
S/H
2 bitADC
2 bitDAC
2 bits
+
-
Vin
Inputreferrednonlinearity
error
4
00 01 10 11Vr
-VrResidual
Residual
Case 1: Ideal ADC, DAC
Vin
Vr
00 01 10 11Vr
-Vr
Residual
Vin
Vr
Negative DecisionLevel Error
Positive DecisionLevel Error
Case 2: Nonideal ADC, Ideal DAC+
Key Point: Can remove ADC Errors by Increasing ADC range in next stg
Di i l C i i Pi li
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AACD-1994, PRG SLIDE 25
Digital Correction in Pipelines
VinStage 1
0.5Stage 2
n1 bitreg
n1 bitreg
n2 bitreg
Correction
Logic
n1+n2-1 bits out
Reduce Gain to Increase Conversion Range
Correction Logic is Simple
Comparators: Need additional, but they are much simpler
Final Result: DAC Linearity and amplifier gain errors ultimately limit linearity
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AACD-1994, PRG SLIDE 26
Important Case: 1.5 bit/Stage with
Digital Correction
-1 +10 12
14
14
12
vin
vout+1
-1
01 10
0
q 2-bit
q 222 = 2 comps
q G = 221= 2
00
refs: C. Conroy, VLSI92, Jusuf ICCAD90, Lee VLSI93, Jespers ESSCIRC91
Key Point: Tolerates comparator offset
on the order of 1/4 full scale!
I ti f ADC R f
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AACD-1994, PRG SLIDE 27
Incorporation of ADC ReferenceLevel Function in Comparator
Vin+Vin-
Vout+Vout-
Vdd
latch / reset
Vref+Vref-
M1 M2 M3 M4
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AACD-1994, PRG SLIDE 28
Vin+ Vin-
Vout+Vout-
Vdd
latch/reset
Vref+Vref-
w1w2 w1 w2
If w1 = M x w2, Vdecision = Vref / M
Well defined built-in Vdecision based on ratio
Simple design for low input cap.
No DC power!
Vout+Vout-
Vdd
latch/reset
R1 R2
Dynamic Comparator Implementation
Low Voltage Switched Capacitor Gain
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AACD-1994, PRG SLIDE 29
Low Voltage Switched-Capacitor GainBlocks
DAC
B+1 bits
STAGE i
+
- opamp
Vout
Vref
Vin
(2B
- 1) x C
C
B+1 bitsflash
C
C
ADC
InterstageAmplifier
-Vref
Vin
Switch
Cs
L V l O i f MOS
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AACD-1994, PRG SLIDE 30
*Integrated A/D&D/A Converter, OCATE, July 1991Low Power ADC by Vlado Valencic
VddGND
Conductance vs. Voltage *
-Vthp
Vdd=5VGND
Vdd=3.3VGND
GND Vdd=1.5V
Gap!
Gon
Vdd
Gon
= gdsn+gdsp
(Vthn=|Vthp| = 0.8V)Vin
-Vthn
Low-Voltage Options for MOS
Transmission Gates
L V lt T i i G t
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AACD-1994, PRG SLIDE 31
Possiblesolutions
Good (+) / Bad (-)
Dual Vth process(0Vth Native dev)
+ standard design approach- need process mod
Low Vth Process + Needed for digital anyway- Big cost in power due to limited swing to railGlobal charge pump - possible cross-talk to sensitive nodes
- difficult to predict CL
Local charge pump + no cross-talk (can isolate sensitive nodes)+ easy to predict CL
Low-Voltage Transmission Gates,
contd
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AACD-1994, PRG SLIDE 32
Vdd = 3.3 V
C1 C2CL
0
3.3
0
Vhi = ~5V
Vsub_hi
Only NMOS switch needed
Less parasitic cap.
V h iC 2
C
2
C
L
C
parasitic
+ + 2 V d d=
High-Voltage Clock Generator
Optimum Scaling of Pipeline Stages
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AACD-1994, PRG SLIDE 33
N bit ADC, B bits/stageex) N=10, B=1
STAGE 1 STAGE 3 STAGE 4Vin STAGE 2
10bit 9bit
STAGE 1 STAGE 3 STAGE 4Vin STAGE 2
10bit9bit With Scaling
Without Scaling8bit
8bit
Optimum Scaling of Pipeline Stagesfor Power Dissipation
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AACD-1994, PRG SLIDE 34
Approx. 40 - 50% reduction in static powerconsumption!
Minimum performance degradation
Requires auto-calibration to correct cap
mismatches for front stages
Speed LimitedNoise Limited
Stage
Power
1 2 N-1 N
Scaled!
Unscaled
(Due to parasitic capacitance)
Optimization result:
Experimental Prototype
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AACD-1994, PRG SLIDE 35
Experimental Prototype
1.2m 2-poly, 1-metal CMOS Technology 3.2x3.3mm active area
Experimentally Observed Power vs.
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AACD-1994, PRG SLIDE 36
3
5
10
15
20
30
1 2 5 10 20
Power(mW)
Fs(MS/s)
p ySampling Rate
Master bias current adjusted for each sample rate
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AACD-1994, PRG SLIDE 37
-1.0
-0.5
0.0
0.5
1.0
-1.0
-0.5
0.0
0.5
1.0
0 code 1000
0 code 1000
(a)
(b)
(LSB)
(LSB)
(a)Measured DNL, 3.3V, 25C, Code Density
Integral and Differential Nonlinearity
(b)Measured INL, 3.3V, 25C, Code Density
SNDR versus Input Level
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AACD-1994, PRG SLIDE 38
2025
30
35
40
45
50
5560
0-10-20-30-40
Input level (dB)
SNDR (dB)
SNDR versus Input Level
3.3V Supply, 25C
Ideal 10 bit
100kHz Input
10MHz Input
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AACD-1994, PRG SLIDE 39
Measurement Results
ADC Performance: 3.3V @ 25C
*: Output pad driver power not included
Technology 1.2-m CMOS
Resolution 10 b
Conversion Rate 20 MS/s
Active Area 3.2 x 3.3 mm2
Differential Input Range +/- 1 V
Input Capacitance 1 pF (single-ended)
Power Dissipation 35 mW* at 20MS/s(2.8 mW* at 1MS/s)
DNL/INL 0.5 / 0.6 LSB
SNDR 59.1 dB (Fin=100 kHz)55.0 dB (Fin= 10 MHz)
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AACD-1994, PRG SLIDE 40
(mW/MS/s)
Power/fs
1/L(m)3m 2m 1m
0.1
1
10
100
1.5m 0.8m
Matsushita,ISSCC93
10bit ADC
Power/fs vs. Technology
[88]
[90][91]
[92]
[93]
[92]
10bit
[94]
[Year]
[94]
This Work
Summary of High Speed ADC Performance
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AACD-1994, PRG SLIDE 41
y g p
Author Type ratebits
techS/H?
PSV Pwr Area FM1 FM2
1. Sekino,So-ny,ISSCC82
2step 30M 8 4Gbip N 5V 0.7 35K 7.5 2.74
2.Tsukada,Hitach
i, ISSCC85
FL 25M 8 2uCMOS Y 5V 0.3 33K 16 13.6
3. Dingwall,RCA,ISSCC85
2step 5M 8 2uCMOS Y 5V 0.15 6K 3.3 5.6
4. Peetz,HP,ISSCC86
FL 250M 8 7Gbip N 5 12 48K 36 0.77
5.Lewis,UCB,ISSCC86
Pipe 5M 9 3uCMOS Y 10 0.18 10K 7.2 23.0
6. V.D.Grift,-Phil, ISSCC87
Fold 50M 8 7.5Gbip N 5 0.3 10K 6.6 5.63
7. Yoshi,So-ny,ISSCC87
FL 350M 8 10Gbip N 5 1.5 22K 35 5.97
8. Akazaw,NT-T,ISSCC87
FL 400M 8 18Gbip N 5 2.7 65K 22 2.08
9. Tsutomo-to,NTT,ISSCC88
FL 2G 6 26Gbip N 5 2 18K 76 9.73
10. V.D.Pla-asche,Ph,ISSC
C88
Fold 100M 8 12Gbip N 5 0.8 17K 8.3 2.65
ADC Performance, Contd
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AACD-1994, PRG SLIDE 42
11.Matsuura,Hita,ISSCC88
2step 20M 8 2u Y 5 0.2 11K 13 16.4
12. Song,UnivIll,ISSCC88
Pipe 1M 12 1.5CMOS Y 5 0.4 7.8K 0.4 4.0
13. Shimit-zu,ISSCC88
2step 20M 10b
4.5Gbip Y 5 0.9 40K 4.4 5.06
14. Kerth, Xtal,CICC88
2step 1M 12b
3uCMOS Y 10 0.7 150K 1.4 8.0
15. Mas-ayuki,NTT,ISSCC89
2st 40M 8b 1uCMOS Y 5 0.6 20K 8.0 3.41
16. Chin,Nat,ISSCC89
2st 1.5M 10b
2uCMOS N 5 0.15 15K 1.0 6.82
17. Fukishi-ma,Sony,ISSCC89
2st 40M? 8b 1.4CMOS Y 5 0.1 8.1K 22.2 56.8?
18. Robertson,AD,ISSCC90
Pipe 20M 10b
BICMOS Y 5 1.0 85K 10.0 10.2
19. Song, UnivIll,ISSCC90
2step 15M 10b
1uCMOS Y 5 0.250 4K 3.0 12.28
20. Zojer,Sei-mens,ISSCC90
2step 75M 10b
7Gbip Y 5 2 23K 10.7 5.476
ADC Performance, Contd
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AACD-1994, PRG SLIDE 43
21.Mats.,Mistub,ISSCC90
2st 30M10b
7GBCMOS Y 10 0.75 40K 4.3 5.87
22. Lin, UCB,-VLSI90
Pipe 2.5M 13b
3uCMOS Y 5V 0.1 40K 3.6 144(12b)
23. Lewis,AT-T,CICC91
Pipe 20M 10b
1uCMOS Y 5V 0.3 12K 4.0 13.6
24. Gendai,Sony,ISSCC91
FL 500M 8b 10Gbip N 5V 3.1 35K 50 4.1
25. Mat-suzawa, Mat-s.,ISSCC91
FL 1G 6b 13Gbip N 5V 2.8 40K 75 6.8
26. ValBerg,-Phil,ISSCC92
fold 600M 8b ? N 5V 0.9 7K 50(est) 14.2
27. Vorenka-mp,Phil,ISSCC92
Pipe 50M 10b
3Gbip Y 5V 0.75 18K 16 21.8
28. Corcora-n,HP,ISSCC92
Pipe 20M 12b
7Gbip Y 10V 3.5 26K 3 3.5
29. Reza-vi,Stan,ISSCC92
2step 5M 12b
1uCMOS Y 5V 0.2 16K 0.8 16.2
30. Karanico-las,MIT,ISSCC93
Pipe 1M 15b
4G,2.4uBiCMOS
Y 10 1.8 100K 025 4.4
ADC Performance, Contd:
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AACD-1994, PRG SLIDE 44
FM1 is ratio of sampling rate to equivalent technology ft multiplied by 103
FM2 is a power figure of merit normalized to technology ft. It is given by
P= power dissipation
B= number of bits
SR=sample rate
31.Kusumoto,Mats,ISSCC93
Pipe 20M 10b
0.8uCMOS Y 5 0.030 10K 2 68.3
32. Sone,NEC,ISSCC93
Pipe 100M 10b
0.8uBiCMOS Y 5V 0.95 32K 5-10? 10.7
33. Colleran,UCLA,ISSCC93
Pipe 100M 10b
12Gbip Y 5 0.8 30K 8 10.2
34. Conroy,VLSI 92
Parallelpipe
85M 8b 1.2uCMOS Y 5 0.8 35K 18 5.7
35. Tada,ISSCC93
2-step 30M 10b
0.8uCMOS Y 3.3 0.030+ 20K 3.5 90
F M 22
BS R( )
P f
t
=
22This work
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AACD-1994, PRG SLIDE 45
0.30
1.0
3.0
10.0
30.0
100
6 7 8 9 10 1211 13Resolution, bits
FM2
9
4
7
8
2
10
15
1
63
115
20
18
23
2113
16
22
14
12
19
Flash
2-stepFolding
Pipeline
24
25
26
27
28
29
31
3233
Comparison of Power Figure of Merit, Recently
Published Flash, 2-step, and Pipeline ADCs
33
34
F M 22
BS R( )
P ft
=
35
Effective ft vs. Channel Length
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AACD-1994, PRG SLIDE 46
1
2
3
4
5
6
7
5u 3u 2u 1.5u 1u
Silicon MOSFET
0.8u 0.6u
8
9
10
Drawn Channel Length
1.2u
Approximate
Value of NMOS
Device ft, Ghz
(Assumes bias
point of
Vgs-VT = 0.5V)
QbicI NMOS(RGM 1994 data)
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AACD-1994, PRG SLIDE 47
Design Considerations for High-Speed, Low-Power CMOS A/D
Converters
Introduction: Technology and ArchitectureConsiderations
Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers
Comparison of Pwr in Pipelines, Sigma-Delta Converters
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AACD-1994, PRG SLIDE 48
vn
2 fp b
fs 2 k T
Cs
Typical Sigma-Delta Front End:
Vin+
Vin-
Vdac-Vdac+ To second and later stages
In-band kT/C:
Conclusion: For each 2x increase in OSR,
Cs can be 2x smaller Sample rate is 2x higher Power remains constant for constant in-band noise
One-bit increase in SNR costs 4X in cap value, power
Comparison of FM3 for Sigma Delta, Pipelines
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AACD-1994, PRG SLIDE 49
F M 3P
fs
22 B
=
Author Type
ModulatorSamp.Rate
OutSR
OutputResolution
Techn PSVMod.Pwr
FM3
1. Dedic,ISSCC94
6thord.
3.25M 200K 14b 1.2uCMOS
5V 40mW 7.8e-16 200mW/MS/sec
2. Alex-ander,ISSCC94
4thord.
12M 192K 14b(limbyxtalk)
1uBiCMOS
5V 150mW(est)
350e-16
3. Rito-neime,ISSCC94
4thord.
2.5M 44K 16b 1.2uBiCMOS
5V 100mW
5.5e-16 2.3mW/kS/sec
4. Ray,pc
4thord.
18M 584K 13b 1uCMOS
5V 25mW 6.6e-16 43mW/MS/sec
5. Mats.,ISSCC94
2ndord.
6M 380K 9b 0.5uCMOS
1V 1.5mW 39e-16 3.9mW/MS/sec
6. Tcho pipe 20M 20M 10b 1.2uCMOS
3V 35mW 15e-16 1.7mW/MS/sec
Typical Power Performance Levels,
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AACD-1994, PRG SLIDE 50
Typical Power Performance Levels,
Recently Published ADCs
10 12 14 16
mW/MS/sec
1
10
100
1000
1
3
4
56
Effective Resolution, bits
Power,
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AACD-1994, PRG SLIDE 51
Design Considerations for High-Speed, Low-Power CMOS A/D
Converters
Introduction: Technology and ArchitectureConsiderations
Design of Low-Power Pipeline A/D Converters Comparison with Alternative Approaches Possible Future Trends and Barriers
Key Issues in High-Speed ADCsG i F d
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AACD-1994, PRG SLIDE 52
Going Forward
Where do we get another major power increment?
Class B op amps?
Charge-domain operation?How do we get to 1.5 volts at reasonable power? Nested Miller op amps? More coarse/fine sampling?
How do we solve the Digital supply noise problem?
More effective on-board sub-regulation? Better CAD tools for simulation?
Process/package enhancements?How do we push sample rates to 200-300 Mhz in CMOS? More parallelism plus self-cal? Better analysis of MOS sample/hold?
Projecting Integration levels in A/DInterface Systems
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AACD-1994, PRG SLIDE 53
Interface Systems
Low-Integration Interface, 1984
High-Integration Interface, 1994
Super-integrated subsystem, 2004
0.15 micron technology
1.5-2.5V Vdd, >108 xistors/chip
Analog content