Low Power ALU Project Phase2

8/12/2019 Low Power ALU Project Phase2

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LOW POWER ALU DESIGN 2013-14

node are being used to design low power high-performance chips based on 2),S% At a

gi&en clock rate and for a known load capacitance the dynamic power dissipation is

proportional to the s5uare of the power supply &oltage% $herefore reducing the power supply

&oltage results in 5uadratic impro&ement in the power dissipation of a 2),S circuit which

is the most common and effecti&e way of reducing the power consumption%

1.3 '"t&(at&"!

A high Speed Fast 7(-bit ALU is designed with the methodology of Back Gate

Forward Substrate Bias BGFSB! by using "#nm $echnology% $his method of forward

biasing the back gate or bulk substrate with respect to the source in the dynamic acti&e mode

is shown in figure below% A forward bias &oltage for both .),S and 8),S is applied% $his

methodology applying at low power source &oltage will impro&e the circuit delay

considerably and gi&es an impro&ement factor of about '-(% $he different types of Adder and

)ultiple*er structures are designed and chosen for best performance with the compromise of

Area .ower and delay% $he BGFSB /oltages has been limited to 0#%4 /0%

Fig '%' BGFSB 3esign%

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1. T""/ Ut&&at&"!

2adence $ools with .0m $echnology using /irtuoso Schematic +ditor for all

Schematic design

Analog 3esign +n&ironment for /erification and Analysis using Spectra $ool%

1. Ora!&at&"! "* the rep"rt

6n this section a brief pre&iew of the organiation of this pro1ect report is gi&en% $he

pro1ect report is di&ided into : chapters as mentioned below%

6n chapter ' 6ntroduction ob1ecti&es problem definition methodology software

tools re5uired in the pro1ect literature sur&ey and organiation profile ha&e been

discussed% $he remaining chapters are organied as follows%

2hapter ( pro&ides study of Literature sur&ey of circuits% 6t includes the design issues

of different types of Adder and )ultiple*er and their performance%

2hapter 7 .ro&ides study about the Adders and different logical style of

implementation and its ad&antages%

2hapter 4 pro&ides the study of .roblem definition of the Architectural

6mplementation of ALU%

2hapter ; pro&ides the study of .roposed Architecture design and 6mplementation of

ALU%

2hapter < pro&ides the results obtained in this pro1ect and the detailed discussions of

these results%

6n chapter : the summary and conclusion of this pro1ect work is addressed%

6n Appendi* A Appendi* B defines the referral paper and paper presentedrespecti&ely%

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Chapter 2

L&terat$re S$r(e5

A high-speed 4-bit ALU has been designed for '/operation to demonstrate the

usefulness of the backgate forward substrate bias BGFSB! method in '%( mm 8-well

2),S technology% $he 4-bit ALU employs a ripple carry adder and is capable of performing

eight operations - four arithmetic and four logical operations% $he BGFSB &oltage has been

limited to 1#%41/% 3elay time measurements are taken for all operations from the S.62+

simulations with and without the back-gate forward substrate bias% A speed ad&antage of a

factor of about (=(%; is obtained with BGFSB o&er the con&entional design>"?%

6n modern era the number of transistors are reduced in the circuit and ultra-low

power design ha&e emerged as an acti&e research topic due to its &arious applications% A full

adder is one of the essential components in digital circuit design many impro&ements ha&e

been made to reduce the architecture of a full adder% $he main aim of this paper is to reduce

the power dissipation and area by reducing the number of transistors%by using general logic of

pmos transistor the two transistor *or gate can be implemented% 6n this paper proposes the

no&el design of a ($ @, gate% $he design has been compared with earlier proposed 7$ 4$

and '#?%

6n present work a new @8, gate using three transistors has been presented which

shows power dissipation of ;;#%:(:(CD in #%7;Cm technology with supply &oltage of 7%7/%

)inimum le&el for high output of (%#;/ and ma*imum le&el for low output of #%#4/ ha&e

been obtained% A single bit full adder using eight transistors has been designed using

proposed @8, cell which shows power dissipation of ;'%;4(CD% )inimum le&el for

high output of '%":/ and ma*imum le&el for low output of #%(4/ is obtained for sum output

signal% For carry signal ma*imum le&el for low output of #%7(/ and minimum le&el for high

output of 7%(/ ha&e been achie&ed% Simulations ha&e been performed by using S.62+ based

on $S)2 #%7;Cm 2),S technology% .ower consumption of proposed @8, gate and full

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adder has been compared with earlier reported circuits and proposed circuitEs shows better

performance in terms of power consumption and transistor count >''?%

$his paper presents comparati&e study of high-speed low-power and low &oltage full

adder circuits% ,ur approach is based on @,-@8, design full adder circuits in a single

unit% A low power and high performance "$ full adder cell using a design style called @,

7$! is discussed% $he designed circuit commands a high degree of regularity and symmetric

higher density than the con&entional 2),S design style as well as it lowers power

consumption by using @, 7$! logic circuits% Gate 3iffusion 6nput G36! techni5ue of low-

power digital combinatorial circuit design is also described% $his techni5ue helps in reducing

the power consumption and the area of digital circuits while maintaining low comple*ity of

logic design% $his paper analyses e&aluates and compares the performance of &arious adder

circuits% Se&eral simulations conducted using different &oltage supplies load capacitors and

temperature &ariation demonstrate the superiority of the @, 7$! based full adder designs

in term of delay power and power delay product .3.! compared to the other full adder

circuits% Simulation results illustrate the superiority of the designed adder circuits against the

con&entional 2),S $G and 9ybrid full adder circuits in terms of power delay and power

delay product .3.! >'7?%

$his paper presents a comparati&e study of high-speed and low-&oltage full adder

circuits% ,ur approach is based on hybrid design full adder circuits combined in a single unit%

A high performance adder cell using an @,-@8, 7$! design style is discussed% $his

paper also discusses a high-speed con&entional full adder design combined with ),S2A.

)a1ority function circuit in one unit to implement a hybrid full adder circuit% )oreo&er it

presents low-power )a1ority-function-based '-bit full adders that use ),S capacitors

),S2A.! in its structure% $his techni5ue helps in reducing power consumption

propagation delay and area of digital circuits while maintaining low comple*ity of logic

design% Simulation results illustrate the superiority of the designed adder circuits o&er the

con&entional 2),S $G and hybrid adder circuits in terms of power delay power delay

product .3.! and energy delay product +3.!% .ost layout simulation results illustrate the

superiority of the newly designed ma1ority adder circuits against the reported con&entional

adder circuits% $he design is implemented on U)2#%' Cmprocess models in 2adence

/irtuoso Schematic 2omposer at '% / single-ended supply &oltage and simulations are

carried out on Spectre S >'4?%

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Full adder is the essential component for the design and de&elopment of all types of

processor% $his pro1ect introduces the design of high performance low power full adder which

ac5uires least area with the lowest transistor count% $he high performance low power full

adder is designed and the implementation of a 7(-bit ripple carry adder based on high

performance low power full adder is described and comparison is made between other

pre&iously designed full adders% $he high performance low power full adder circuit is

designed and the simulation has been carried out on $anner +3A tool% $he result shows that

the proposed high performance low power full adder is an efficient full adder cell with least

),S transistor count that reduces the high power consumption and it considerably increases

the speed >';?%

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Chapter 3ADDERS

An Adder or summer is a combinational digital circuit that performs addition of numbers% 6n

many computers and other kinds of processors adders are used not only in the arithmetic

logic units! but also in other parts of the processor where they are used to cal

T5pe/ "* A##er/

'% 2),S Adder

(% )irror Adder

7% 3omino Adder%

4% Split .ath 3ata 3ri&en 3ynamic logic%

;% 2omplementary .ass $ransistor Logic%


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Figure 7%' 2),S Full Adder%

$he SU) and 2AH of full adder is calculated by using following e5uation%

SU) I A *or B *or 2! JJJJJJJJJJJJJJJJJJJJJJJJ%%'!

2AH I A and B! or B and 2! or 2 and A!JJJJJJJJJJJJJJJ(!

$ABL+ 7%' Full Adder

A B CIN SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 01 0 1 0 1

1 1 0 0 1

1 1 1 1 1

$he e5uation '! and (! are the full adder e5uations for SU) and 2AH% $he SU) is high

when odd numbers of inputs are high% And the 2AH is high when two or more than two

input is high% $he abo&e e5uations can be written as

SU) I A @, B @, 2JJJJJJJJJJJJJJJJJJJJJJJJ%7!

2AHIABKBKA!268JJJJJJJJJJJJJJJJJJJJJJJ%%%J4!

$he e5uation 7! and 4! can be used to implement a full adder% $his gi&es a regular structure

of full adder% A well know factor is that in the static full adder e&ery pull down network has

its compliment in the pull up network% So this results in increase in transistor count and hence

increases in area as well power consumption% 3rawback of 2),S is the relati&ely weak

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Figure 7%( $wo dynamic 8A83 gates sharing same clock

$he dynamic-static combination is known as a domino gate% $his is analogous to a

chain of dominoes - the precharge represents setting up of dominoes and the e&aluation

represents their se5uential triggering% 8o doubt the domino circuit has remo&ed the problem

of monotonicity but it further has certain disad&antages% $he problems associated with

domino are non-in&erting output and the charge sharing problem% As it is clear that by placing

a in&erter sol&es the problem of monotonicity thereby getting correct output H% $his will be

clear from the figure (%"

Figure 7%7 ,utput wa&eforms of two dynamic 8A83 gates sharing same clock

3.2.1 Pr"pert&e/ "* D"m&!" L"&%

A single clock can be used to prechargee&aluate each stage in a chain

.recharge occurs in parallel but e&aluation occurs se5uentially

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3.2.2 D&/a#(a!tae/ "* #"m&!" "&% %&r%$&t/

N"!-&!(ert&! "$tp$t

$he domino circuits produce only the non -in&erting output howe&er certain logic

synthesis operations re5uire in&erting as well as non -in&erting operation in the same

circuit% So there is a need of some logic with in&erting as well as non-in&erting

function%

Chare /har&!

2harge sharing is an undesirable signal integrity phenomenon obser&ed most

commonly in the domino logic family of digital circuits% $he charge sharing problem

occurs when the charge which is stored at the output node in the phase is shared among

the output or 1unction capacitances of transistors which are in the e&aluation phase%2harge sharing may degrade the output &oltage le&el or e&en cause erroneous output

&alue%

C"%, "(er"a#&!

6n the domino logic circuits clock is associated with e&ery .),S therefore in case of

large or cascading domino logic circuits o&erloading occurs% So more the number of .),S

transistors more will be the clocks associated and hence more is the power dissipation%

3.3 Sp&t Path Data Dr&(e! D5!am&% L"&%

$o impro&e the slow pre-charge phase of the SU) path in the original 37L adder we

split the pre-charge path into two% $he design of the .38 is also di&ided into two paths%

+ffecti&ely the output node from the original 37L logic has now been split into two marked

by 3' and 3(% Splitting the pre-charge and e&aluation paths results in significantly reduced

capacitance at the output node% 2ombined with faster pre-charge the circuit also achie&es a

degree of resistance to charge-sharing issues% $he split-path approach effecti&ely hal&es the

possible paths for charge sharing within the adder circuit as compared to the con&entional

37L or standard domino implementations% )inimum sied keepers further help to restore the

charge at nodes 3' and 3(% $he output signals 3' and 3( dri&e a standard 2),S 8A83

structure to generate the final output% An in&erted SU) output goes back to dri&e the gates of

the two keeper transistors% $he charge on 3' and 3( is thus restored through a common path

allowing both the nodes to restore simultaneously minimiing the probability of any

incorrect operation% $he hybrid adder circuit thus incorporates the key ad&antages of 37Llogic style as well as original standard 2),S% $he use of a shorter pre-charge path ensures

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faster circuit operation% $he final standard 2),S topology brings along a high noise margin

impro&ed signal robustness sharper rise and fall times as well as an o&erall increase in

reliability% Splitting the pre-charge and e&aluation networks also means lower number of

stacked .),S and 8),S transistors% $his allows rela*ed siing of the transistors e&en

minimum sied de&ices! and translates into an impro&ed fan-in and fan-out performance of

the circuit in both super-threshold and sub-threshold operating regions%

Fig 7%; Split .ath 3ata 3ri&en 3ynamic Logic Full adder.

3.4 C"mpeme!tar5 Pa// Tra!/&/t"r L"&%

$he complementary pass transistor logic 2.L! full adder with swing restoration is

shown in Fig% (%'; 6ts dual-rail structure uses 7( transistors% $he basic difference between the

pass-transistor logic and the complementary 2),S logic styles is that the source side of the

pass logic transistor network is connected to some input signals instead of the power lines >:?%

$he ad&antage is that one pass-transistor network either p),S or n),S! is sufficient to

implement the logic function which results in smaller number of transistors and smaller input

load% 9owe&er pass-transistor logic has an inherent threshold &oltage drop problem% $he

output is a weak logic ' when ' is passed through a n),S and is a weak logic # when

# is passed through a p),S% $herefore output in&erters are also used to ensure the

dri&ability% 2.L is not an appropriate choice for low power due to its high switching acti&ity

of intermediate nodes high transistor count and o&erloading of its inputs%

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Figure 7%< 2omplementary .ass $ransistor Logic Adder%

3. Tra!/m&//&"! Gate 6$ A##er

A transmission- gate adder $GA! >(? using 2),S transmission gates is shown in

Fig% (%'


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Figure 7%: $ransmission Gate Full Adder

3. Tra!/m&//&"! 6$!%t&"! 6$ A##er

A transmission function full adder $FA! >('(? based on the transmission function

theory is shown in Fig% (%':% 6ts design based on transmission function theory and has '(?%

$he logic e*pressions for the intermediate signals and outputs are gi&en as followsM

SumI A B2in

2out I A%B K 2in AB%

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Figure 7%'' 9ybrid Full Adder%

A% )odule 'M @,@8,

6t use different sets of transistors to generate the @, and @8, functions separately $o

reduce the number of transistors we use a similar pass transistor circuit as in >? with only si*

transistors to generate the balanced @, and @8, functions as shown in Fig% (%

2omparing with those designs that use an in&erter to generate the complement signal the

switching speed is increased by eliminating the in&erter from the critical path% $he two

complementary feedback transistors restore the weak logic caused by the pass transistors%

$hey restore the non full-swing output by either pulling it up through p),S to the power

supply or down through n),S to ground so that sufficient dri&e is pro&ided to the successi&e

modules%% 9owe&er this circuit suffers from the same threshold &oltage drop problem as any

other pass-transistor logic circuits% $he worst-case delay happens at the transition from #' to

## for inputs AB% 3ue to the unsatisfactory performance at low-supply &oltage we modified

the circuit of Figure (%(# by adding two series p),S transistors to sol&e the worst-case delay

problem of transition from #' to ## for% $wo series n),S transistors are added to sol&e the

problem of transition from '# to '' for% Dhen the state of ## arri&es the @8, output couldobtain a strong ' through two series p),S pull-up transistors to the power supply which

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a&oid the high-impedance state as in the pre&ious case% Similarly the @, output could

obtain a strong # through two series n),S pull-down transistors to ground when the state

of transits to ''%

Figure 7%'( @,-@8,


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Figure 7%'7 7$ @, Gate

Sum I A B 2

2arry I B2 K 2A K AB I 2 A B! K AB%

Figure 7%'4 )odified 9ybrid Full Adder $!%

$he Sum output function is obtained by a cascade of 7$ @, gates% 2arry can be realied

using a wired , logic in accordance with the abo&e e5uation% Another $ full adder using

centralier output condition contains three modulesNtwo 7$ @, gates and one multiple*er($!% 6t can work at high speed with low power dissipation due to minimum number of

transistors and small transistor delay

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Chapter 4

PRO:LE' DE6INITION

$he con&entional design of ALU was not compromised with Area .ower and 3elay

$he use of con&entional design in low power application was not so good and suitable

9ence the main aim was to reduce the power consumption in the design and intern to

increase the speed of operation of the circuit to work at faster rate

$he solution was only to design the Functional Blocks in different logic styles and to enhance

the .erformance%#

4%' .,.,S+3 D,O

Back Gate Forward Substrate Bias BGFSB! is adopted in this pro1ect%

$he method of forward biasing the back gate or bulk substrate with respect to the

source in the dynamic acti&e mode is shown in figure below along with the

implementation of ' Bit ALU%

A forward bias &oltage for both .),S and 8),S is applied%

$his methodology applying at low power source &oltage will impro&e the circuit

delay considerably and gi&es an impro&ement factor of about '-(%

Fig 4%' ' Bit ALU

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$he Figure shows the design Architecture of without BGFS B and Dithout BGFSB

for a simple in&erter e*ample%

Fig 4%( 6n&erter with BGFSB )ethod%

Fig 4%7 6n&erter without BGFSB )ethod%

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Chapter

De/&! Ar%h&te%t$re "* ALU

Fig ;%' M Block 3iagram of 4-Bit ALU

Figure ' shows the block diagram of the 4-bit ALU of the ripple carry adder type which

performs four arithmetic and four logical operations% $he four arithmetic operations include

A33 SUB$A2$ 682+)+8$ and 3+2+)+8$% $he four logical operations include

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A83 , +@, and +@8,% +ach stage of the ALU is composed of the following three

componentsM '! the input multiple*er with A83=, logic

(! the full adder and

7! the output multiple*er with A83=, logic%

+ach bit uses two multiple*ers and one full adder% $here is one multiple*er at the input

section and one at the output% $he multiple*ers ha&e two select inputs S# and S'% $he 4-bit

ALU uses a 4-to-' )U@ designed in 2),S pass transistor logic for low power% $he )U@s

are used to pro&ide the proper input signal for the adder circuit depending on the operation

being performed on the input side and also to pass the output of the full adder to the output

pin at the output side% Figure shows the block diagram of a 4-to-' )U@ where a select pin

S( is connected to the A83=, logic% For S( #P one of the four arithmetic operations is

performed while for S( 'P one of the four logical operations is performed as shown in $able

6% Figure shows the logic diagram of the full adder from which the following four logic

functionsM A83 , +@, and +@8, ha&e been deri&ed% , is implemented from 8,-

68/+$ configuration in 2),S% $he output stage in Fig includes a 4-to-' )U@ with added

A83=, logic at the output% S(p is complement of S( bit used in the input stage of the 4-to-

' )U@ with A83=, logic% For S( bit e5ual to ' or S(p bit e5ual to ero we get logic

function at the output% Since the logical operations are performed using the basic logic gates

the delay for each logic operation would be the delay through the gate% 9owe&er the

arithmetic operations make use of the complete adder% 6ncrement and decrement operations

are special cases of addition and subtraction% 6ncrement operation is e5ui&alent to an addition

by ' and subtraction is e5ui&alent to (Es complement addition% $he delay for each arithmetic

operation is more comple* than that of the logical operation as it depends not only on the

type of logic used to construct the SU) and 2AH units of the full adder but also on the

input pattern and the critical paths in the circuit% ,ptimiing the design of the full adder

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optimies all operations to some e*tent% $he Boolean e*pressions for the SU) and 2AH

are described as followsM

Dhere A and B are two inputs and 268 is the 2AH input to the full adder% As shown in

$able 6 a particular operation of the ALU is performed based on the three select signals S#

S' and S(! thus allowing one of the eight operations to be performed% S# is the LSB and S(

is the )SB% For the logical operations each bit output is obtained in parallel as the

operations of each bit are independent of the other% For all arithmetic operations each

successi&e stage depends on the pre&ious stage for the 2AH bit% After the full adder

performs the necessary operation the output multiple*er selects the correct output% $he &alue

of signal S( decides whether it is a logical or arithmetic operation% Figure shows the topology

of a 4-bit ripple carry adder% $he carry ripples from one stage to the other% For some input

patterns no rippling occurs while for some others rippling occurs all the way from LSB to

the )SB

$ABL+ ;%' ALU ,peration

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Fig ;%( M ipple 2arry Adder

position% $he propagation delay for such a structure also called the critical path is defined as

the worst case delay o&er all input patterns >7?% 6n case of a ripple carry adder the worst-case

delay happens when a carry generated at the least significant bit position propagates all the

way to the most significant bit% $he delay is then proportional to the number of bits in the

input words 8 and is gi&en by

where t2AH and tSU) are propagation delays from one stage to another% Following two

important conclusions are drawn from +5%

$his technology uses two le&els of polysilicon and two le&els of metal for interconnection%

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$he polysilicon at the le&el one is used for the gate and as well as for interconnection% $he

technology is used both for the design of analog and digital circuits% $he minimum sie

),SF+$ has '% mm channel width and '%( mm channel length respecti&ely% Figure

Low Power ALU Project Phase2

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