LIST OF FIGURES - u-bordeaux.frori-oai.u-bordeaux1.fr/pdf/2012/ROSSONI_MATTOS_DIEGO_2012.pdf ·...

Université Bordeaux 1

Les Sciences et les Technologies au service de l’Homme et de l’environnement

N° d’ordre : 4653

THÈSE

PRÉSENTÉE A

L’UNIVERSITÉ BORDEAUX 1

ÉCOLE DOCTORALE DES SCIENCES PHYSIQUES ET DE L’INGÉNIEUR

Par Diego, ROSSONI MATTOS

POUR OBTENIR LE GRADE DE

DOCTEUR

SPÉCIALITÉ : ELÉCTRONIQUE

DESIGN AND CHARACTERIZATION OF AN 8GSPS FLASH

ANALOG-TO-DIGITAL CONVERTER FOR RADIO

ASTRONOMY AND COSMOLOGY APPLICATIONS

Directeur de recherche : Alain Baudry

Soutenue le : 04 Décembre 2012

Devant la commission d’examen formée de :

M. BARTHELEMY, Hervé Professeur Univ. Sud Toulon Var Rapporteur

M. BAUDRY, Alain Professeur Univ. Bordeaux 1 (LAB) Directeur de thèse

M. BÉGUERET, Jean-Baptiste Professeur Univ. Bordeaux 1 Co-directeur de thèse

M. DEVAL, Yann Professeur Univ. Bordeaux 1 (IPB) Président

M. DUGOUJON, Laurent Ingénieur STMicroeletronics Examinateur

M. JESTIN, Guy Ingénieur Direction Générale de l’Armée Examinateur

M. LOUMEAU, Patrick Professeur ENST Paris Rapporteur

M. GAUFFRE, Stéphane Ingénieur Univ. Bordeaux 1 (LAB) Examinateur invité

M. PEDROZA, Jean-Louis Ingénieur Univ. Bordeaux 1 (CENBG) Examinateur invité

ABSTRACT iii

ABSTRACT

An Analog-to-Digital Converter (ADC) has been developed for astrophysical and

cosmological applications. This class of circuits demands, especially in the

millimeter wavelength domain, ultra wide bandwidths, ultra high sampling

frequencies and a low resolution. The “flash” architecture has been chosen for its

speed and bandwidth. This ADC samples at 8Gsps and it has been fabricated in

65nm CMOS technology from STMicroelectornics.

The design has been done in two steps. The first was the prototype of a track-and-

hold circuit. The second was the ADC. Both circuits have been characterized and

from these results some perspectives for further improvements have been proposed.

In order to achieve the final goal of the multi-bit ADC (6-bit resolution) we have

decided to design a first prototype with half the final resolution, namely a 3-bit

resolution ADC. Our idea was, with this first prototype, to conduct a first analysis

of the behavior of the integrated functional blocks and, consequently, find the

correct improvements required for the ADC final version.

English Title: Design And Characterization Of An 8gsps Flash Analog-To-Digital

Converter For Radio Astronomy And Cosmology Applications

Key-words: 65nm CMOS, ADC, Ultra-wide bandwidth, Instrumentation, Radio

astronomy, ALMA

RESUME v

RESUME

L‟exploration de l‟univers distant ou proche passe par l‟observation dans le domaine

des ondes optiques et radio. La radioastronomie en onde millimétrique et

submillimétrique s‟intéresse aux régions froides de l‟Univers et à la formation des

étoiles et galaxies. C‟est avec l‟objectif d‟améliorer la résolution angulaire des

instruments actuels d‟observation que le projet ALMA (Atacama Large

Millimeter/Sub-millimeterArray) a été créé pour observer l‟univers entre 30 GHz et 1

THz. Sa résolution angulaire sera meilleure que celle des plus grands télescopes

optiques. Ce projet, réalisé par un consortium international, consiste en un

ensemble de 66 antennes fonctionnant en interférométrie dans le désert de

l‟Atacama au nord du Chili. L‟endroit n‟a pas été choisi par hasard, mais pour son

très faible contenu en vapeur d‟eau favorable à la radioastronomie en onde

mm/sub-mm. L‟interféromètre ALMA sera inauguré le 13 mars 2013 pour une

pleine exploitation scientifique dès la fin de 2013. Cependant, ALMA devant

fonctionner pour les 30 à 50 années à venir, des recherches pour une deuxième

génération d‟instruments ALMA sont nécessaires ; en particulier, les circuits de

conversion Analogique-Digital à large bande sont au cœur des futurs dispositifs

d‟ALMA.

L‟utilisation des Convertisseurs Analogique-Numérique (CAN) en astrophysique

mm/submm au sol ou pour des applications spatiales présente des contraintes

spécifiques. Cette catégorie de circuits demande des bandes passantes très larges,

de très hautes fréquences d'échantillonnage ainsi qu‟une faible résolution

(relativement peu de bits). Souvent, une faible dissipation est aussi demandée. Les

CANs proposés sur le marché par les fabricants de convertisseurs ne satisfont pas à

toutes ces contraintes. Pour cela, le dessin d‟un ASIC (Application-Specific

Integrated Circuit) est nécessaire.

Le développement de ce projet de thèse s‟est fait dans le cadre d‟une collaboration

entre le Laboratoire d‟Astrophysique de Bordeaux (LAB), le laboratoire d‟Intégration

vi

du Matériel au Système (IMS) et le Centre d‟Etudes Nucléaires de Bordeaux-

Gradignan (CENBG), intéressé par un nouveau CAN pour ses applications en

cosmologie, car elles aussi demandent de très hautes fréquences d'échantillonnage

et des bandes passantes très larges.

Afin de remplir le cahier des charges demandé pour l‟application ALMA de deuxième

génération, l‟architecture flash a été retenue. Ce choix s‟explique pour la rapidité et

la bande passante de cette architecture. Les principales spécifications de ce

convertisseur analogique-numérique sont : une fréquence d‟échantillonnage de

8GHz ; une bande passante analogique d‟entrée de 8GHz (ce qui permet l‟utilisation

de deux fenêtres de Nyquist) ; une résolution de 6 bits. La technologie utilisée est la

CMOS 65nm de chez STMicroeletronics.

Les travaux de thèse ont commencé par une étude bibliographique approfondie de

l‟état de l‟art des CANs, ceux disponibles à l‟achat dans le marché, ou ceux en

phase de recherche mentionnés dans les publications techniques spécifiques. La

conception des circuits a été réalisée en deux étapes différentes. La première d'entre

elles a consisté à concevoir, fabriquer et caractériser un circuit échantillonneur-

bloqueur (EB). La deuxième a consisté à développer le convertisseur analogique-

numérique puis à le caractériser sur silicium au laboratoire.

Le premier circuit prototypé a été l‟échantillonneur-bloqueur. La schématique a été

développée conjointement par les équipes du LAB et du CENBG. Au démarrage, le

défi était d‟implémenter le dessin de cette schématique et d‟assurer le bon

fonctionnement du circuit après l‟introduction des composant parasites venant du

dessin. La schématique de l‟EB est entièrement différentielle permettant la

diminution du bruit et l‟augmentation de la vitesse. L‟échantillonneur-bloqueur est

composé de 4 blocs fonctionnels : l‟amplificateur d‟entrée, le buffer d‟horloge, le

cœur de l‟EB et le buffer de sortie. Les impédances d‟entrée, d‟horloge et de sortie

sont adaptées à 100Ω différentiels.

Après fabrication de l‟EB en CMOS 65nm, le circuit a été assemblé sur un circuit

imprimé de test (PCB) de deux manières différentes. Dans un premier cas on a

laissé l‟entrée et sortie différentielles „en l‟air‟ afin de permettre la caractérisation

avec des sondes et éliminer les parasites des fils de liaison ; dans le deuxième cas

RESUME vii

on a câblé le circuit sur PCB. C‟est l‟équipe d‟électronique du LAB qui a développé le

PCB.

Les résultats obtenus dans l‟étape de caractérisation de l‟échantillonneur-bloqueur

ont permis la validation de la méthode de conception grâce aux bonnes

performances obtenues en silicium, et validation aussi des modèles des composants

et de la technologie grâce à la bonne cohérence obtenue entre les résultats de

simulation et les mesures.

En plus de ses bonnes performances, la conception de ce premier prototype a aussi

donné des indices sur les améliorations pouvant lui être apporté. Ces indices ont

débouché dans la suite des travaux par une nouvelle version de l‟EB encore plus

performante.

Après la finalisation des étapes concernant l‟échantillonneur-bloqueur, notre

attention s‟est concentrée sur la conception du CAN. Nous avons commencé avec la

définition du „diagramme de blocs‟ et la conception de chaque bloc individuel avant

l‟assemblage du tout. Pendant cette phase, un choix au niveau de la technologie

CMOS de chez STMicroelectronics a été fait de façon a réduire l‟offset intrinsèque

des comparateurs.

Le diagramme de blocs final du CAN intègre l‟EB (la version utilisée est celle

fabriquée dans le premier prototype et pas celle optimisée après les mesures), un

amplificateur d‟entrée, les comparateurs, suivis par des bascules différentielles et

par l‟étage d‟encodage, un buffer d‟horloge et finalement les buffers LVDS de sortie.

Un démultiplexeur de 1 vers 4 a été intégré pour baisser la fréquence de sortie et

faciliter la caractérisation du convertisseur analogique-numérique en laboratoire.

Atteindre l'objectif final d‟un CAN multi-bits complet (6 bits sont visés) dès le

premier dessin a semblé ambitieux et il a été décidé d‟obtenir une première version

d‟un convertisseur offrant la moitié de la résolution initialement prévue (3 bits).

L'objectif de cette résolution réduite est de permettre l‟implémentation d‟un

prototype plus simple où l‟analyse du comportement des blocs fonctionnels intégrés

sera plus facile, pour ensuite passer à une deuxième, voire troisième version qui

finalement remplira le cahier des charges établi au démarrage du projet.

viii

Après la conception, l‟étape de dessin a demandé beaucoup d‟effort pour essayer de

minimiser l‟impact des parasites sur les performances du CAN. Les alimentations

de chaque bloc ont été dessinées de façon indépendante et en utilisant toutes les

couches métalliques disponibles afin d‟éviter les chutes de tension. Cette dernière

précaution découle de nos mesures du prototype de l‟EB où des chutes de tension

ont été observées sur les alimentations.

La caractérisation d‟un convertisseur d‟une telle complexité n‟est pas aisée.

Plusieurs „degrés de liberté‟ ont été laissés lors de la conception du CAN et même si

plusieurs éléments ont pu être caractérisés pendant les mesures les résultats

obtenus lors de ce travail ne permettent pas d‟expliquer tous les paramètres du

CAN ; et donc ne permettent pas sa complète caractérisation. Il resterait donc à

mener d‟autres essais avec d‟autres configurations et réglages pour les entrées de

contrôle.

Cependant, nos résultats actuels offrent des perspectives d'amélioration pour de

futures implémentations. Lors du passage d‟un circuit de 3 bits à 6 bits de

résolution certains blocs devront être remplacés, en particulier l‟EB dont une

nouvelle version existe, et d‟autres blocs devront être améliorés tandis que d‟autres

pourront rester tels qu‟ils sont implémentés actuellement.

Notre premier CAN à 3 bits, au final, a rempli la plupart de ses objectifs dans la

mesure où il a permis l‟observation et l‟évaluation de sa fonctionnalité et de ses

performances. Mais il n‟est pas directement utilisable pour remplacer les

convertisseurs ALMA actuels dans la perspective d‟une deuxième génération

d‟instruments d‟ALMA. Toutefois, le convertisseur analogique-numérique réalisé

dans cette thèse a ouvert le chemin et laissé des indices pour de futures

implémentations tant pour les applications sol que spatiales.

Titre en français : Conception et caractérisation d'un CAN Flash de fréquence

d'échantillonnage de 8 Géchantillons/seconde pour des applications en

radioastronomie

RESUME ix

Mots-Clés : CMOS 65nm, CAN, Très larges bandes passantes, Instrumentation,

Radioastronomie, ALMA

Les travaux de cette thèse ont été développés dans les locaux du Laboratoire IMS à

Talence et du LAB à Floirac.

Laboratoire de l’Intégration du Matériau au Système (IMS)

351, cours de la Libération

Université Bordeaux 1, Bât. A31

33405 Talence cedex – France

Laboratoire d’Astrophysique de Bordeaux (LAB)

2, rue de l'Observatoire - BP 89

33271 Floirac cedex – France

ACKNOWLEDGEMENTS xi

ACKNOWLEDGEMENTS

First of all, thank Région Aquitaine and STMicroelectronics for having made this

project possible.

Furthermore, I would like to thank my advisors, Professors Alain BAUDRY and Jean-

Baptiste BEGUERET for having trusted my capabilities at the beginning and for their

guidance during the development of this project. I hope all the discussions we have

had and the experiences we have shared have made you grow as much as I did.

Moreover, I cannot forget the patience you have shown during this last year of work.

It has been hard, but without your motivation it would have been even harder...

Thank you Professors Hervé BARTHELEMY and Patrick LOUMEAU for the special

attention you have dedicated for the evaluation of this work as well as the other

members of the jury, Yann DEVAL, Guy JESTIN, Laurent DUGOUJON, Jean-Louis

PEDROZA et Stéphane GAUFFRE for your interesting comments.

During all these years in the laboratory I have met lots of interesting people inside

those walls and I am glad that I could share this little bit of path with you. Thus, I

wish to thank specially the EC2 and CSH team members for all the wisdom I could

grab from you and all the transpiration drops we have left on the field together.

Thank you Bernardo, André, Dean, Yohan, Yoann, Nicos, Youss, Kamal, Sofiane, Nej,

Hassen, Paolo, Luca, Raffaele, PO, Cédric, Sophie, Andrée, Aya, Chama, Patrice,

Quentin, Romaric, François, Thierry, Yann, Hervé, Eric, Natalhie, Dominique, etc.

I could not forget the team from the LAB and CENBG. Stéphane, Cyril, Philippe,

Benjamin, Hervé, Pascal, Zahroudin, Abderhamane, Jean-Louis,Patrick, please

receive all my gratitude for you collaboration in this project. Stéphane, thank you for

the PCBs.

I would also like to thank my family for who the achievement of this work and the

proud that came with this success are far more precious than for anyone else. Thank

xii

you for your support during all these scholar years. I dedicate this entire work for

you. Mum, dad, brother, sorry about the distance...

For my wife, Catarina, I must state that no word is enough to express how important

you have been during this period when my attention and dedication have been split

and how difficult it would have been if you were not next to me helping to carry this

load. I love you so much.

Finally, my baby girl Carolina, my little angel. Thank you for the happiness you have

brought into my life. You make me want to go further and further and give the best of

me to offer you all you deserve.

LIST OF CONTENTS xiii

LIST OF CONTENTS

INTRODUCTION ................................................................................................................................. 1

CHAPTER I - Generalities ................................................................................................................... 5

I.I. The Analog-to-Digital Conversion ............................................................................................... 9

I.I.I. The Sampling Theorem ......................................................................................................... 10

I.I.II. Characteristics of the A/D Conversion ............................................................................. 11

I.I.III. Non-idealities of Analog-to-Digital Converters .............................................................. 14

I.I.IV. Data Converters Dynamic Performance .......................................................................... 19

I.II. The Application Description...................................................................................................... 23

I.II.I. Radio Astronomy Applications .......................................................................................... 23

I.II.II. Cosmology Applications .................................................................................................... 26

I.III. References ................................................................................................................................... 28

CHAPTER II – Study of the Specifications and the Architecture ................................................ 29

II.I. The Circuit Specifications ........................................................................................................... 33

II.II. Analog-To-Digital Converter Architectures .......................................................................... 35

II.II.I. Successive Approximation Register (SAR) ...................................................................... 35

II.II.II. Pipeline ADC ...................................................................................................................... 37

II.II.III. The Flash ADC .................................................................................................................. 38

II.II.IV. ADC Architectures Resume ............................................................................................ 39

II.II.V. The ADC State-of-the-Art ................................................................................................. 40

II.III. The Structure Of The ADC ...................................................................................................... 42

II.IV. References .................................................................................................................................. 43

CHAPTER III – Track-and-Hold Design ......................................................................................... 45

III.I. The Track-and-Hold (TAH) and the Flash ADC ................................................................... 49

III.I.I. The Track-and-Hold Specifications ................................................................................... 50

III.I.II. The Track-and-Hold Core ................................................................................................. 50

III.I.III. The Input Amplifier .......................................................................................................... 52

III.I.IV. The Clock Amplifier ......................................................................................................... 53

xiv

III.I.V. The Output Buffer .............................................................................................................. 53

III.II. The TAH Implementation ....................................................................................................... 55

III.III. The First Prototype Measurements ....................................................................................... 56

III.III.I. The DC Measurements ..................................................................................................... 57

III.III.II. The S-Parameters Characterization ............................................................................... 58

III.III.III. The Transient Measurements ........................................................................................ 59

III.III.IV. The Dynamic Performance............................................................................................ 60

III.III.V. The Global Performance ................................................................................................. 62

III.IV. Next Version of the TAH ........................................................................................................ 64

III.V. References .................................................................................................................................. 68

CHAPTER IV – Flash ADC Design .................................................................................................. 69

IV.I. The Flash ADC Design .............................................................................................................. 73

IV.I.I. The Input Amplifier ............................................................................................................ 74

IV.I.II. The Comparators ................................................................................................................ 75

IV.I.III. The Differential Flip-Flop (DFF) ..................................................................................... 77

IV.I.IV. The Encoder ....................................................................................................................... 77

IV.I.V. The Clock Amplification and Distribution ..................................................................... 79

IV.I.VI. The Demultiplexer ............................................................................................................ 81

IV.I.VII. The LVDS Buffer .............................................................................................................. 82

IV.II. The ADC Implementation ....................................................................................................... 83

IV.II.I. The TAH and the Input Amplifier ................................................................................... 83

IV.II.II. The Comparator ................................................................................................................ 84

IV.II.III. The DFF ............................................................................................................................. 85

IV.II.IV. The Clock Divider............................................................................................................ 86

IV.II.V. The Phase Controller ........................................................................................................ 86

IV.II.VI. The LVDS Buffer .............................................................................................................. 87

IV.II.VII. The ADC .......................................................................................................................... 87

IV.III. The First 3-bit Prototype Measurements .............................................................................. 90

IV.III.I. The DC Measurements ..................................................................................................... 90

IV.III.II. The Transient Measurements ......................................................................................... 91

IV.III.III. The Dynamic Performance............................................................................................ 95

IV.IV. Next Version of the ADC ....................................................................................................... 99

LIST OF CONTENTS xv

IV.IV.I. The TAH and the Input Amplifier ................................................................................. 99

IV.IV.II. The Comparators ............................................................................................................. 99

IV.IV.III. The Encoder .................................................................................................................. 100

IV.IV.IV. The Demultiplexer ....................................................................................................... 100

IV.V. References ................................................................................................................................ 102

CHAPTER V - Conclusion .............................................................................................................. 103

V.I. Theory and Motivations ........................................................................................................... 104

V.II. Design and Implementation ................................................................................................... 104

V.III. The List of Publications ......................................................................................................... 105

LIST OF FIGURES xvii

LIST OF FIGURES

Figure 1.1 – (a) Analog Input Signal (V); (b) Time discretization (V); (c) Amplitude

discretization (bits). ................................................................................................. 9

Figure 1.2 – Sampling Function. ........................................................................... 10

Figure 1.3 – Example of a sampled signal. ............................................................ 10

Figure 1.4 – Aliased spectrum. .............................................................................. 11

Figure 1.5 – Transfer function for a 3-bit ADC binary coded. ................................ 12

Figure 1.6 – ADC transfer function and the quantization error. ............................. 13

Figure 1.7 – Offset ADC transfer function and the quantization error. ................... 13

Figure 1.8 – DNL progression. ............................................................................... 15

Figure 1.9 – INL evolution. .................................................................................... 15

Figure 1.10 – Transfer function of an ADC exhibiting an offset error. .................... 16

Figure 1.11 – Transfer function of an ADC with gain error. ................................... 16

Figure 1.12 – Transfer function of an ADC presenting a hysteresis error. .............. 17

Figure 1.13 – Clock jitter and its effect on the sampling. ....................................... 18

Figure 1.14 – The clock sampling threshold. ......................................................... 19

Figure 1.15 – Evolution of the uncertainty error with the clock edge slope. ........... 19

Figure 1.16 – Representation of the SFDR on the spectrum. ................................. 20

Figure 1.17 – The gas cloud seen by: (a) an optical Telescope; (b) a millimeter-wave

Telescope. ............................................................................................................. 24

Figure 1.18 – Input signal: (a) chronological samples; (b) Gaussian amplitude

distribution. .......................................................................................................... 25

Figure 1.19 – ALMA system architecture. .............................................................. 20

Figure 2.1– Typical SAR ADC block diagram. ........................................................ 35

Figure 2.2– 3-bit SAR ADC conversion time-diagram. ........................................... 36

Figure 2.3 – (a) Pipeline unitary cell; (b) Pipeline ADC block diagram. ................... 37

Figure 2.4– Flash ADC block diagram. .................................................................. 38

Figure 2.5 – Time-interleaving chronogram. .......................................................... 40

xviii

Figure 2.6 – Architecture comparison in terms of the resolution and sampling

frequency. ............................................................................................................. 41

Figure 2.7 – Architecture comparison in terms of the input bandwidth and sampling

frequency. ............................................................................................................. 41

Figure 3.1 – TAH fully differential architecture. ..................................................... 49

Figure 3.2 – TAH core schematic. .......................................................................... 50

Figure 3.3 – TAH core during: (a) tracking-phase; (b) hold-phase. ......................... 51

Figure 3.4 – The evolution of the TAH output signal. ............................................. 52

Figure 3.5 – Schematic of the input amplifier. ....................................................... 52

Figure 3.6 – Schematic of the clock amplifier. ....................................................... 53

Figure 3.7 – Schematic of the output buffer. ......................................................... 54

Figure 3.8 – Die picture of the fabricated TAH. ...................................................... 55

Figure 3.9 – Picture of the PCB used for tests. ....................................................... 56

Figure 3.10 – Block diagram of the test bench. ...................................................... 57

Figure 3.11 – Picture of the PCB during the probe tests. ....................................... 58

Figure 3.12 – (a) S11 and (b) S22 characterization. .................................................. 58

Figure 3.13 – The gain of the TAH. ........................................................................ 59

Figure 3.14 – Hold-time measurements. ................................................................ 60

Figure 3.15 – Total harmonic distortion (THD) of the TAH for 8GHz sampling

frequency.. ............................................................................................................ 61

Figure 3.16 – SFDR for two input frequencies: (a) 3.9GHz; (b) 7.9GHz. .................. 61

Figure 3.17 – ENOB versus the input frequency. ................................................... 62

Figure 3.18 – TAH output: new design (solid line); previous version (dashed line). . 65

Figure 3.19 – TAH hold-time and respective voltage variation for: (a) 2GHz; (b)

4GHz; (c) 6GHz and (d) 8GHz sampling frequencies............................................... 66

Figure 3.20 – TAH spectral performance for 8GHz sampling frequency and:

1.875GHz (red line); 3.9875GHz (blue line); 5.625GHz (pink line) and 7.125GHz

(black line) input frequencies. ............................................................................... 66

Figure 4.1 – Flash ADC block diagram. ................................................................. 73

Figure 4.2 – Input amplifier block diagram. ........................................................... 74

LIST OF FIGURES xix

Figure 4.3 – (a) Input amplifier and (b) OTA schematics. ....................................... 75

Figure 4.4 – Stages of the comparator: (a) First stage with HPA transistors and

resistive load; (b) Active inductive load stage for capacitance cancellation and

bandwidth enhancement; (c) Active load amplifier stage. ....................................... 76

Figure 4.5 – Resistive reference ladder. ................................................................. 76

Figure 4.6 – Differential flip-flop schematic. .......................................................... 77

Figure 4.7 – (a) Full-custom differential NAND; (b) NANDs connection for the one-

hot encoding. ........................................................................................................ 78

Figure 4.8 – Clock divider by 4. ............................................................................. 79

Figure 4.9 – (a) g0; (b) g1; (c) g2 logic generation. .................................................. 80

Figure 4.10 – TAH clock enabler schematic. .......................................................... 81

Figure 4.11 – 1:4 demultiplexer. ............................................................................ 82

Figure 4.12 – Schematic of the LVDS buffer. ......................................................... 82

Figure 4.13 – Input amplifier: (a) gain and bandwidth; (b) compression point. ...... 83

Figure 4.14 – Comparator offset standard deviation for (a) LVTLP transistors; (b)

HPALP transistors. ................................................................................................ 84

Figure 4.15 – Comparator first stage layout. ......................................................... 85

Figure 4.16 – DFF functionality simulation. .......................................................... 85

Figure 4.17 – Clock divider by 4. ........................................................................... 86

Figure 4.18 – Clock phase control. ........................................................................ 86

Figure 4.19 – Eye diagram of the LVDS buffer output. .......................................... 87

Figure 4.20 – (a) ADC output reconverted to analog and (b) the respective spectrum.

............................................................................................................................. 87

Figure 4.21 – (a) ADC power consumption (b) ADC useful circuit power

consumption for 8GSPS. ....................................................................................... 88

Figure 4.22 – Die picture of the fabricated 3-bit ADC. ........................................... 89

Figure 4.23 – (a) Block diagram of the test bench; (b) PCB used for measurements..

............................................................................................................................. 91

Figure 4.24 – ADC power consumption distribution. ............................................. 91

Figure 4.25 – LVDS transient output for Fclk = 800MHz. ........................................ 92

xx

Figure 4.26 – LVDS transient output for Fclk = 8GHz. ............................................ 93

Figure 4.27 – LVDS output eye-diagram for FS=8GHz.. .......................................... 93

Figure 4.28 – Frequency of appearance of the output codes. ................................. 96

Figure 4.29 – Output spectrum of a 2.1-3.9GHz noise input. ................................ 96

Figure 4.30 – Average output spectrum obtained from 20 individual measurements

for a 2.1-3.9GHz noise input signal. ...................................................................... 97

Figure 4.31 – Comparators distribution for compensating the random process

gradients on the 4-bit thermometer transfer function. ......................................... 100

LIST OF TABLES xxi

LIST OF TABLES

Table 1.1 – The DNL .............................................................................................. 14

Table 1.2 – The INL ............................................................................................... 15

Table 2.1 – ADC specifications summary ............................................................... 34

Table 2.2 – ADC Architectures Characteristics ...................................................... 39

Table 3.1 – TAH DC Measurements ....................................................................... 57

Table 3.2 – TAH Performance Summary ................................................................ 63

Table 3.3 – State-Of-The-Art Comparison .............................................................. 63

Table 4.1 – Thermometer to One-Hot Conversion .................................................. 78

Table 4.2 –One-Hot to Gray Conversion ................................................................ 78

Table 4.3 – TAH + Input Amplifier Performance summary ..................................... 83

Table 4.4 – 3-bit Gray Encoding ............................................................................ 95

Table 4.5 – Dynamic performance ......................................................................... 97

1

INTRODUCTION

INTRODUCTION 3

The development of the integrated circuits processes and design tools has brought

enormous improvements in performance and in scale of integration. Consequently,

the design of circuits for a specific application (ASIC – Application-Specific

Integrated Circuit)has become easier and more realistic. Thus, instead of using

general-purpose cells or circuits, which can fit many designs without being

optimized to a specific task, full-custom designs allow the enhancement of global

performance by eliminating unnecessary functionalities to reach the optimal trade-

off.This customization is even more important to analog circuits, where the word

“trade-off” is a part of daily vocabulary.

Systems used in ultra-high frequencies for radio astronomy applications have

particular demands which made the customization mandatory. Therefore, the work

presented in the following chapters has the customization as background.The

relative small resolution and the large bandwidth implicated in the design make the

use of general-purpose circuits impossible.

In this context, Chapter I starts presenting the theory and the characteristics of an

analog-to-digital conversion and its non-idealities, such as the intrinsic

quantization noise. This chapter defines also the needs of the application in radio

astronomy and in cosmology as well as the behavior of the signal of interest.

Chapter II enters in the analog-to-digital converter domain by showing several fast

architectures and evaluating their strengths and weakness and comparing them to

the wanted characteristics for the application.

The following chapters, Chapter III and Chapter IV, present the design strategies

and decisions, measurement results and perspectives for further developments of

the track-and-hold and the analog-to-digital converter, respectively. Both designs

have been fabricated in 65nm CMOS technology from STMicroeletronics.

Final considerations of the work and its achievements are presented in the

Conclusion.

5

CHAPTER I - GENERALITIES

Thisfirst chapter introduces the analog-

to-digital conversion, itscharacteristics

and principlesand alsothe non-idealities

inherent to any design that limit its

performances. The needs that motivate

this design are also explained in this

chapter as well as theproperties of the

environment surrounding the device and

the signal to be digitized. Some radio

astronomy and cosmology applications

are briefly commented.

6 Contents

CHAPTER I - GENERALITIES 7

CONTENTS

I.I. The Analog-to-Digital Conversion ....................................................................... 9

I.I.I. The Sampling Theorem ............................................................................... 10

I.I.II. Characteristics of the A/D Conversion....................................................... 11

I.I.III. Non-idealities of Analog-to-Digital Converters ........................................... 14

I.I.III.I. Linearity Error .................................................................................... 14

I.I.III.II. Offset Error ........................................................................................ 16

I.I.III.III. Gain Error ........................................................................................ 16

I.I.III.IV. Hysteresis Error ................................................................................ 17

I.I.III.V. Clock Related Errors .......................................................................... 17

I.I.IV. Data Converters Dynamic Performance .................................................... 19

I.I.IV.I. Spurious-Free Dynamic Range ............................................................ 20

I.I.IV.II. Total Harmonic Distortion .................................................................. 20

I.I.IV.III. Signal-to-Noise Ratio......................................................................... 21

I.I.IV.IV. Signal-to-Noise Ratio and Distortion ................................................. 21

I.I.IV.V. The Effective Number of Bits .............................................................. 21

I.II. The Application Description ............................................................................ 23

I.II.I. Radio Astronomy Applications ................................................................... 23

I.II.I.I. The signal of Interest ............................................................................ 25

I.II.I.II. The ALMA Achitecture ......................................................................... 26

I.II.II. Cosmology Applications ............................................................................ 26

I.III. References ..................................................................................................... 28

8 The Analog-to-Digital Conversion


I.I. THE ANALOG-TO-DIGITAL CONVERSION

In physics, all the measured quantities (temperature, weight, time, distance, etc.)

fluctuate from one value to another one continuously. This is a specificity of analog

signals. An Analog-to-Digital Converter (ADC), also known as a digitizer, is the

device that translates the real world signals (analog) into „computers language‟

(digital). This conversion mechanismallows the computers to processand interact

with these signals.The Analog-to-digital (A/D) conversion consists in evaluating the

amplitude of a given signal and making anassociation between the sampled

amplitude and one digital value. Figure 1.1 shows the conversion principle in two

steps:the sampling of the input signal and the quantization of the samples

amplitude.

t

V

0

1

2

3

4

TS

t

V

0

1

2

3

4

TS

t

bits

00

01

10

11

(a) (b) (c)

Figure 1.1 – (a) Analog Input Signal (V); (b) Timediscretization (V); (c) Amplitude discretization (bits).

The two discretizations shown in figure 1.1represent the two main characteristics of

an A/D converter. The first important parameter is the sampling frequency, 𝑓𝑆 (and

the sampling period, 𝑇𝑆, linked to 𝑓𝑆by the equation 1.1). The analog signals varying

continuously, the higher the sampling frequency is, more samples will be takenin a

given time window and, consequently, more precise the conversion will be. The

second characteristic is the resolutionwhich is directly associated to the accuracy of

the conversion.Number of bits increases exponentially the number of output codes,

thus improving the resolution.

𝑇𝑆 =1

𝑓𝑆 (1.1)

Theoretical principles behind the A/D conversion will be explained in the following

sections.


I.I.I. THE SAMPLING THEOREM

First of all, the sampling theorem is presented. Shannon statedin [1.1]:

If a function 𝑓(𝑡) contains no frequencies higher than 𝑊 Hz, it is

completely determined by giving its ordinates at a series of points

spaced 1/2𝑊 seconds apart.

Mathematically, when an analog signal is sampled, the transient signal is

multiplied by a sampling function (figure 1.2)formed by periodic Dirac pulses. This

operation can be seen in equation 1.2. The product is a stream of impulses whose

amplitudes are those ofthe analog signal at a given instant 𝑡(see figure 1.1(b)).

t

S(t)

1

TS 2TS 3TS 4TS 5TS 6TS

Figure 1.2 – Sampling Function.

𝑣𝑆𝑎𝑚𝑝𝑙𝑒𝑑 𝑡 = 𝑣 𝑡 ∙ 𝑠 𝑡 = 𝑣 𝑡 ∙ 𝛿 𝑡 − 𝑛𝑇𝑆

+∞

𝑛=−∞

(1.2)

The Fourier transform is presented in equation 1.3.

𝑉𝑆𝑎𝑚𝑝𝑙𝑒𝑑 𝑓 = 𝑉 𝑓 ∗1

𝑇𝑆 𝛿 𝑓 −

𝑘

𝑇𝑆

+∞

𝑘=−∞

=1

𝑇𝑆 𝑉 𝑓 −

𝑘

𝑇𝑆

+∞

𝑘=−∞

(1.3)

Equation 1.3 finally shows that input signal spectrum becomes periodic. Figure 1.3

shows the spectrum of a sampled signal𝑣(𝑡).

f

V(f)

-2FS -FS 0 FS 2FS 3FS-3FS

Figure 1.3 – Example of a sampled signal.


In order to avoid the spectrum aliasing, the input signal must be bandwidth limited

at 𝑓𝑆/2 Hertz(also known as Nyquist frequency) while sampling frequency is 𝑓𝑆 ,

accordingly to the Sampling Theorem. This property is due to the periodicity of the

resulting spectrum. Figure 1.4 represents a spectrum of a sampled signal

disrespecting this condition and then, unable to be perfectlyrebuilt.

f

V(f)

-2FS -FS 0 FS 2FS 3FS-3FSFS

2-FS

2

Figure 1.4 – Aliased spectrum.

The value of the sampling frequency relative to the maximum input

frequencydefines another characteristic of a sampled signal:

If 𝑓𝑆 > 2𝑓𝐼𝑁𝑀𝐴𝑋 it means an oversampling system. Oversampling a signal

improves resolution and reduces noise;

If 𝑓𝑆 = 2𝑓𝐼𝑁𝑀𝐴𝑋 system is sampled at Nyquist condition;

If 𝑓𝑆 < 2𝑓𝐼𝑁𝑀𝐴𝑋 system is subsampled and in this case, aliasing occurs.

Depending on input signal bandwidth, signal can still be

reconstructed. This method is called bandpass sampling [1.2].

I.I.II. CHARACTERISTICS OF THEA/DCONVERSION

The transfer function of an ideal ADC can be represented as in figure 1.5. It

represents the digital output code versus the analog input. The maximum value on

the x-axis can be interpreted as the maximum tolerated amplitude for the input

signal and it is called the Full-Scale (FS).The number of levels in the digital code

depends on the number of bits (𝑛)of the conversion; in other words it depends on

the resolution of the ADC. The minimum analog value that causes a variation in

digital code is called quantum (𝑞) or LSB (Less Significant Bit). The relation between

these parameters is given in equation 1.4.


𝐹𝑆 = 𝑞2𝑛 ⇒ 𝑞 =𝐹𝑆

2𝑛 (1.4)

Analog Input (V)

Digital Output Code

000001010011100101110111

0 1 2 3 4 5 6 7 8

Ideal Transfer Function

Real Transfer Function

Figure 1.5 – Transfer function for a 3-bit ADC binary coded.

Even for an ideal ADC, the transfer function generates an error called quantization

error. It comes from the fact that many analog values can be represented by the

same digital code and when an analog signal is quantized to a digital code (𝑥𝑞 ), it

can be interpreted as the original analog value (𝑥) plus a quantization error (𝑒𝑞 )

(equation 1.5). Figure 1.6 shows the progression of the quantization error during an

A/D conversion. It swings from0to – 𝐿𝑆𝐵, which empirically becomes the uncertainty

of the ADC.Commonly, an offset of 𝐿𝑆𝐵/2 is introducedto the transfer function so

the quantization error can be expressed as a function centered in 0 with an

uncertainty varying from 𝐿𝑆𝐵/2 to −𝐿𝑆𝐵/2 (figure 1.7). Mathematically, the

quantization error can be seen as a sawtooth function with the amplitude between

𝑞/2and−𝑞/2.

𝑥𝑞 t = 𝑥 𝑡 + 𝑒𝑞 t ⇒ 𝑒𝑞 t = 𝑥𝑞 t − 𝑥 𝑡 (1.5)

The quantization error is also known as the quantization noise and it is intrinsic to

the ADC behavior. In this case, Signal -to-Noise Ratio (SNR) can be obtained from a

ratio between the RMS value of the useful signal (x) and the RMS value of the

quantization error (e) (equation 1.6).

𝑆𝑁𝑅 = 20𝑙𝑜𝑔 𝑉𝑅𝑀𝑆 𝑥

𝑉𝑅𝑀𝑆 𝑒 (1.6)


Analog Input (V)

Digital Output Code

000001010011100101110111

0 1 2 3 4 5 6 7 8



Analog Input (V)0 1 2 3 4 5 6 7 8

Quantization Error (V)

-LSB0

Figure 1.6 – ADC transfer function and the quantization error.

Analog Input (V)

Digital Output Code

000001010011100101110111

0 1 2 3 4 5 6 7 8



Analog Input (V)

0 1 2 3 4 5 6 7 8

Quantization Error (V)

-LSB/2

LSB/2

-LSB

Figure 1.7 – Offset ADC transfer function and the quantization error.

Considering the useful signal is a sinusoid with unitary amplitude, its RMS value is

represented by equation 1.7, while the RMS valueof the quantization noise is given

by equation 1.8.

𝑉RMS 𝑥 =VPEAK

2=

FS/2

2=𝑞2𝑛

2 2 (1.7)

𝑉𝑅𝑀𝑆 𝑒 =𝑉𝑃𝐸𝐴𝐾

3=𝐿𝑆𝐵/2

3=

𝑞

2 3 (1.8)


Finally, the SNR is expressed in the equation 1.9.

𝑆𝑁𝑅 = 20𝑙𝑜𝑔 𝑞2𝑛 2 2

𝑞 2 3 = 20𝑙𝑜𝑔 2𝑛 + 20𝑙𝑜𝑔

3

2 = 6.02𝑛 + 1.76 (1.9)

I.I.III. NON-IDEALITIES OF ANALOG-TO-DIGITAL CONVERTERS

When an ideal ADC is designed and fabricated, undesired effectsoccur and

deteriorate its performances. These effects are listed below.

I.I.III.I. LINEARITY ERROR

When physically implemented, the ADCs can present a non-linear resolution that is

originally created by an insufficient control of the quantization references or

comparators, resulting in a variable LSB. The linearity error can be evaluated in two

different ways:DNL and INL, meaning the Differential and the Integral

Nonlinearities, respectively.

I.I.III.I.I. THE DIFFERENTIAL NONLINEARITY

The DNL is defined by equation 1.10, which represents the relation between the

idealquantum and the real one. Table 1.1 shows an example of the LSB transition

voltages of both ideal and real 3-bits resolution ADC, and the associated DNL.

Figure 1.8 shows the evolution of the DNL, quantified asfunction of the LSB.

𝐷𝑁𝐿𝑖 = 𝑉𝑖+1 − 𝑉𝑖𝐿𝑆𝐵𝐼𝐷𝐸𝐴𝐿

− 1,𝑤𝑕𝑒𝑟𝑒 0 < 𝑖 < 2𝑛 − 2 (1.10)

TABLE 1.1 – THE DNL

Transition Transition voltage (mV)

DNL (mV) Ideal ADC Real ADC

0 LSB 100 98 -0.02 LSB 2LSB 200 197 -0.01 2LSB 3LSB 300 303 0.06 3LSB 4LSB 400 401 -0.02 4LSB 5LSB 500 498 -0.03 5LSB 6LSB 600 600 0.02 6LSB 7LSB 700 699 -0.01


Figure 1.8 – DNL progression.

I.I.III.I.II. INTEGRAL NONLINEARITY

The INL is defined as the integration of the DNL (equation 1.11). Table 1.2 adds the

INL column inthe previous Table 1.1. The evolution of the INL can be seen at

figure 1.9. The INL is evaluated in function of the LSB, but, as the DNL it can be

expressed as a function of the FS.

𝐼𝑁𝐿𝑖 = 𝐷𝑁𝐿𝑗𝑗≤𝑖

(1.11)

TABLE 1.2 – THE INL

Transition Transition voltage (mV)

DNL (mV) INL (mV) Ideal ADC Real ADC

0 LSB 100 98 -0.02 -0.02 LSB 2LSB 200 197 -0.01 -0.03 2LSB 3LSB 300 303 0.06 0.03 3LSB 4LSB 400 401 -0.02 0.01 4LSB 5LSB 500 498 -0.03 -0.02 5LSB 6LSB 600 600 0.02 0.00 6LSB 7LSB 700 699 -0.01 -0.01

Figure 1.9 – INL evolution.

-7

-5

-3

-1

1

3

5

7

1 2 3 4 5 6 7D

NL (%

LSB

)

Transition between codes

-4

-3

-2

-1

0

1

2

3

4

1 2 3 4 5 6 7

INL (%

LSB

)

Transition between codes


I.I.III.II. OFFSET ERROR

Offset error appears when the real transfer function characteristics match the ideal

case but the transfer function is shifted along the x-axis (figure 1.10). Basically it

means that the quantums q between each comparator arepreserved, but are not

equally distributed within the FS. This error could be associated to the behavior of

the ADC comparators or to their voltage references or even to the stages preceding

the comparators. If the input signal common-mode voltage is not the same as the

center of the FS, the signal converted data will have an offset.

Analog Input (V)

Digital Output Code

000001010011100101110111

0 1 2 3 4 5 6 7 8

Ideal ADC

VO

FF

SET

Offset ADC

Figure 1.10 – Transfer function of an ADC exhibiting an offset error.

I.I.III.III. GAIN ERROR

When the slopeof the real and the ideal transfer function are not the same, thenthe

real ADC shows a gain error (figure 1.11). Practically, the gain error is caused by a

variable quantum between each digital code.It can be generated once again by the

behavior of the comparatorsor the voltage references or some distortionsfrom the

earlier blocks.

Analog Input (V)

Digital Output Code

000001010011100101110111

0 1 2 3 4 5 6 7 8

Ideal ADC

ADC with gain error

Gain Error

Figure 1.11 – Transfer function of an ADC with gain error.


I.I.III.IV. HYSTERESIS ERROR

Generally associated with the comparators, the hysteresis error is illustrated by

thetransition between two different digital codes which variesaccording to the

pathof the input analog signal. Figure 1.12 represents this error.

Analog Input (V)

Digital Output Code

000001010011100101110111

0 1 2 3 4 5 6 7 8

Ideal ADC

Hysteresis Error

Figure 1.12 – Transfer function of an ADC presenting a hysteresis error.

I.I.III.V. CLOCK RELATED ERRORS

Sampling switching cadence is given by the edges of a square signal at 𝑓𝑆 called

clock; the characteristics of this signal will impact the A/D conversion process and

can produce errors.

The action of sampling is characterized by the interaction between the input signal

and the clock signal. Ideally, the duration of this interaction is zero. In reality, this

time is not zero and is called the aperture time. So the actual value of the sampled

voltage at the end of the aperture time is a function of the input signal slew rate

and the errors introduced by the switching itself.

I.I.III.V.I. APERTURE DELAY

When the sampling process starts (𝑡𝑖 ), triggered by the clock, the input signal

voltage is 𝑉𝑠𝑎𝑚𝑝𝑙𝑒𝑑 . However, considering the existence of the aperture time, at the

end of the sampling process (𝑡𝑓 ) the sampled voltage is 𝑉𝐴𝑉𝐺 (where 𝑉𝐴𝑉𝐺 is, in a first-

order model,the average of the input voltage during the aperture time).So, we can

consider that the clock has triggeredthe sampling process at the instant (𝑡𝑖 + 𝑡𝑑 )

that the input voltage was 𝑉𝐴𝑉𝐺 , instead of 𝑉𝑠𝑎𝑚𝑝𝑙𝑒𝑑 . The aperture delay, is thus

defined as the time between the real sampling and the considered sampling

instants, in this case, 𝑡𝑑 .


I.I.III.V.II. CLOCK JITTER

The clock signal, as other signals, is disturbed by noise coming from different

sources as intrinsic thermal noise and power supply embedded noise.The noiseover

the clock changesits edges position which will randomly vary following a Gaussian

distribution around the ideal edge position. This effect is defined as clock jitter (see

figure 1.13)

t

V

t

Clock Jitter

Gaussian

Distribution

Sa

mp

le E

rro

r

Ga

ussia

n

Dis

trib

utio

nClock

Edge

Variable P

osition

Figure 1.13 – Clock jitter and its effect on the sampling.

The clockjitteris an important error source because, as foraperture delay, the

sampling instant is changed.

I.I.III.V.III. APERTURE UNCERTAINTY

Theidealthreshold voltage for sampling an ADC is the clock average voltage, in this

case 𝑉𝐷𝐷/2 (figure 1.14). The concept of the aperture uncertainty is related to a

variation of the actual threshold. Such a variation is due to the non-infinite clock

slopewhich makes the clock to beclose to the threshold voltage for a longer time.

This fact increases the sampling zone and error. Figure 1.15 shows the evolution of

the uncertainty error with the clock edge slope;from figure 1.15(a) which shows the

ideal sampling instant which produces a null error to figure 1.15(d) representing

the smallest clock edge slope and the biggest sampling zone.


t

VCLOCK

VDD

0

VDD

2

Figure 1.14 – The clock sampling threshold.

t

VCLOCK

VDD

0

t

V

No error

t

VCLOCK

VDD

0

Sampling Zone

t

V

Sampling Error

(a) (b)

t

VCLOCK

VDD

0

Sampling Zone

t

V

Sampling Error

t

VCLOCK

VDD

0

Sampling Zone

t

V

Sampling Error

(c) (d)

Figure 1.15 – Evolution of the uncertainty error with the clock edge slope.

I.I.IV. DATA CONVERTERS DYNAMIC PERFORMANCE

During the data conversion process the errors presented in the previous sections

and other non-idealities can appear and disturb the A/D conversion, impacting its

dynamic performances.Effects as distortion and noise can be identified on the

spectrum of the converted signal. Consequently, the Fast Fourier Transform (FFT)

comes up as the main tool for the evaluation of the converter behavior.


The ADC characteristics permitting the evaluation will be described below. The

following definitions are fully relevant if the input signal is a pure sine wave. They

are, however, of interest for the broad band signals which correspond to the radio

astronomy case.

I.I.IV.I. SPURIOUS-FREE DYNAMIC RANGE

Considering the spectrum of a converted signal, the difference between the useful

signal power and the highest spectral component power inside the useful

bandwidth is called Spurious-Free Dynamic Range (SFDR). Figure 1.16 represents a

given output spectrum and the respective SFDR.The SFDR is generally expressed in

dBc, or decibels relative to the carrier.

f

PdBc

SFD

R

Figure 1.16 – Representation of the SFDR on the spectrum.

I.I.IV.II. TOTAL HARMONIC DISTORTION

The Total Harmonic Distortion (THD) is the relation between the powers of all the

harmonics of the input signal and the fundamental frequency power, see equation

1.12, where 𝐻𝑘 stands for the voltageamplitude of the signal harmonics and 𝐻0 is

the fundamental frequency signal voltage amplitude.Generally expressed in dB or

dBc (expressed in % for audio systems), this relation means that the more distortion

the signal suffers, the higher the THD is.

𝑇𝐻𝐷 𝑑𝐵 = 20log

𝐻𝑘

2𝑘≥1

𝐻0

(1.12)


I.I.IV.III. SIGNAL-TO-NOISE RATIO

The relation between the meaningful signal power, without harmonics, and the

environmentnoise power (either quantification noise or not) is called Signal-to-Noise

Ratio (SNR) and is expressed by equation 1.13. The SNR is expressed in dB.

𝑆𝑁𝑅 𝑑𝐵 = 10log 𝑃𝑠𝑖𝑔𝑛𝑎𝑙

𝑃𝑛𝑜𝑖𝑠𝑒 (1.13)

The overall SNR of an ADC must take in account two components, the first coming

from the digitizing action and its quantization noise and the second coming from

the clock jitter. Equations 1.14 and 1.15 present the SNR from jitter and the total

SNR equations [1.3].

𝑆𝑁𝑅𝑗𝑖𝑡𝑡𝑒𝑟 𝑑𝐵 = −20log 2𝜋𝑓𝑖𝑛𝑚𝑎𝑥 ∆𝑡𝑅𝑀𝑆 (1.14)

𝑆𝑁𝑅𝑇𝑂𝑇𝐴𝐿 𝑑𝐵 = −10log 10 −𝑆𝑁𝑅𝐴𝐷𝐶

10 + 10

−𝑆𝑁𝑅𝑗𝑖𝑡𝑡𝑒𝑟

10 (1.15)

I.I.IV.IV. SIGNAL-TO-NOISE RATIO AND DISTORTION

The input signal harmonics can be incorporated into the equation 1.15. In this

case, the final quantity is the Signal-to-Noise and Distortion (SINAD) also called

Signal-to-Noise and Distortion Ratio (SNDR) or even Total Harmonic Distortion plus

Noise (THD+N). SINAD is calculated from equation 1.16, where 𝑃𝑠𝑖𝑔𝑛𝑎𝑙 is the power

of the fundamental signal and 𝑃𝑠𝑖𝑔𝑛𝑎𝑙 is the power of all harmonics. The SINAD can

also be expressed in terms of the THD and the SNR (equation 1.17).

𝑆𝐼𝑁𝐴𝐷 𝑑𝐵 = 10log 𝑃𝑠𝑖𝑔𝑛𝑎𝑙

𝑃𝑛𝑜𝑖𝑠𝑒 + 𝑃𝑑𝑖𝑠𝑡𝑜𝑟𝑡𝑖𝑜𝑛 (1.16)

𝑆𝐼𝑁𝐴𝐷 𝑑𝐵 = −10log 10 𝑇𝐻𝐷

10 + 10 −𝑆𝑁𝑅

10 (1.17)

I.I.IV.V. THE EFFECTIVE NUMBER OF BITS

Finally, the actual resolution performance of a given ADC can be compared to the

ideal one. Considering equation 1.9 where the SNR generated by the quantization


noise is given in function of the number of bits, it is possible to think otherwise and

say that the effective number of bits (ENOB) is defined as the number of bits that

generate a given SNR. However, SINAD is used instead of SNR in order to take

generated noise and distortion into account. By reordering the equation 1.9 and by

replacing the SNR by the SINAD, the ENOB is given by equation 1.18.

𝐸𝑁𝑂𝐵 =𝑆𝐼𝑁𝐴𝐷 − 1.76

6.02 (1.18)


I.II. THE APPLICATIONDESCRIPTION

The expansion of digital systems applications, due to their increasing processing

power and the shrinking technologies that allow a better integration, has eliminated

some analog functional blocks pushing the data conversion to rise in speed, so the

signal can be processed earlier in the radio communications transmission

chain[1.4][1.5].

The main context of this work isthe project calledAtacama Large Millimeter/Sub-

millimeter Array (ALMA). This international project consists in deploying 66

antennas in the Atacama Desert in Chile at an elevation of 5000m. It will improve

the spatial resolution and will observe in the frequency range from 30 to

950GHz.The end of construction is 2013 while in the mean time science

observations were started as early as 2011 with a subset of antennas.The ALMA

configurable antennas can simulate a single 16km diameter antenna and the data

provided by the measurements are processed in the main building at 5000m by a

special computer, called the correlator sub-system, capable of executing 17P

operationsper second [1.6].

For radio astronomy applications, the data is integrated over a certain amount of

time (typically from seconds to hours) in order to eliminate the signal intrinsic

noise. The goal of this work is to design a new and faster ADC allowing to reduce

the number of analog signal processing stages prior to correlation.

In cosmology, studies are performed for wide bandwidth signals and so this new

fast ADC design should fulfill the instrumental needs.

I.II.I. RADIO ASTRONOMY APPLICATIONS

Millimeter-wave radio telescopes allow the observation of the interstellar and

circumstellar clouds medium containing massive quantities of sub-micrometric

particles of dust, as well as atoms and molecules, with a simple or a high level of

complexity (prebiotic molecules).These observations are necessaryfor the study of

the physical-chemical mechanisms inside these molecular clouds and for the

understanding of the mechanisms behind the creation of the stars and their planets

being formed in our galaxy and in other galaxies.

24 The ApplicationDescription

From a cosmological point of view, it is known that the raw material of stars and

galaxies was generated in the first instants of the Universe history. The

observations made in the sub-millimeter or far infrared domains bring information

about the radiated energy and the evolution processes of galaxies as well as the

evolution of matter since the beginning of the Universe until now.Much information

about the cold and dark interstellar medium cannot be provided by classical optical

telescopes. Figure 1.17 shows the example of a coldgas cloud in space observed by:

(a) an optical telescope; (b) a millimeter-wave telescope. We can see that the radio

telescope provides a different image of the observed zone and samples the actual

radiation emitted by the cold cloud whereas the optical image shows a void (dark

cloud) surrounded by field stars.

(a) (b)

Figure 1.17 – The gas cloud seen by: (a) anoptical Telescope; (b) amillimeter-wave Telescope.

Existing radio telescopes are generally equipped with particular spectrometers

called correlators and with low resolution (2 or 3 output bits) and high sampling

frequency (from some MHz up to fewGHz) ADCs.The ADC low resolution is fully

acceptable because the signal coming from space which is buried within the

equipment intrinsic Gaussian noise will decrease with the integration time (up to a

few hours). In radio astronomy time integration is the usual way to extract the

signal of interest radiated by the observed source from the system noise.

Desired ADC features for radio astronomy applications are not exactly the same as

those provided by the classical mass market which prefers a greater resolution to a

high sampling frequency. Moreover, low-power criteria are important in radio

astronomy for large projects such as ALMA or to allow satellites embedded scientific

applications in the mm/sub-millimeter domain.


I.II.I.I. THE SIGNAL OF INTEREST

The input signal is characterized as a Gaussianwhite noise (see figure 1.18). Its

amplitude distribution is Gaussian and centered at 0 and it has aflat power spectral

density. The latter quantity is directly proportional to the antenna system

temperature, that is to say the receiver noise temperature which is dominant and

characterizes the receiver noise performance and the observing frequency.

(a) (b)

Figure 1.18 – Input signal: (a) chronological samples; (b) Gaussian amplitude distribution.

Am

plit

ud

e

Am

plit

ud

e

Frequency

Time

26 The ApplicationDescription

I.II.I.II. THE ALMA ARCHITECTURE

The current implementation of the ALMA project is presented in figure 1.19.Each

antenna is composed by the following heterodyne architecture. First, the ultra high

input frequencies are down converted to the 4-12GHz intermediate frequencies in

both polarizations. Then, this 8GHz bandwidth is treated by 4 ADCs with input

bandwidths going from 2-4GHz.Faster ADCs allowing the direct conversion of the 4-

12GHz bandwidth are the object of the researches for the ALMA second generation

back-end sub-system.

AmpPolaritazion 1

Mixer

AmpPolaritazion 2

Mixer

Mixer and

Filters

Mixer and

FiltersADC

ADC...on the way

to correlators

...on the way

to correlators

4x

2-4GHz

4x

2-4GHz

30

GH

z –

90

0G

Hz

4-12GHz

4-12GHz

Figure 1.19 – ALMA system architecture.

I.II.II. COSMOLOGY APPLICATIONS

The working groups “NEUTRINO”and“BASSES RADIOACTIVITES”from the CENBG

study the neutrino properties and thus need to use low background noise gamma

spectroscopy. These research activities are fromthe SuperNEMO project which tries

to highlight the double beta disintegration without neutrino emission, which

is not allowed by the Standard Model. The observation of these phenomena would

prove the non-conservation of the lepton number.

Many mechanisms can cause this disintegration: light neutrino exchanges, heavy

neutrinos, marjorons or super symmetric particles. These mechanisms are possible

if the neutrino was a marjoron particle identical to its antiparticle. In the light

neutrino exchanges, the disintegration also allows to access to the neutrino

mass scale by measuring the effective mass “m” which is linked to the half-life of

process.


Detection of two electrons whose energy sum is equal to the transition energy is the

experimental sign of the degeneration. The angular distribution between two

electrons and their individual energypermit the identification of the involved

mechanisms. The goal of the project would be to obtain an energy resolution better

than 8%, at 1Mev, with a timeuncertainty smaller than 100ps.The use of an ADC

with a bandwidth of about 10GHz (100ps period) would providedirectly

thetimestamps of thesignalsgeneratedbythe calorimeter.

28 References

I.III. REFERENCES

[1.1] C. E. Shannon, “Communications in the presence of noise”, Proc. IRE, vol. 37,

pp. 10-21, Jan. 1949.

[1.2] R. G. Vaughan, N. L. Scott, and D. R. White, “The Theory of Bandpass Sampling,” in IEEE Transactions on Signal Processing, Sept. 1991, vol. 39, no 9, p. 1973- 1984.

[1.3] C. Azeredo-Leme, “Clock jitter effects on sampling: A tutorial,” IEEE Circuits Syst. Mag., vol. 11, no. 3, pp. 26–37, Third Quarter, 2011.

[1.4]Y. C. Jang, S. H. Park, S.C. Heo, and H. J. Park, “An 8 GS/s 4 Bit.340mW CMOS Time Interleaved Flash Analog-to-Digital Converter,” IEICE Trans. Fundamentals, vol. E87-A, no.2, pp. 350-356, February 2004.

[1.5]F. Vessal and C.A.T. Salama, “An 8-Bit 2-Gsample/s Folding-Interpolating Analog-to-Digital Convert in SiGe Technology,” IEEE J. Solid-State Circuits, vol. 39, No. 1, pp. 238-241, Jan. 2004.

[1.6]A. Baudry, “The ALMA Correlators”, ALMA Newsletter, no 7, Jan. 2011.

29

CHAPTER I I - STUDY OF THE

SPECIFICATIONS AND THE ARCHITECTURE

During Chapter II, the ADC features will

be specified. Afterward, some familiar

ADC architectures are presented and

each of their main characteristics

explained. Then, the choice of the

architecture of the present design will be

made based on the particularities of the

structures of the State-Of-The-Art.

30 Contents

CHAPTER II – STUDY OF THE SPECIFICATIONS AND THE ARCHITECTURE

31

CONTENTS

II.I. The Circuit Specifications ............................................................................... 33

II.II. Analog-To-Digital Converter Architectures ..................................................... 35

II.II.I. Successive Approximation Register (SAR) ................................................. 35

II.II.II. Pipeline ADC ........................................................................................... 37

II.II.III. The Flash ADC ....................................................................................... 38

II.II.IV. ADC Architectures Resume .................................................................... 39

II.II.V. The ADC State-of-the-Art ........................................................................ 40

II.III. The Structure Of The ADC ............................................................................ 42

II.IV. References .................................................................................................... 43

32 Analog-To-Digital Converter Architectures


33

II.I. THE CIRCUIT SPECIFICATIONS

As presented in the previous chapter, one of the main applications of this ADC is

the ALMA interferometer. The present system processes 8 basebands each 2 GHz

wide (4GHz clock) for each of the 10 receiver bands ranging from 30 to 950 GHz.

The ALMA intermediate frequency range following each heterodyne receiver lies in

the range 4 to 12 GHz. As it is very difficult and impossible nowadays to digitize the

4-12 GHz bandwidth it is envisaged for the ALMA second generation

instrumentation to digitize a 4 GHz bandwidth after the total bandwidth has been

split (with a minor loss around 8 GHz) into 4-8 GHz and 8-12 GHz. Hence, the 2

first specifications are obtained:

Sampling frequency 8GHz.

Analog input bandwidth 8GHz (4-8 GHz being mandatory for this

application and 0-4 GHz bandwidth is presented as an optional feature);

Considering radioastronomy applications, due to the nature of the incoming signal

(Gaussian white noise), the 3-bit resolution is enough for the system because the

signal to noise ratio increases as the square root of the integration time. However,

given the ultra high-speed operation frequencies, the challenge of increasing the

resolution to 6-bit seems to enlarge the application possibilities. Thus, a new

specification is obtained:

ADC resolution 6-bit.

The next specifications concern the test phase. Due to the 8GHz sampling

frequency, it is not measurable by all kinds of equipments. So, output frequency

must be decreased. The chosen value is 2GHz. With 2GHz, the state of the art of the

measurement tools and devices allows the implementation of more possibilities of

test circuits and also it can be easily obtained from the 8GHz. Consequently, the

definition of the output standard can be done. In order to get the data out of the

circuit at this frequency, the best way is to use a differential architecture and with a

low voltage swing to increase speed. The standard is then the Low Voltage

Differential Signaling (LVDS). Thus, two new specifications are defined.

Output frequency 2GHz;


Output standard LVDS.

The quality of the clock is crucial and must also be defined in order to do not

deteriorate the ADC performance. Thus, considering the equation 1.14, where

the𝑆𝑁𝑅𝑗𝑖𝑡𝑡𝑒𝑟 is19.82dB the ∆𝑡𝑗𝑖𝑡𝑡𝑒𝑟 is then 1.35ps rms for 𝐹𝑖𝑛𝑚𝑎𝑥 =12GHz. This value

would make the ENOB 2.5bit together with an ideal 3bit ADC SNR.

Input clock jitter lesser than 1.35ps rms.

In addition to the previously defined specifications, the technology that is going to

be used must also be defined.

The ADC required for the ALMA interferometer is very specific and will not be used

in cell phones. However, the challenge is to enlarge the possibilities of applications

and to do so, the CMOS is preferable than BiCMOS, firstly because of their smaller

power consumption compared to the bipolar devices and secondly, but not less

important, because of their smaller area which saves silicon and allows a better

integration into the mobile devices. The silicon provider is STMicroelectronics due to

an existing partnership between STMicroelectronics and the IMS Laboratory. The

provided technology for the ADC is the 65nm CMOS with 7 metal layers. Core

devices, with low power option, will be used in the design, which increases the

challenge because of the low 1.2V voltage supply, but enlarges the suitable

applications for its lower power. This technology will be used with ground-based

projects in mind but would be well suited for future space projects as well.

Table 2.1 summarizes the specifications.

TABLE 2.1 – ADC SPECIFICATIONS SUMMARY

Parameter Specification Unit

Sampling Frequency 8 GHz Input Bandwidth @ -3dB 8 GHz Resolution 6 bit Output Frequency 2 GHz Output Standard LVDS - Input Clock Jitter <1.35 ps rms Technology 65nm CMOS -

So far, the specifications give an idea about the input and the output of the ADC.

However the functional blocks that will construct the A/D converter depend on the

choice of the architecture. In the next part of this Chapter, the main ADC

architectures will be presented so that this choice can be done.


35

The 6-bit implementation is a design goal while our first run will be for 3-bit (see

details in Section IV.II) which are sufficient for radioastronomy.

II.II. ANALOG-TO-DIGITAL CONVERTER ARCHITECTURES

Many architectures convert signal from analog to digital. Each of them has its own

characteristics, strengths and limitations making them suitable for one application

or another. During the following paragraphs the most common ADC architectures

used in A/D conversion will be presented.

II.II.I. SUCCESSIVE APPROXIMATION REGISTER (SAR)

This conversion process is based on approximation logic. Figure 2.1 shows a typical

block diagram of this kind of ADC.

Comparator

TAHR

eg

iste

r a

nd

Co

ntr

ol L

og

ic

DAC

Analog Reference

Analog Input

Digital Output

Figure 2.1– Typical SAR ADC block diagram.

As shown in figure 2.1, the SAR ADC has a track-and-hold (TAH) and it uses just

one comparator and the references are adjusted in order to go from a coarse

conversion to a fine one. This simplified block-diagram of the SAR ADC makes it

suitable for numerous applications which require a compact area. In addition, the

use of one comparator makes its offset ignorable because it generates an offset on

the transfer function but does not introduce any non-linearity.

The SAR ADC conversion starts with the comparison of the input voltage to ½ of the

full-scale. The result of this comparison gives the most significant bit (MSB).

Subsequently, according to the first comparison result, the sequencer adjusts the

references to ¼ or ¾ of the full-scale and the MSB-1 is obtained. This process is

repeated until the less significant bit is acquired. Thus, the successive


approximation of an-bit SAR requires n clock cycles which is not appropriate for

ultra-high speed applications. Figure 2.2 shows a sequence of conversion for a 3-bit

SAR ADC.

Clock cycle

Analog Reference (V)

0Vdd/8

Vdd/4

3Vdd/8

Vdd/25Vdd/8

3Vdd/4

Vdd

0 1 2 3 4

1 0 0 1Comparator

decisions

7Vdd/8

Input Signal

Figure 2.2– 3-bit SAR ADC conversion time-diagram.

Some techniques have been developed in order to increase the SAR speed by

reducing its latency but keeping the simplified block diagram.

The first of them is the replacement of the simple comparator by a multi-bit

quantizer. The referred multi-bit quantizer must be a flash converter as the

conversion requires just one clock cycle. In this case, for each clock cycle, instead of

one bit, two, three or even more bits are decided reducing the clock cycles required

for the conversion by the same factor. However, using multiple comparators makes

offset relevant. Nevertheless, in order to keep the SAR simplicity and to prevent

additional nonlinearities due to the comparators offsets, a 2-bit solution is generally

used [2.1].

This solution is not appropriate to overcome the ADC sampling frequency

specification because it would require a clock 2 or 3 times above the 8GHz and all

the time constraints would be tightened.

The second possible solution is an asynchronous architecture. The principle of the

asynchronous functionality is that the clock signal is used to indicate the start of

the conversion and cadence the process but all the internal timings and decisions

occur asynchronously, dictated by the circuit response speed. The first comparison


37

is then triggered by the clock and the MSB is obtained. However, another variable

takes place in the conversion. A flag indicating that the comparator has already

taken a decision. Thus, instead of waiting for the next clock edge for triggering the

MSB-1 comparison, the following stages are triggered by this flag. The internal

working frequency is thus established by the comparator speed.

This method accelerates the circuit by eliminating the waiting time. However, the

two inputs of the comparator are equal, it would be impossible for it to decide one

way or another. Theoretically, this drawback can be overcome with a comparison

time limiter. In other words, if the proposed comparison delay has passed and the

decision is not taken, a given decision is forced. It will not be critical for the system

because if the decision is not taken, it means both inputs are close and so decide

for an „1‟ or a „0‟ will have just a LSB impact.

II.II.II. PIPELINE ADC

A different commonly used high-speed ADC architecture is the pipeline. The

pipelined conversion is a series of A/D conversions. The main block diagram of the

pipeline ADC can be seen in figure 2.3. The conversion is made in steps, from the

MSB to the LSB. A pipeline ADC has a latency time between the first clock and the

first available data. However, because it is a serial process, once the first bits are

obtained, on each clock cycle a new digital code is available.

TAH

Analog Input

DACn-bit ADC xn -+

Analog Output

Digital Output

(a)

Analog Input Pipeline

unitary cell

Pipeline

unitary cell

Pipeline

unitary cell

Pipeline

unitary cell

MSB LSBMSB-1 LSB+1

(b)

Figure 2.3– (a) Pipeline unitary cell; (b) Pipeline ADC block diagram.


As shown in figure 2.3, the analog signal first passes through a track-and-hold and

then an A/D converter. The first stage output is already the MSB of the entire

process. These bits are converted into an analog output again and the error

between this signal and the held input is amplified and the process starts again

until the LSB is obtained.

In order to get the best performance from the pipeline architecture, the offset, the

gain and the timing errors (caused by the technological process or temperature

drift) between the sequential stages must be eliminated. Thus, the complexity

increases because of the required calibrations.

II.II.III. THE FLASH ADC

The flash ADC is known as being the fastest of the ADCs. The converted code is

obtained after one clock cycle. The block diagram of the flash ADC is represented in

figure 2.4. This architecture is also known as fully parallel A/D converter.

Re

fere

nce

La

dd

er

n C

om

pa

rato

rs

Flip

-Flo

ps

Th

erm

om

ete

r-to

-bin

ary

en

co

de

r Digital Output

Analog Input

Figure 2.4– Flash ADC block diagram.

The characteristic of the flash ADC is that the input signal is firstly converted into a

code called thermometer which gradually represents the amplitude of the input

signal. This happens through the parallel configuration of the comparators which

sequentially commute following the amplitude of the input signal.

Flash ADC sampling frequency can reach tens of gigahertz with recent technologies.

However, the resolution of this kind of converter is limited by the exponential

growth of the comparators number with resolution ( # 𝑜𝑓 𝑐𝑜𝑚𝑝𝑎𝑟𝑎𝑡𝑜𝑟𝑠 = 2𝑛 − 1 ).

Increasing this number means that the area and the power consumption also

increase. Another consideration is that with the shrinking technologies, the voltage


39

supply is lower, then reducing the difference between two voltage references and

putting it around the intrinsic offset of the comparators. This aspect makes the

flash architecture suitable for high speed applications where the required resolution

is around or below 8 bits.

The main drawback of this architecture is the parallel topology of the comparators.

The use of a large number of cells introduces nonlinearity error due to the offset

mismatching. Thus, the offset voltage must be much smaller than the LSB,

averaged or compensated by a calibration system.

II.II.IV. ADC ARCHITECTURES RESUME

The three main ADC architectures have been previously described. Table 2.2

summarizes its performances in terms of number of comparators and conversion

time.

TABLE 2.2 – ADC ARCHITECTURES CHARACTERISTICS

Architecture Number of

comparators Clock cycles

Suitable Resolution

[bits]

SAR 1 n >12 Pipeline 𝑷× 𝟐

𝒏𝑷 𝑷 8<>12

Flash 𝟐𝒏 − 𝟏 1 <8

In addition to these architectures, dual-slope, sigma-delta and ramp-compare ADCs

are also examples of analog-to-digital architectures. They are not described here.

For all A/D converter architectures, there is a useful technique used to increase the

sampling frequency: the time-interleaving (figure 2.5). By driving the input signal to

a different ADC in each clock cycle, it takes advantage of various channels to

convert data with an equivalent higher sampling frequency.


t

Equivalent Clock

t

ADC2 Clock

t

ADC1 Clock

Figure 2.5– Time-interleaving chronogram.

For an accurate use of this methodology, the ADCs behavior in terms of gain and

offset, and phases and delays between them must be completely controlled, either

by the elimination of the undesired effects or by its characterization for later data

processing in the digital domain.

II.II.V. THE ADC STATE-OF-THE-ART

In the following paragraphs, the state-of-the-art of high speed A/D converters is

detailed. The information will be presented in charts comparing the previously

presented architectures in terms of resolution, sampling frequency and power

consumption, in order to allow the choice of the most suitable architecture for this

project.

Figure 2.6 shows a comparison between the resolution and the architecture versus

the sampling frequency. For frequencies going from 1GHz to 12GHz, the most

common architecture are the interleaved (SAR or pipeline) and flash. The flash, due

to its parallelism is the only one to be designed in these frequencies without the

interleaving process; but they could, of course, be interleaved as well.


41

Figure 2.6– Architecture comparison in terms of the resolution and sampling frequency.

Another aspect that is important to analyze is the input bandwidth. Figure 2.7

shows the variation of the input bandwidth for different architectures for

frequencies between 1GHz and 12GHz. Thus the state-of-the-art shows that the

largest bandwidths tend to be obtained for flash ADC designs.

Figure 2.7– Architecture comparison in terms of the input bandwidth and sampling frequency.

0

2

4

6

8

10

12

0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00

Reso

luti

on

Sampling Frequency (GHz)

Flash Time-Interleaved ALMA 1st Gen THIS WORK

0.00

1.00

2.00

3.00

4.00

5.00

6.00

7.00

8.00

9.00

0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00

Inp

ut

Bn

ad

wid

th (

GH

z)

Sampling Frequency (GHz)

Flash Time-Interleaved ALMA 1st Gen THIS WORK

[2.2]

[2.5]

[2.4]

[2.3]

[2.7]

[2.6] [2.9]

[2.8]

[2.11]

[2.10] [2.14]

[2.12] [2.15]

[2.13]

[2.17]

[2.16] [2.19]

[2.18]

[2.21]

[2.20]

[2.23]

[2.22]

[2.25]

[2.24]

[2.26]

[2.27]

[2.17]

[2.2]

[2.19]

[2.21]

[2.14]

[2.15]

[2.18] [2.22]

[2.27]

[2.4]

[2.24] [2.23]

[2.26]

[2.13]

[2.20] [2.11-12]

[2.16]

[2.10]

[2.9] [2.5]

[2.6]

[2.8]

[2.7]

ALMA

42 The Structure Of The ADC

II.III. THE STRUCTURE OF THE ADC

With the information presented earlier in this Chapter, we can conclude that, with

respect to their limited sampling frequency and input bandwidth, the SAR and the

pipeline architectures cannot be used alone. However, they appear to be a

reasonable choice if an interleaved topology is brought into play. Flash architecture

also stands as a good choice in this area of interest.

The main advantage presented by the flash architecture is that, the input

bandwidth increases with the sampling frequency.

Considering the input bandwidth issue, which is a very important point for the

ALMA application, and also all the complexity, in terms of clock distribution, gain

and offset calibration, etc., that an interleaved system requires, the flash

architecture is then selected. It is important to clarify that it is not less challenging

to design a flash ADC at these frequencies, but this architecture presents specific

problems that will require an enormous attention during the design (buffering the

comparators, offset, etc.).


43

II.IV. REFERENCES

[2.1] Zhiheng Cao et al., “A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13µm

CMOS,” in Solid State Circuits Conference, 2008.ISSCC 2008, p. 542-634.

[2.2] Sheng-Chuan Liang et al., “10 GSamples/s, 4-bit, 1.2V, Design-for-Testability

ADC and DAC in 0.13µm CMOS technology,” in IEEE Asian Solid-State Circuits

Conference, 2007, ASSCC 2007, p. 4016-419.

[2.3] Michael Choi et al., “A 6-bit 5-GSample/s Nyquist A/D converter in 65 nm

CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, p. 16–17.

[2.4] S. Sheikhaei et al., "A 4-bit 5 GS/s flash A/D converter in 0.18µm

CMOS", Proc. IEEE Int. Symp. Circuits Syst., 2005, vol. 6, p. 6138-6141.

[2.5] Ying-Zu Lin et al., “A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS,” inCustom

Integrated Circuits Conference, CICC 2007,Sept. 2007, p. 213-216.

[2.6] Christian Paulus et al., “A 4GS/s 6b Flash ADC in 0.13µm CMOS,” in Symp.

VLSI Circuits Dig. Tech. Papers, Jun. 2004, p. 420-423.

[2.7] M. Khalilzadeh Agdam et al., “A Low-Power High-Speed 4-Bit ADC for DS-UWB

Communications,” in IEEE Computer Society Annual Symposium on VLSI, March

2007, ISVLSI 2007, p. 506-507.

[2.8] Cyril Recoquillon et al., “The ALMA 3-bit 4 Gsample/s, 2-4 GHz Input

Bandwidth, Flash Analog-to-Digital Converter” in ALMA Memo No. 532, 2005.

[2.9] Kazuaki Deguchi et al., “A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90nm

CMOS,” in IEEE Symposium on VLSI Circuits, June 2007, p. 64-65.

[2.10] Sunghyun Park et al., “A 3.5 GS/s 5-b Flash ADC in 90nm CMOS,” in IEEE

Custom Integrated Circuits Conference, Sept. 2006, CICC 2006, p. 489-492.

[2.11] Soon-Ik Cho et al., “A 6-bit 2.5GSample/s Flash ADC using Immanent

C2MOS Comparator in 0.18µm CMOS,” in IEEE International Symposium on Circuits

and Systems, May 2007, ISCAS 2007, p. 3379-3382.

[2.12] Mingzhen Wang et al., “Low-Power 1.25-Ghz Signal Bandwidth 4-Bit CMOS

Analog-to-Digital Converter for high Spurious-Free Dynamic Range Wideband

Communications,” in IEEE International SOC Conference, Sept. 2007, p. 109-112.

[2.13] Peter Scholtens et al., “A 6b 1.6GSample/s Flash ADC in 0.18µm CMOS

using Averaging Termination,” in IEEE International Solid State Circuits Conference

Digest of Technical Papers, 2002, ISSCC 2002, vol. 2, p. 128-435.

[2.14] Wei-Hsiang Ma et al., “A 5.5GS/s 28mW 5-bit Flash ADC with Resonant

Clock Distribution” in Proceedings ofEuropean Solid-State Circuits Conference, Sept.

2011, ESSCIRC 2011, p. 155-158.

44 References

[2.15] Hayun Chung et al., “A 7.5GS/s 3.8-ENOB 52mW flash ADC with clock duty

cycle control in 65nm CMOS,” in IEEE Symposium on VLSI Circuits, June 2009, p.

268-269.

[2.16] William Ellersick et al., “A 12-GS/s CMOS 4-bit A/D Converter for an

Equalized Multi-Level Link” in IEEE Symposium on VLSI Circuits, June 1999, p. 49-

52.

[2.17] Young-Chan JANG et al., “An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash

Analog-to-Digital Converter with Multi-Phase Clock Generator” in IEICE

Transactions on Electronics, 2007, vol. 90, no. 6, p. 1156-1164.

[2.18] Young-Chan JANG et al., “An 8-GS/s 4-Bit 340mW CMOS Time Interleaved

Flash Analog-to-Digital Converter,” in IEICE Transactions on Fundamentals of

Electronics, Communications and Computer Sciences, 2004, vol. E87-A, no. 2, p.350-

356.

[2.19] Khaled Ali Shehata et al., “1.5GSPS 4-bit flash ADC using 0.18µm CMOS” in

International Conference On Microelectronics, Dec. 2007, ICM 2007, p. 311-314.

[2.20] Ali Nazemi et al., “A 10.3GS/s 6bit (5.1 ENOB at Nyquist) Time-

Interleaved/Pipelined ADC Using Open-Loop Amplifiers and Digital Calibration in

90nm CMOS,” in IEEE Symposium on VLSI Circuits, June 2008, p. 18-19.

[2.21] Aida Varzaghani et al., “A 6GS/s, 4-bit Receiver Analog-to-Digital Converter

with Embedded DFE,” inSymp. VLSI Circuits Dig. Tech. Papers, Jun. 2005, p. 322–

325.

[2.22] Sandeep K. Gupta et al., “A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW

Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture,” in

IEEE International Journal of Solid-State Circuits, Dec. 2006, p. 2650-2657.

[2.23] Shuo-Wei Mike Chen et al., “A 6b 600MS/s 5.3mW Asynchronous ADC in

0.13μm CMOS,” in IEEE International Solid State Circuits Conference Digest of

Technical Papers, ISSCC 2006, p. 2350-2359.

[2.24] Simon M. Louwsma et al., “A 1.35 GS/s, 10 b, 175mW Time-Interleaved AD

Converter in 0.13µm CMOS,” in IEEE International Journal of Solid-State Circuits,

April 2008, p. 778-786.

[2.25] Bob Verbrugen et al., “A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC

in 40 nm Digital CMOS” in IEEE International Journal of Solid-State Circuits, Oct.

2010, p. 2080-2090.

[2.26] Yun-Jeong Kim et al., “An 8-bit 1Gsps CMOS Pipeline ADC,” in IEEE

Proceedings of Asia-Pacific Conference on Advanced System Integrated Circuits, Aug.

2004, p. 424-425.

[2.27] Aida Varzaghani et al., “A 4.8 GS/s 5-bit ADC-Based Receiver With

Embedded DFE for Signal Equalization” in IEEE International Journal of Solid-State

Circuits, March 2009, p. 901-915.

45

CHAPTER I I I - TRACK-AND-HOLD

DESIGN

Chapter III describes the motivations for

the use of an integrated track-and-hold

into the flash ADC architecture. The

design steps and methods will also be

presented in this chapter as well as the

measurements for the fabricated

prototype.

46 Contents

CHAPTER III – TRACK-AND-HOLD DESIGN 47

CONTENTS

III.I. The Track-and-Hold (TAH) and the Flash ADC ............................................... 49

III.I.I. The Track-and-Hold Specifications ........................................................... 50

III.I.II. The Track-and-Hold Core ........................................................................ 50

III.I.III. The Input Amplifier ................................................................................ 52

III.I.IV. The Clock Amplifier ................................................................................ 53

III.I.V. The Output Buffer ................................................................................... 53

III.II. The TAH Implementation .............................................................................. 55

III.III. The First Prototype Measurements .............................................................. 56

III.III.I. The DC Measurements ........................................................................... 57

III.III.II. The S-Parameters Characterization ....................................................... 58

III.III.III. The Transient Measurements ............................................................... 59

III.III.IV. The Dynamic Performance ................................................................... 60

III.III.IV.I. The Total Harmonic Distortion ........................................................ 60

III.III.IV.II. The TAH Spurious-Free Dynamic Range ........................................ 61

III.III.IV.III. The Effective Number of Bits ......................................................... 61

III.III.V. The Global Performance ........................................................................ 62

III.IV. Next Version of the TAH .............................................................................. 64

III.V. References .................................................................................................... 68

48 The Track-and-Hold (TAH) and the Flash ADC


III.I. THE TRACK-AND-HOLD (TAH) AND THE FLASH ADC

The typical block diagram of a flash ADC presented in the last chapter does not

integrate the TAH function. This is possible because the time-discretization

(figure1.1) is instantaneously made by the latch just after the comparator (see

figure 2.4). Thus, the TAH is not mandatory as in SAR or pipeline ADCs.

However, considering the high input and sampling frequencies of this design, the

TAH function can help decreasing the aperture delay error of the latching phase

and also minimizing any unbalanced delay in clock signal propagation, once the

input signal remains constant during the sampling time. A TAH is also desirable

when the design will evolve from 3-bit to the more complex 4 to 6-bit design.

The specifications for the design of the TAH must take into account some ADC

specifications such as the sampling frequency, the input bandwidth and also the

dynamic performance indicators, such as the SINAD and the ENOB that must fit a

3-bit ADC application.

In order to respond to speed and noise constraints the TAH will use a fully

differential architecture, as used in [3.1]. The architecture of the fabricated TAH

prototype is presented in figure 3.1. Each of the functional blocks will be detailed in

the next sections. The technology used for the design is the 65nm CMOS from

STMicroelectronics.

Input

Buffer

Output

Buffer

Clock

Buffer

Track

& Hold

Input

Signal

Clock

Signal

Sampled

Signal

Figure 3.1– TAH fully differential architecture.


III.I.I. THE TRACK-AND-HOLD SPECIFICATIONS

In order to integrate this TAH into the specified ADC, the design must take into

account the expected performance of the ADC. The main specifications are listed

below:

The maximum sampling frequency and the input analog bandwidth must be

equal to those of the ADC, so, 8GHz;

The TAH differential gain is 0dB;

Differential signal and clock inputs and also signal output impedances must

be matched to 50Ω;

The time during which the signal is held, must exceed 2/3𝑟𝑑 of the maximum

clock half-period. Thus, the hold-time must exceed 41.6ps;

The dynamic performance, given by the THD, SFDR and SINAD, at the

output of the TAH must better than required for 3-bit functionality;

III.I.II. THE TRACK-AND-HOLD CORE

The schematic of the TAH core is presented in figure 3.2. The TAH consists ofone

differential pair amplifier (Q1 and Q2), one source-follower stage (QSF), one switching

differential pair (QT and QH), one hold capacitor (CH) and onefeedthrough capacitor

(Cfth).

Q2Q1

ClkClk

VBIAS VBIAS VBIAS

VBIAS2 VBIAS2

In In

CH

QSF

Out Out

Cfth

QHQT

RL RL

Cfth

CH

QSF

QH QT

ClkClk

IT

Figure 3.2– TAH core schematic.


Firstly, the signal passes through the differential pair amplifier where it is amplified

using the load RL. Then, the functionality of the TAH core can be explained in two

parts:

During the tracking-phase (figure 3.3(a)) the Clk is „up‟ turning QT „on‟ and

QH „off‟. Thus, the current IT passes through the transistor QSF and so the

output signal follows the input;

Afterward, for the other half-period of the clock, the TAH is in the hold-phase

(figure 3.3(b)). This time, Clk is „up‟ and QSF is „off‟. Consequently, the output

signal is that previously held on the capacitor CH. However, once the CSF is

turned „off‟, it is important to recover the charges cumulated on the

transistor so that they will not modify the value of the output signal. The

recovery of these charges is done by the capacitor Cfth(see reference [3.2]).

The cancellation of this effect provides a less disturbed output signal. For

this design CH capacitance is about 205fF.

The evolution of the output signal during the two distinct phases of the TAH is

represented in figure 3.4.

Q1

ClkClk

VBIAS VBIAS

VBIAS2

In

CH

QSF

Out

Cfth

QHQT

RL

IT

Q1

ClkClk

VBIAS VBIAS

VBIAS2

In

CH

QSF

Out

Cfth

QHQT

RL

IT

(a) (b)

Figure 3.3– TAH core during: (a) tracking-phase; (b) hold-phase.


t

Clk

VDD

0

t

Output

Tracking-

PhaseHold-

Phase

Input

Signal

Output

Signal

Figure 3.4– The evolution of the TAH output signal.

III.I.III. THE INPUT AMPLIFIER

Before the TAH core, the input signal is amplified. The input amplifier provides

enough gain to transform the single-ended signal to differential. In addition, the

provided gain compensates for the losses in the TAH core. This block is composed

by two differential pair amplifiers with separated biasing (figure 3.5). The CCOUP

capacitors value is 5pF.

Q2Q1

VBIAS

VBIAS2 VBIAS2

In InOut

RL RL

Ccoup

RL

VBIAS

Ccoup

Q4Q3

RL

VBIAS3

Out

Figure 3.5– Schematic of the input amplifier.

Internally, the matching is done with a 50Ω resistor to the ground for a large

bandwidth operation.


III.I.IV. THE CLOCK AMPLIFIER

The clock amplifier must provide enough gain in order to the make the clock signal

swing rail-to-rail. Since the clock frequencies and input frequencies are specified at

8GHz, the same structure as the input amplifier has been used for the clock

amplifier (impedance matching and differential pair amplifiers). In addition to the

two differential pairs, CMOS inverters have been used to help saturating the clock

signal and creating a vertical slope (see figure 3.6). The dimensions of the second

stage of the CMOS inverters are twice the first so the load of the TAH core switches

can be driven as expected.

Q2Q1

VBIAS

VBIAS2 VBIAS2

In In

Out

RL RL

Ccoup

RL

VBIAS

Ccoup

Q4Q3

RL

VBIAS3

Out

Figure 3.6– Schematic of the clock amplifier.

In addition to the amplifier function, a circuitry has been integrated to the clock

amplifier just before the output in order to stop the clock of the TAH and let it at

the tracking mode. This allows us to characterize the TAH linearity.

III.I.V. THE OUTPUT BUFFER

The output buffer is composed of a differential pair amplifier and a source-follower

amplifier. It has also two serial 50Ω resistors in order to match the output

impedance. The differential pair compensates for the losses on the load while the

source-follower, with a gain of about 0dB, drives the load. Figure 3.7 shows the

schematic of the output buffer.


Q2Q1

VBIAS

In In

Out

RL RL

VBIAS2

Q3

Out

Q4

VBIAS2

50Ω

50Ω

Figure 3.7– Schematic of the output buffer.


III.II. THE TAH IMPLEMENTATION

As previously presented, the TAH has been fabricated primarily to be used as a

stand-alone device thus allowing an independent characterization of the design.

Figure 3.8 shows a picture of the fabricated TAH. The used technology is the 65nm

CMOS from STMicroelectronics. The die area is 1.1mm².

Figure 3.8– Die picture of the fabricated TAH.

In order to ease the characterization by increasing the number of variables, the four

functional blocks have three voltage supplies: one for the input and clock amplifiers

(VA), another one for the TAH core (VB) and the last one for the output buffer (VC).

The 28 pads have been divided as follows:

14 pads for ground;

6 pads for the differential input, clock and output;

7 pads for the voltage supplies (2 for VA, 3 for VB and 2 for VC);

1 pad for the clock enabler.

The fact that the voltage supplies are connected to the circuit with more than one

pad reduces the parasitic inductive load of the bonding wires.

The other precautions taken during the layout concern the differential pairs, which

have been drawn using the common-centroid technique to reduce the mismatch,

and also the triple n-well drawn around the four functional blocks in order to

provide a better insulation between them.

56 The First Prototype Measurements

III.III. THE FIRST PROTOTYPE MEASUREMENTS

The fabricated device has been assembled on a PCB (Printed Circuit Board) allowing

two test possibilities: with probes or with bonding wires on the input and the

output. The PCB used for the tests is presented in figure 3.9.

Figure 3.9– Picture of the PCB used for tests.

Figure 3.10 shows a block diagram of the test bench used for the characterization

of the TAH. The signal generators are from Agilent and Rhode Schwarz and the

oscilloscope from oscilloscope Lecroy with bandwidth of 16GHz and sampling

frequency of 40GHz over 4 channels or 80GHz over 2 channels. The scope uses an

8-bit implemented design but with an effective number of bits around 6-bit.

The next sections will present all the measurements that have been done and the

results obtained during the measurements are briefly discussed. Finally, the

measurements are compared to the post-layout simulation and the designed TAH is

compared to the state-of-the-art.

Input

Output

Clock


TAH

Voltage Supplies

and Clock

Enable

Input Signal

Generator

Hybrid

coupler

Clock Signal

Generator

Oscilloscope

Hybrid

coupler

Figure 3.10– Block diagram of the test bench.

III.III.I. THE DC MEASUREMENTS

During the DC measurements, the first step was to test the continuity between the

voltage supplies and the ground in order to check the absence of critical errors such

as a short or an open circuit. No critical errors were found.

Secondly, the current consumption on each voltage supply has been measured.

Each of the functional blocks is responsible for about 25% of the total power

consumption. First measurements of the current consumption, at the nominal

voltage supply (1.2V) have shown that the relative consumption of each block was

as expected but that the actual consumption was not the expected one because of

the resistive losses on the power lines. Thus, the voltage supply has been increased

in order to recover the nominal current consumption. Table 3.1 summarizes the DC

measurements.

TABLE 3.1 – TAH DC MEASUREMENTS

Voltage Supply

Test Condition

Nominal Voltage Nominal Current

V (V) I (mA) I (%) P (mW) V (V) I (mA) I (%) P (mW)

VA 1.2 58 48.7 69.6 1.33 70 52.2 93.1

VB 1.2 33 27.7 39.6 1.31 32 23.8 41.9

VC 1.2 28 23.5 33.6 1.35 32 23.8 43.2


III.III.II. THE S-PARAMETERS CHARACTERIZATION

The S-parameters measurements have been done with probes directly connected to

the TAH pads (see figure 3.11). The S11 and the S22 parameters are presented in

figure 3.12 and show that the reflection coefficient is smaller than -10dB for a

bandwidth greater than 10GHz.

Figure 3.11– Picture of the PCB during the probe tests.

S11(dB)

0

-10

-20

-30

-40

10

Start 200MHz Stop 20GHz

(a)

S22(dB)

0

-10

-20

-30

-40

10

Start 200MHz Stop 20GHz

(b)

Figure 3.12– (a) S11 and (b) S22 characterization.

The S21 parameter, or the gain of the system, is around -2dB. Figure 3.13 shows the

gain and the bandwidth of the TAH, which is about the specified 8GHz.


Figure 3.13– The gain of the TAH.

III.III.III. THE TRANSIENT MEASUREMENTS

Another important characteristic of the TAH that must be evaluated is the hold-

time. The hold-time has been defined as the time duration betweenthe sampling

instant and the time where a variation of 5mV on the sampled voltage is observed.

The 5mV variation has been specified because it means 1% of the expected output

full-scale.

To determine the hold-time, it is necessary to specify the exact sampling time. As

this is uncertain because of the circuit aperture errors it was preferable to develop a

specific methodology. By putting the output signal over a square signal representing

the sampling instants and by sweeping this square signal over time, the sampling

instant is recognized when the smallest hold-time is maximized. The smallest hold-

time is obtained for a sampling frequency of 8GHz, which is the maximum input

frequency and consequently the minimum sampling period. In these conditions, the

measured hold-time is 40ps, which means the duration of the hold-time is not less

than 40ps during the measurements. Figure 3.14 shows the measurements of the

hold-time for three different cases:

First is 1GHz input signal sampled by a 2GHz clock;

Second an 1.9GHz input signal sampled by a 2GHz clock;

Third is a 3.9GHz input signal sampled by an 8GHz clock.

-12

-10

-8

-6

-4

-2

0

0 2 4 6 8 10

Gain

(dB

)

Frequency (GHz)


(a)

(b)

(c)

Figure 3.14– Hold-time measurements.

III.III.IV. THE DYNAMIC PERFORMANCE

The dynamic performance of an ADC is evaluated from the analysis of the spectrum

of the converted signal. Dynamic performance indicators of the A/D converters,

such as the THD, the SFDR, the SINAD and the ENOB, can also be used for the

characterization of a TAH. The next paragraphs show the results obtained during

the tests of the TAH.

III.III.IV.I. THE TOTAL HARMONIC DISTORTION

During the characterization, the THD has been evaluated for different input

frequencies. The sampling frequency has been maintained at 8GHz. Figure 3.15

shows the variation of the THD versus the input frequency.The THD increase

observed in Fig. 3.15 is surprising; it could be related in part to the instrumentation

used during our tests (digital scope limited to 6 effective bits).

Input Output

Input

Output


Figure 3.15–Total harmonic distortion (THD) of the TAH for 8GHz sampling frequency.

III.III.IV.II. THE TAH SPURIOUS-FREE DYNAMIC RANGE

The SFDR has been measured for 8GHz sampling frequency and two input

frequencies, 3.9GHz and 7.9GHz. The spectra are shown on Figure 3.16. The

measured SFDR are -36dBc and -44dBc, respectively.

(a) (b)

Figure 3.16– SFDR for two input frequencies: (a) 3.9GHz; (b) 7.9GHz.

III.III.IV.III. THE EFFECTIVE NUMBER OF BITS

The ENOB, as presented on Chapter I, is directly linked to the SINAD which is the

most complete spectral indicator in considering the distortion and the noise.

Figure 3.17 shows the variation of the ENOB versus the input frequency. Around

4GHz, the ENOB is about 6 effective bits decreasing to about 5 effective bits around

8GHz.

-39

-37

-35

-33

-31

-29

-27

-25

1.09375 3.90625 7.8125

TH

D (dB

)

Frequency (GHz)

-36dB

c

-44dB

c


Figure 3.17– ENOB versus the input frequency.

III.III.V. THE GLOBAL PERFORMANCE

The TAH has shown an acceptable behavior during the characterization. However,

the THD and the ENOB plots versus frequency exhibit a peculiar variation. In

particular, the increase with frequencies above 4GHz is unexpected. So far, we have

not found a good explanation to the behavior of the THD and ENOB with frequency.

The measurements have been repeated and show the same trend. However, this

plot seems to indicate that the oscilloscope may limit the measured performances.

All the results presented earlier point to the good adaptability of the TAH to a 3-bit

ADC up to 8GHz.

Finally, to compare the circuit performance to the state-of-the-art, a figure-of-merit

(FoM) is needed. The result is obtained with equation 3.1, which is the same used

for the FoM of ADCs, where 𝑃 is the power consumption and 𝑓𝑆 is the sampling

frequency.

𝐹𝑜𝑀 =𝑃

2𝐸𝑁𝑂𝐵𝑓𝑆 (3.1)

While operating in Nyquist sampling condition, the TAH has a FoM of about

1.59pJ/conv.step. If just the TAH core is considered (that is to say the

Input/Output and Clock buffers in Figure 3.1 are not considered), the FoM is

0.395pJ/conv.step.

The main characterization parameters of this design are summarized in table 3.2.

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

1.09375 3.90625 7.8125

EN

OB

(bit

)

Frequency (GHz)


TABLE 3.2 – TAH PERFORMANCE SUMMARY

Parameter Performance Unit

Sampling Frequency 8 GHz Input Bandwidth @ -3dB 8 GHz Gain 0 dB Hold-time 40 ps Power Consumption 178 mW Voltage Supply 1.32 V THD -37 dB

ENOB 5.8 bit

FoM [core only] 0.4

[0.09] pJ/conv.step

Chip area 1.1 mm²

The comparison between the performance obtained with this work and the state-of-

the-art is shown in table 3.3. We note that for the state-of-the-art publications cited

here (see references 3.1 to 3.4) we do not know whether the FoM values quoted in

these publications are for the TAH core only or not. However, our core only value of

0.09pJ/conv. step is better than all published values except one.

TABLE 3.3 – STATE-OF-THE-ART COMPARISON

Parameter This work Circuit

Unit [3.1] [3.2] [3.3] [3.4]

Sampling Frequency 8 30 10 4 10 GHz Input Bandwidth @ -3dB 8 7 4 2 3 GHz Gain 0 8 - - dB Hold-time 40 - 74 - ps Power Consumption [core only] 178 [41] 270 26 20 800 mW Voltage Supply 1.32 1.8 0.9 5.5/4.5 V THD -37 -30 -37.5 - -47.22 dB ENOB 5.8 5.85 5.9 > 4 7.58 bits FoM [core only] 0.4 [0.09] 0.156 0.0435 0.3125 0.418 pJ/conv.

Technology CMOS 65nm

CMOS 130nm

CMOS 65nm

CMOS 90nm

BiCMOS 0.25µm

-

Chip area 1.1 1mm² - 0.000450 0.97 mm²

64 Next Version of the TAH

III.IV. NEXT VERSION OF THE TAH

In order to improve the performance of the TAH, especially concerning the hold-

time, the TAH core has been redesigned. The design is based on the previous

architecture. However some modifications have been brought to the circuit

dimensioning.

Initially, the biasing of the differential pair amplifier of the TAH core has been

improved. Some Design Kit upgrades have been done during the design of the first

prototype and so, the optimum biasing has been compromised. Thus, a higher gain

has been achieved with the same current consumption.

Secondly, the source follower NMOS has been replaced by a HPA (High Performance

Analog) n-channel transistor. This device presents a smaller channel resistance

reducing the resistive losses on the source follower allowing a higher common mode

voltage on the output node.

Finally, the feedthrough capacitor 𝐶𝑡𝑕 has been studied in order to improve the

hold-time. Its functionality is to absorb the charges released during the switching of

the source-follower transistor. Thus, the dimensions of 𝐶𝑡𝑕 must be linked as much

as possible to the source-follower‟s. Here again the last minute changes on the

design kit have introduced some undesired effects. After the changes, the 𝐶𝑡𝑕

capacitor has a value is 33.5fF instead of the previous 60fF. Figure 3.18 compares

the TAH output of the new design and the original one for 8GHz sampling frequency

and for 2, 3.9 and 6.2GHz input frequencies.

(a)


(b)

(c)

Figure 3.18– TAH output: new design (solid line); previous version (dashed line).

Figure 3.19 shows the hold time of the new design for different sampling

frequencies (2, 4, 6 and 8GHz) and a 5.625GHz input signal. The new design is able

to hold the output signal over 200ps, which correspond to a sampling frequency of

2GHz.

(a)

(b)


(c)

(d)

Figure 3.19– TAH hold-time and respective voltage variation for: (a) 2GHz; (b) 4GHz; (c) 6GHz and (d)

8GHz sampling frequencies.

In a procedure similar to that applied to the TAH core, the biasing of all components

has been reviewed. The improvement of the gain obtained with the rebiasing of the

input buffer, combined with the achievements on the TAH core, allowed the removal

of one differential pair of the input buffer.

The spectral results are presented in figure 3.20. The SFDR is greater than about

30dBc in general, 30dBc being the worst casefor the input frequency at 1.875GHz.

Figure 3.20– TAH spectral performance for 8GHz sampling frequency and: 1.875GHz (red line);

3.9875GHz (blue line); 5.625GHz (pink line) and 7.125GHz (black line) input frequencies.


As a conclusion, the same gain performance has been achieved with a smaller

current consumption (only 85mW) and the hold-time has been increased thanks to

the re-dimensioning of the 𝐶𝑡𝑕 capacitor. Considering the fabrication of the new

TAH, only few modifications have to be done on the layout and with these

modifications, the parasitic effects, primarily those related to the value of 𝐶𝑡𝑕, must

of course be taken into account.


III.V. REFERENCES

[3.1] S. Shahramian, S.P. Voinigescu, A.C. Carusone, “A 30-GS/sec Track and Hold

Amplifier in 0.13-μm CMOS Technology,” in Proc. Custom Integrated Circuits

Conference, 2006. CICC '06, p. 493-496.

[3.2] G. Chen, Y. Luo, A. Drake, K. Zhou, “A 5-Bit 10GS/s 65nm Flash ADC with

Feedthrough Cancellation Track-and-Hold Circuit”, in International Midwest

Symposium on Circuits and Systems, 2009. MWSCAS ‟09, p. 423-426.

[3.3] T. Sato, S. Takagi, N. Fujii, Y. Hashimoto, K. Sakata, and H. Okada, “4-Gb/s

Track and Hold Circuit using Parasitic Capacitance Canceller,” in ESSCIRC,

Proceeding of the IEEE, Sept. 2004, pp. 347–350.

[3.4] S. Halder, H. Gustat, C. Scheytt, "An 8 Bit 10 GS/s 2Vpp Track and Hold

Amplifier in SiGe BiCMOS Technology", in ESSCIRC, Proceeding of the IEEE, 2006,

pp. 416–419.

69

CHAPTER IV - FLASH ADC

DESIGN

In this Chapter, details of the ADC design

will be shown. All functional blocks will be

described. The measurement results will

also be discussed. Finally, the last part of

the Chapter IV will be dedicated to the

perspectives of our ADC evolutions.

70 Contents

CHAPTER IV – FLASH ADC DESIGN 71

CONTENTS

IV.I. The Flash ADC Design ................................................................................... 73

IV.I.I. The Input Amplifier .................................................................................. 74

IV.I.II. The Comparators ..................................................................................... 75

IV.I.III. The Differential Flip-Flop (DFF) .............................................................. 77

IV.I.IV. The Encoder ........................................................................................... 77

IV.I.V. The Clock Amplification and Distribution ................................................ 79

IV.I.V.I. The Clock Divider ............................................................................... 79

IV.I.V.II. The Phase Controllers ....................................................................... 80

IV.I.V.III. The TAH Clock Enabler .................................................................... 81

IV.I.VI. The Demultiplexer .................................................................................. 81

IV.I.VII. The LVDS Buffer ................................................................................... 82

IV.II. The ADC Implementation .............................................................................. 83

IV.II.I. The TAH and the Input Amplifier ............................................................. 83

IV.II.II. The Comparator ..................................................................................... 84

IV.II.III. The DFF ................................................................................................ 85

IV.II.IV. The Clock Divider .................................................................................. 86

IV.II.V. The Phase Controller .............................................................................. 86

IV.II.VI. The LVDS Buffer ................................................................................... 87

IV.II.VII. The ADC .............................................................................................. 87

IV.III. The First 3-bit Prototype Measurements ...................................................... 90

IV.III.I. The DC Measurements ........................................................................... 90

IV.III.II. The Transient Measurements ................................................................ 91

IV.III.II.I. The LVDS Buffer and the Clock Divider ........................................... 91

IV.III.II.II. The Demultiplexer .......................................................................... 94

IV.III.II.III. The Encoder .................................................................................. 94

IV.III.III. The Dynamic Performance ................................................................... 95

IV.IV. Next Version of the ADC .............................................................................. 99

IV.IV.I. The TAH and the Input Amplifier ............................................................ 99

IV.IV.II. The Comparators .................................................................................. 99

IV.IV.III. The Encoder ....................................................................................... 100

IV.IV.IV. The Demultiplexer.............................................................................. 100

IV.V. References .................................................................................................. 102

72 The Flash ADC Design


IV.I. THE FLASH ADC DESIGN

So far, during the last Chapters the motivations of the design and the

characteristics of this ADC have been defined. Here, each functional block will be

explained. Figure 4.1 shows the final block diagram of the A/D converter. The input

signal is sampled by the TAH and then amplified by the input amplifier in order to

adapt the amplitude to the FS. Afterward, the signal is compared, synchronized and

coded in Gray code. Then, the signal is demultiplexed in order to reduce the output

frequency by 4. These slower bits enter output LVDS buffers and the demultiplexed

output is consequently available. All this process is cadenced by a clock which is

properly shaped by the clock amplifier. The clock phase controllers are also clock

buffers locally placed close to the respective functional block in order to reduce the

clock lines parasitic capacitance effects. Finally, a block has been introduced in

order to enable the TAH functionality or bypass it.

Input Amplifier

Ref

eren

ce L

add

er

Co

mp

arat

ors

En

cod

er

LVD

S B

uffe

r

Clock Amplifier

TAH_ clock control

1:4

Syn

chro

niza

tion

DF

Fs

TAH

1 to

4D

emul

tiple

xer

DFFs

Phase control

Phase control

Phase control

Phase control

Figure 4.1– Flash ADC block diagram.

As the TAH has already been presented in Chapter III, its design will not be

mentioned in the following paragraphs which are dedicated to the remaining

functional blocks.


IV.I.I. THE INPUT AMPLIFIER

An input amplifier has been included in order to adjust the TAH output level to the

ADC full-scale, which can be extended up to 540mV (almost half of the voltage

supply). An operational transconductance amplifier (OTA) has been integrated into

the feedback loop of the input amplifier in order to enable the regulation of the

input signal common-mode voltage. The amplifier is composed by three differential-

pair stages, the last having its output DC level controlled by the feedback loop

(figure 4.2).The three differential-pairs provide the gain and perform the conversion

from differential to single, since only one input is used by the comparators. Both

schematics are presented in figure 4.3.

OTA

Vref

- +

Vinp

Vinn

Input

Amplifier

Voutn

Figure 4.2– Input amplifier block diagram.

1.2V

Vbias

VinP

VinN

Vcm

VOTA

VoutN

Vcmout

VoutP

(a)


Vbias

1.2V

Vref VcmoutVOTA

(b)

Figure 4.3– (a) Input amplifier and (b) OTA schematics.

IV.I.II. THE COMPARATORS

The comparison functionality is the most important operation of an ADC. The more

accurate it is, the better is the global system performances.

The approach used for this comparator design was to use several differential pair

amplifiers, in an open loop configuration, and keep amplifying the difference

between the input signal and the DC reference until the output swing reaches the

rail-to-rail range. To do so, 9 amplification stages have been used. The explanation

is in the following.

The first stage has been biased out of the saturation region for all possible levels of

the DC reference (which unbalances the differential pair). The four following stages

are loaded by an active inductor in order to increase the bandwidth. The active

inductor is shown in figure 4.4(b). The last four stages are loaded by an active load.

The three different stages that compose the comparator are presented in figure 4.4.

The use of an active inductor allows the capacitance cancellation and consequently

the bandwidth enhancement [4.1].


Ibias

Vdd

Vinp

Lo

ad

Lo

ad

Vinn

Ibias

Vdd

Vinp

LoadLoad

Vinn

Active

In

du

cto

r

Ibias

Vdd

Vinp

Lo

ad

Lo

ad

Vinn

(a) (b) (c)

Figure 4.4– Stages of the comparator: (a) First stage with HPA transistors and resistive load; (b) Active

inductive load stage for capacitance cancellation and bandwidth enhancement; (c) Active load amplifier

stage.

Considering the 1.2V voltage supply and the 540mV full-scale, the voltage

difference between two references, the LSB, is about 8.5mV, for a 6-bit flash ADC,

which has 63 references. Thus, the gain provided by the amplification stages, which

is about 50dB (316V/V), is enough to amplify, and saturate, an input signal with a

LSB/2 amplitude (about 4.25mV) to 1.2V.

Moreover, considering the 8.5mV LSB, the intrinsic offset of the comparators must

be in an acceptable level in comparison with the LSB to avoid missing codes during

the A/D conversion. More details will be discussed on next section.

The DC references for the comparators are generated by 6 resistances in a resistive

divider (see figure 4.5). Three nodes are available from the outside of the chip, the

lower and the higher voltages and the middle point voltage in order to allow a better

regulation of the references.

Vhigh Vlow

Vmiddle

Vref2

Vref3

Vref6

Vref5Vref7 Vref1

Vref4

Figure 4.5– Resistive reference ladder.


IV.I.III. THE DIFFERENTIAL FLIP-FLOP (DFF)

The most used cell in this ADC is the DFF. It is used to sample the comparators

thermometer output code, to synchronize the encoder output, to divide the clock

and also to build the demultiplexer. Figure 4.6 shows the schematic of the

implemented DFF. The master-slave configuration is well-known and its

functionality and robustness respond to the needs of the ADC.

CLKN

CLKP

InP

InN

CLKP

CLKN

MASTER SLAVE

OutP

OutN

Figure 4.6– Differential flip-flop schematic.

IV.I.IV. THE ENCODER

Until now the presented blocks have the same structure for 3 or 6-bit ADC.

However, the encoder design depends on the number of bits. The first discussions

on this project have defined a preliminary step with a design of a 3-bit resolution

prototype. This procedure allows the validation of the functionality of all the parts of

the circuit. Even the most critical block, the comparator, can be tested under the 6-

bit condition if the DC references are approached to decrease the LSB.

The encoding stage is divided into two parts. The first one performs the encoding

from the thermometer code to the one-hot code. The second encodes the one-hot

code to Gray code.

The one-hot code indicates in what position, within the 2n possibilities, the input

signal is located.Table 4.1 shows the truth table for the thermometer to one-hot

conversion.


TABLE 4.1 – THERMOMETER TO ONE-HOT CONVERSION

Code Thermometer encoded One-Hot encoded

t0 t1 t2 t3 t4 t5 t6 h0 h1 h2 h3 h4 h5 h6 h7

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

2 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0

3 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0

4 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0

5 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0

6 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0

7 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1

The one-hot encode is performed by differential full-custom NANDs with 2 inputs.

Its schematic is shown in figure 4.7.

a

a

b

b

Vbias

Vdd

outout

RloadRload

Vdd

Gnd

D

D

Q

Q

DFF

D

D

Q

Q

DFF

D

D

Q

Q

DFF

a

b

a

b

a

b

h2

h1

h0

s(a) (b)

Figure 4.7– (a) Full-custom differential NAND; (b) NANDs connection for the one-hot encoding.

Then, the resulting one-hot encoded data are used for encoding each bit

individually in Gray code. This is made by an OR operation. The truth table of this

conversion is shown on table 4.2.

TABLE 4.2 – ONE-HOT TO GRAY CONVERSION

Code One-Hot encoded Gray encoded

h0 h1 h2 h3 h4 h5 h6 h7 g0 g1 g2

0 1 0 0 0 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0 1 0 0


Code One-Hot encoded Gray encoded

h0 h1 h2 h3 h4 h5 h6 h7 g0 g1 g2

2 0 0 1 0 0 0 0 0 1 1 0

3 0 0 0 1 0 0 0 0 0 1 0

4 0 0 0 0 1 0 0 0 0 1 1

5 0 0 0 0 0 1 0 0 1 1 1

6 0 0 0 0 0 0 1 0 1 0 1

7 0 0 0 0 0 0 0 1 0 0 1

Bits g0, g1 and g2 are then given by the equations 4.1, 4.2 and 4.3.

𝑔0 = 𝑕1 + 𝑕2 + 𝑕5 + 𝑕6 (4.1)

𝑔1 = 𝑕2 + 𝑕3 + 𝑕4 + 𝑕5 (4.2)

𝑔2 = 𝑕4 + 𝑕5 + 𝑕6 + 𝑕7 (4.3)

The OR logical operation is performed by 8 differential pairs connected to the same

resistive load. Thus, all 8 one-hot bits are connected to one differential pair and the

ones which generate the respective bits are connected on the opposite input of the

differential pair. Figure 4.8 shows the Gray encoder schematic.

IV.I.V. THE CLOCK AMPLIFICATION AND DISTRIBUTION

The clock amplifier is similar to that used in the TAH stand-alone (see Chapter III).

However, the complete clock distribution has some particularities in the design of

the ADC. These specific points are described below.

IV.I.V.I. THE CLOCK DIVIDER

As it will be further explained, the data output cadence is 2GHz. The DFFs are used

to generate the division by 4. The block diagram can be seen in figure 4.9. A buffer

stage is added to guarantee the signal integrity.

D

D

Q

Q

DFF1

D

D

Q

Q

DFF2

8 GHz

clock

Buffer 2 GHz

clock

Figure 4.8– Clock divider by 4.


Ibias

Ibias

Ibias

Ibias

Ibias

Ibias

Ibias

h1

Vdd

h2

h3

h4

h5

h6

h7

RloadRload

g0g0

h1

h2

h3

h4

h5

h6

h7

Ibias

h0 h0

Ibias

Ibias

Ibias

Ibias

Ibias

Ibias

Ibias

h1

Vdd

h2

h3

h4

h5

h6

h7

RloadRload

g1g1

h1

h2

h3

h4

h5

h6

h7

Ibias

h0 h0

Ibias

Ibias

Ibias

Ibias

Ibias

Ibias

Ibias

h1

Vdd

h2

h3

h4

h5

h6

h7

RloadRload

g2g2

h1

h2

h3

h4

h5

h6

h7

Ibias

h0 h0

(a) (b) (c)

Figure 4.9– (a) g0; (b) g1; (c) g2 logic generation.

IV.I.V.II. THE PHASE CONTROLLERS

The phase controllers are two serial CMOS inverters locally placed close the

respective functional blocks (TAH, DFF, Synchronization DFF and demultiplexer, as

seen in figure 4.1). This approach has been used in order to reduce the parasitic

capacitance on the clock distribution tree.

The phase control is obtained with the variation of the power supply. By doing this,

the strength of the inverter is changed in direct proportion with the power supply.

Consequently, a weaker (stronger) inverter takes more (less) time to reach the

threshold voltage of the following stage. In order to allow the phase control, the

power supply of each buffer is independent.

We stress that these phase controllers which may bring extra noise will not be

needed in our final design


IV.I.V.III. THE TAH CLOCK ENABLER

This circuit has been implemented in order to allow the ADC to work with and

without the TAH functionality. For this, an enabler circuit has been put in series

with the TAH differential clock. The clock must then be locked at the correct level to

put the TAH in the sampling mode. The circuit is shown in figure 4.10. When

enable is „1‟, the CLKp and CLKn are inverted, when it is „0‟, CLKp is tied down and

CLKn is tied up. This condition puts the TAH in the sampling position.

Vdd

CL

Kp

CLKn

Large

W

Small

Wenable

enable

Vdd

CL

Kn

CLKp

Large

W

Small

W

enable

enable

Figure 4.10– TAH clock enabler schematic.

IV.I.VI. THE DEMULTIPLEXER

The data output cadence is 2GHz in order to transfer the data at a lower rate to the

output buffer for further processing. Consequently, the 8GHz clock must be divided

by four in order to be used by the demultiplexer. This approach has been used

because, at the beginning of the project, the available measurement equipments did

not reach the GHz frequencies. The 2GHz output would then be the input of an

external demultiplexer, dividing the clock again by four allowing the measurements

with a 500MHz clock cadence.

Although it was possible to add, integrated to the ADC, a 1:16 demultiplexer, it

would internally generate an enormous quantity of spectral spurious degrading the

overall performances. In addition, the integration of a 1:16 demultiplexer would

require 48 pads with a single-ended output or 96 pads for a differential output

standard, for the 3-bit version. Figure 4.11 shows the block diagram of the 1:4

demultiplexer, which is composed by a shift register and a synchronization stage.


D

D

Q

Q

DFF

D

D

Q

Q

DFF

D

D

Q

Q

DFF

D

D

Q

Q

DFF

8GHz

D

D

Q

Q

DFF

D

D

Q

Q

DFF

D

D

Q

Q

DFF

D

D

Q

Q

DFF

2GHz

bout4 bout3 bout2 bout1

bin0

Shift Register

Figure 4.11– 1:4 demultiplexer.

IV.I.VII. THE LVDS BUFFER

A LVDS buffer has been designed for the output interface (Fig. 4.12). For this, a

1.8V voltage supply has been used and consequently the standard transistors have

been replaced by a thicker model. A feedback loop has been integrated in order to

ensure the 1.2V common-mode voltage. The feedback controls the current mirror,

whose value has been set to 3.5mA in order to respect the output voltage on the

load.

In this configuration, transistors Q1 to Q4 act as switches, driving the ILVDS current

through the load in one sense (by Q1 and Q2 when InP is up and InN down) or in

the other (by Q3 and Q4).The positive feedback makes the common-mode voltage

stable whatever the ILVDS current.

PAD

PAD

1.8V

InP

InP

InN

InN

1.2V

+ -

bonding

bonding

10

0Ω

OTA

Q1

Q2

Q3

Q4

ASIC

Outside

the ChipILVDS

Figure 4.12– Schematic of the LVDS buffer.


IV.II. THE ADC IMPLEMENTATION

In this part, the details about the implementation of the ADC will be explained;

simulation results will be given block-by-block and for the ADC top cell. It has been

decided within the time allocated to this thesis and for a first fabrication run to test

a rather simple 3-bit implementation. However, the question of the comparators

offset for a 6-bit design is briefly discussed below. The details of our 3-bit layout will

be presented in this chapter.

IV.II.I. THE TAH AND THE INPUT AMPLIFIER

The TAH uses the core of the circuit presented in Chapter III. The only difference is

that the output buffer is replaced by the ADC input amplifier.

Although the importance of the input amplifier alone, the results that will be further

presented take into account the TAH. This procedure avoids any later error due to a

worse integration between the two functional blocks. Both present a 15dB gain and

a 1dB compression point at -8dBm, for an input at 6.5GHz. Figure 4.13(a) shows

the gain of the input amplifier and figure 4.13(b) shows the compression point.

(a) (b)

Figure 4.13– Input amplifier: (a) gain and bandwidth; (b) compression point.

This block has the following performances presented in Table 4.3.

TABLE 4.3 – TAH + INPUT AMPLIFIER PERFORMANCE SUMMARY

Input Frequency THD (dB) SINAD (dB) SFDR (dBc) ENOB

Fin=2.8125GHz -26.41 26 30.65 4.02

Fin=7.03125GHz -27.41 27 29.27 4.19

84 The ADC Implementation

IV.II.II. THE COMPARATOR

The offset has been evaluated for this comparator configuration. However, its value

is greater than the 6-bit LSB (8.5mV). So, in order to use this comparator in the

future 6-bits ADC, the offset must be reduced or corrected.

The offset has been reduced using HPA (High Performance Analog) transistors,

instead of the LVT (Low VT) transistors. These transistors have a minimum length of

140nm. However, they are physically implemented with different processes allowing

them to operate in higher frequencies with a large length. The reduction of the offset

comes from the fact that the transistor can increase in size (without losing its

performance) and since the offset is inversely proportional to the square root of the

transistor gate surface (1 𝑊 ∗ 𝐿 ) [4.2], the offset is reduced. Figure 4.14 shows the

reduction of the offset standard deviation (σ) from 4.78mV to 2.70mV. This means a

reduction of 43.5% of the offset. This σ means that 70% of the comparators will

have an offset of ±2.7mV. Consequently, the 3σ, which corresponds to 99% of the

cases, indicates an offset of ±8.1mV. This value is still smaller than the 6-bit LSB.

The previous 3σ, with classical low Vt transistors, would correspond to ±14.34mV

(almost 2 LSBs).

(a) (b)

Figure 4.14– Comparator offset standard deviation for (a) LVTLP transistors; (b) HPALP transistors.


During the comparator layout implementation, all the differential pairs have been

carefully located into a matrix configuration in order to reduce the mismatch

between the two components. Figure 4.15 shows the layout of the first stage of the

comparator. Each transistor of the differential pair has been split in two parts and

placed inside a common-centroid 5x5 matrix in order for them to have the same

surroundings. In addition, the layout is insulated by a deep n-well to decrease the

noise propagation through the substrate. This approach has been applied to all the

functional blocks.

Figure 4.15– Comparator first stage layout.

IV.II.III. THE DFF

The functional simulations have presented no specific issue as it can be seen in

figure 4.16. The green line is the input, the red line the DFF output and the pink

and yellow ones are the differential clock.

Figure 4.16– DFF functionality simulation.


IV.II.IV. THE CLOCK DIVIDER

Figure 4.17 shows a transient simulation of the clock divider: the 8GHz clock in

green and the 2GHz clock in orange.

Figure 4.17– Clock divider by 4.

IV.II.V. THE PHASE CONTROLLER

By changing the voltage supply of the local buffer by ±50mV, the clock phase rising

edge can be delayed by ±2ps, as shown in figure 4.18.

Figure 4.18– Clock phase control.


IV.II.VI. THE LVDS BUFFER

Figure 4.19 shows the eye diagram of the LVDS buffer output. The common-mode is

correctly centered in 1.2V while the differential amplitude is around 300mV.

Figure 4.19– Eye diagram of the LVDS buffer output.

IV.II.VII. THE ADC

The functional blocks have been put together and the overall performance has been

evaluated at schematic and post-layout level. In order to perform this evaluation, an

ideal DAC has been implemented in veriloga language. With the analog signal from

the DAC output, the spectrum can be analyzed. Figure 4.20 shows an example of a

4.21GHz signal sampled by the 8Gsps (giga samples per second) ADC and then

rebuilt by the DAC and the respective spectrum (these results are from post-layout

simulations).

(a) (b)

Figure 4.20– (a) ADC output reconverted to analog and (b) the respective spectrum.

In figure 4.20, the 8 levels of the 3-bit ADC can be identified and its spectrum

shows a SFDR of 26dBc. The ENOB for this case is 2.5 effective bits. This can be

explained by the parasitic components of the layout and also by the light saturation


present on the DAC output. The power consumption of the first prototype is shown

in figure 4.21. It is presented in two parts: the first is the global power consumption

and the second is the power consumption of the useful circuit (the useful circuit

does not consider the blocks integrated to ensure the functionality of the first run,

like the phase controllers, the internal buffers added after each stage to reshape the

signals, the clock enabler for the TAH, etc.). The average values are 625mW and

430mW, respectively.

(a) (b)

Figure 4.21– (a) ADC power consumption (b) ADC useful circuit power consumption for 8GSPS.

In order to ease the characterization tasks, the voltage supplies of all the functional

blocks have been designed separately so that they can be optimized individually.

Therefore, the final dimensions of the fabricated ADC prototype (figure4.22) are

largely determined by the number of pads. The layout counts 80 pads:

10 for the differential signal and clock inputs (each input uses 5 pads:

ground-signal_P-ground-signal_N-ground);

24 pads for the LVDS demultiplexed outputs;

2 pads for the LVDS clock divided by 4 (in order to synchronize the output

bits);

4 pads for the clock phase control;

40 other pads for voltage supplies and DC references.

Despite of the large area, it is important to note that the active circuit is only

0.74mm².


Figure 4.22– Die picture of the fabricated 3-bit ADC

In order to reduce the resistive losses on the voltage supply distribution lines, all

metal layers have been used to connect the pads to the circuit core. In the proximity

of the functional blocks, the voltage supplies are distributed in a star topology to

avoid two neighbor cells to have different voltage supply.

As mentioned earlier, all functional blocks have been isolated by a triple N-well in

order to decrease the digital noise interference on the analog part. In addition, the

signals at 2GHz on the demultiplexer may generate spectral spurious into the

useful bandwidth. Therefore, the demultiplexer has been placed far away from the

rest of the circuit (about 250µm). Between the demultiplexer and the encoder,

which is the nearest block, the substrate is insulated.

The circuit has been assembled directly on the PCB. The PCB integrates the 100Ω

resistive loads for the LVDS buffers and voltage regulators for all the DC supplies

and references.


IV.III. THE FIRST 3-BIT PROTOTYPE MEASUREMENTS

The validation process has been made in three major levels. The first one is the DC

measurements that can provide information about critical issues that such as

short-circuits, open-circuits or an abnormal current consumption. The second

validation level corresponds to the transient analyses by which the functionalities of

several blocks can be explored. The last validation level is related to the dynamic

performance. At this level, issues like distortion, noise, clock jitter are analyzed

within the overall performance of the ADC.

Figure 4.23 shows the block diagram of the ADC test bench and also a picture of

the PCB, which was developed in the LAB, where the ADC has been assembled for

characterization.

3-bit ADC

Voltage Supplies

and Control

Signals

Input Signal

Generator

Hybrid

coupler

Clock Signal

Generator

Oscilloscope and

Logic Analyser

Hybrid

coupler

(a) (b)

Figure 4.23– (a) Block diagram of the test bench; (b) PCB used for measurements.

IV.III.I. THE DC MEASUREMENTS

No major issue has been found in the circuit during the DC evaluations.

Regarding the current consumption, it has been measured and it is presented in

figure 4.24 compared to the total consumption. The total power consumption is

730mW, for 8Gsps (620mW for 4Gsps).


Figure 4.24– ADC power consumption distribution.

IV.III.II. THE TRANSIENT MEASUREMENTS

The objective of the transient measurements is to evaluate the functionality of the

individual parts of the circuit. This evaluation goes from the output to the input

blocks. The TAH was shown to be operational (see Chapter III) and in a first time,

the characterization was performed with the TAH in the tracking mode.

IV.III.II.I. THE LVDS BUFFER AND THE CLOCK DIVIDER

This characterization has started with the clock divider. The clock divider is used

internally to drive the demultiplexer and it is buffered out of the circuit to

synchronize the output data. So, there is a direct path from the input to the output.

The validation of the clock divider allows the observation of the DFF and the LVDS

buffer. The functionality of the DFF is very important for the ADC because they are

also used internally for the sampling, the synchronization after the decoder and the

demultiplexer. The LVDS buffer is used 13 times and it is important to characterize

its behavior.

The validation has started with the LVDS block by observing its output signal.

Firstly, the common-mode of the output has been measured directly on the 100Ω

TAH, 55.20Input

Amp., 59.52

Comps, 64.08

DFFs, 36.60

Encoder, 92.52

Demux, 82.92

Clock Amp., 70.20

Clock Div., 10.92

LVDS Buffers, 82.0

8

Ph. cont., 64.67

Power Consumption

@ 4Gsps(mW)

TAH, 67.20Input

Amp., 63.60

Comps, 72.00

DFFs, 41.76

Encoder, 93.48

Demux, 80.64

Clock Amp., 92.16

Clock Div., 15.24

LVDS Buffers, 83.5

2

Ph. cont., 124.32

Power Consumption

@ 8Gsps(mW)


load and its value is 1.2V, which is the expected one for this buffer. Secondly, an

800MHz clock has been applied to the circuit and the result is presented in figure

4.25. It shows the correct division by 4 performed by the DFFs and also the

acceptable amplitude of about 400mVpp on the load.

Figure 4.25–LVDS transient output for Fclk= 800MHz.

Then, the clock frequency has been increased to its nominal value, 8GHz (some

intermediate frequencies have also been evaluated). The result is presented in figure

4.26. The signal rising and falling edges are limited by the parasitic elements but

the differential voltage is maintained at 400mVpp. The eye-diagram presented in

figure 4.27 shows that despite of the edges behavior, the eye is well opened and the

peak-to-peak jitter is about 17ps.


Figure 4.26–LVDS transient outputfor Fclk= 8GHz.

Figure 4.27–LVDS output eye-diagram for FS=8GHz obtained with 6GHz differential probes.

In order to establish the maximum clock frequency for which the LVDS

functionality is maintained, the clock frequency has been increased above the

nominal value. Due to the losses on the hybrid couplers and cables (estimated

about 5dB), the clock power has been increased. The maximum clock frequency is

then 9.2GHz. However, it was impossible to test it above because the feedback loop

of the clock divider has a natural resonance frequency around 2.3GHz (exactly


9.2GHz/4). The existence of the resonance frequency has also been subsequently

confirmed in a post-layout simulation with no input clock.

With the analysis performed to validate the LVDS buffer, it is clear that the DFFs

are functional because the output of the clock divider was always 𝑐𝑙𝑘 4.

IV.III.II.II. THE DEMULTIPLEXER

Once the functionality of the DFF and the clock divider have been confirmed, it is

possible to evaluate the correct behavior of the demultiplexer.

In order to validate it, the nominal clock frequency has been applied to the ADC.

The evaluation has started with an input frequency of 𝐹𝑆 2 and then the MSB has

been analyzed. In the Nyquist sampling condition, the sampling of a sinus wave will

result in a MSB oscillating from „0‟ to „1‟ with the frequency of the input signal, in

this case, 4GHz. The resulting binary stream would be “..0101010..”. If the

demultiplexer is working properly, this stream would be split in 4 other streams

corresponding to a fourth of the MSB. So, the first part would be composed by ones

(“..10101010..”), the second by zeros (“..10101010..”) and so on. This theoretical

scheme has been seen during the measurements, which result in 4 DC signals

corresponding to the MSB.

The same approach was used for 𝐹𝐼𝑁 = 𝐹𝑆 4 for the MSB binary stream being

“..11001100..”. The 4 parts of the MSB are constant. This situation changes when

𝐹𝐼𝑁 = 𝐹𝑆 8. In this case, the binary stream is “..11110000..”, each fourth of the

MSB changes its logical state at each clock cycle (““..11110000..”).

After all these considerations, the conclusion is that the demultiplexer is functional,

which is coherent with the previous results, from the clock divider, that have shown

that the DFFs were working correctly.

IV.III.II.III. THE ENCODER

The analysis made on the demultiplexer would not be possible if the encoder was

not functional. However, the only bit observed was the MSB. In order to validate the

correct encoding of all 3-bit in Gray code, the following method was used.

Firstly, a very low power signal has been sent to the input. The ADC samples at

8GSPS at Nyquist conditions. The way to use a low amplitude input signal is to


increase its amplitude step-by-step so that all codes can be identified in the correct

sequence. Thus, considering the Gray code (see Table 4.4), a very low amplitude

signal, oscillating around the common-mode voltage, will be converted in codes 3

and 4. If the encoding is performed correctly, when the amplitude increases, the

adjacent codes must start appearing. The expected codes sequence 3/4, 2/5, 1/6

and 0/7 has been correctly verified which validates the encoding process.

TABLE 4.4 – 3-BIT GRAY ENCODING

Code Gray encoded

g2 g1 g0

0 0 0 0

1 0 0 1

2 0 1 1

3 0 1 0

4 1 1 0

5 1 1 1

6 1 0 1

7 1 0 0

IV.III.III. THE DYNAMIC PERFORMANCE

With the previously validations done, the remaining blocks to be characterized

constitute the analog front-end (AFE), which are the TAH, the input amplifier and

the comparators).The main elements of the AFE cannot be characterized

individually in a simple manner; thus, the AFE performance will be evaluated

globally with the rest of the circuit by measuring the SFDR SNR, SINAD, THD and

ENOB parameters.

A statistical analysis of the output data has shown the behavior of each code in

terms of frequency of appearance. Figure 4.28 presents the behavior of one ADC

(several units have been assembled on a test PCB by the LAB – Laboratoire

d'Astrophysique de Bordeaux). It shows that the frequency of appearance of code 5

is not consistent with the other codes. The code 5 should be as frequent as its

opposite, code 2. However, it seems that the appearances of code 5 have been

replaced by those associated with code 6. This could result from an offset on the

sixth comparator, thus, enlarging the thresholds for code six and compressing

those of code 5. The effect of the lack of one bit is the degradation of the resolution.


Eight different codes are needed for 3-bit resolution. Consequently, seven codes

limit the resolution to 2.8-bit (see equation 4.1).

# 𝑜𝑓 𝑐𝑜𝑑𝑒𝑠 = 2𝑛 → 7 = 2𝑛 → 𝑛 = log2 7 = 2.8 (4.1)

Figure 4.28– Frequency of appearance of the output codes.

The second dynamic analysis consisted in using a broad band noise source (the

noise source is from ALMA project) sent to the ADC input. An anti-aliasing filter

with effective bandwidth from 2.1 and 3.9GHz was used during this test where the

whole bandwidth was sampled at 4 GHz clock rate. The spectrum is presented in

figure 4.29. An obvious conclusion can be done: the clock divided by 4 generates a

noise spurious (about 7dB) at the middle of the useful bandwidth, degrading the

ADC performance.

Figure 4.29– Output spectrum of a 2.1-3.9GHz noise input.


This spectral spurious, which has its origin in the clock divided by 4, will be ignored

for the following calculations of the dynamic performance.

Finally, the dynamic performances were obtained from the spectra of the converted

signals. Figure 4.30 presents one of these spectra. It corresponds to a 3.49GHz

input frequency sampled at 7GHz. Twenty conversions have been performed and

the spectra have been averaged to highlight the spurious at 𝐹𝑆

4 − 𝐹𝐼𝑁and 3𝐹𝑆

4 −

𝐹𝐼𝑁. These spurious related to 𝐹𝑆

4 come from the demultiplexer clock.

Figure 4.30– Average output spectrum obtained from 20 individual measurements for a 2.1-3.9GHz

noise input signal.

The results obtained with this analysis are presented in table 4.5.

TABLE 4.5 – DYNAMIC PERFORMANCE

𝑭𝑺 𝑭𝑰𝑵 (GHz) Parameter

ENOB (bits) SFDR (dBc) THD (dB) SNR (dB) SINAD (dB)

8/3.98 24.68 -17.22 13.55 12 1.7

7/3.49 27.00 -20.45 17.77 15.9 2.35

7/7.14 17.99 -17.51 16.70 14.08 2.05

The first analysis leads to the ENOB. The best ENOB is 2.35 (relatively far from the

maximum expected, 3 bits); this is acceptable for this design. The other parameters

given in Table 4.7 are briefly discussed. The SFDR shows that there is a good

dynamic range for the three presented cases. Considering the THD and the SNR,

the SNR seems to be the limiting factor for the SINAD. Thus, this analysis

-50

-40

-30

-20

-10

0

10

0 0.5 1 1.5 2 2.5 3 3.5

Am

plitu

de (

dB

)

Frequency (GHz)


concludes that the SINAD and consequently the ENOB are limited by the noise and

not by the harmonic distortion. One plausible explanation to this fact would be the

clock jitter. The several phase controllers inserted in the clock distribution tree are

responsible for the increasing of the clock jitter. One way to confirm this hypothesis

would be to diminish the jitter by increasing the voltage supply for all blocks related

to the clock tree. The tendency would be to improve the SNR and also the SINAD.

In summary, considering just the power consumption of the useful blocks, from

TAH to the encoder plus the clock amplifier, the figure of merit for the best case

would be 12pJ/conv. step.


IV.IV. NEXT VERSION OF THE ADC

Considering the results presented earlier and the fact that the next prototype is a 6-

bit version, some of the functionalities must be improved. These points are

presented in the following sections. However one point is common for all possible

improvements, the reduction of the static power consumption because it was not a

constraint for this design. Thus, an effort must be done about it for the new

implementations.

IV.IV.I. THE TAH AND THE INPUT AMPLIFIER

The first modification is about the TAH that must be replaced by the enhanced

version presented at the end of Chapter III.

Concerning the input amplifier, it has to be reviewed because of the changes on its

input, with the TAH new design, and also because of the changes on its load, the

comparators. The changes on the comparators, which will increase from 8 to 63,

are discussed in the next section.

IV.IV.II. THE COMPARATORS

These functional blocks are the most critical part of the ADC and they must be

improved for the next version. The approach used here was to use several

differential pairs, in an open-loop configuration, and amplify the difference between

the input and the DC references until the output saturates. However, with the

decreasing of the LSB when the resolution is set to 6-bit, the comparators must

have better performances.

A switched architecture (reset/regeneration phaseswith positive feedback for the

gain) can be studied but at 8GHz the switching phase has a non negligible impact

on the settling times that can limit the operation. Despite the results of this study,

the comparator must be implemented in a differential architecture.

Moreover, the interpolation of the comparator pre-amplifiers could provide a

solution for decreasing the load seen by the input amplifier.

The positioning of the comparators in the layout is also a point that has to be

considered during the routing step. In fact, the foundry process can create

100 Next Version of the ADC

disturbances on the circuit, like the off-set of the comparators, for example. The

processes can also create gradients, linear or not, that would shift a given

characteristic in one direction or in another. To decrease this effect, it is important

to try to compensate the variations with the right positioning of the comparators.

Figure 4.31 shows how to distribute the 15 comparators in the array in order to

decrease the effects of those random gradients on the 4-bit thermometer transfer

function. As the thermometer code increases, the input signal crosses the

thresholds of the comparators that are placed on its opposite site. Consequently,

the gradients are minimized between 2 adjacent comparators.

9 5 13 1 15 3 11 7 8 4 14 2 12 6 10

Figure 4.31– Comparators distribution for compensating the random process gradients on the 4-bit

thermometer transfer function.

IV.IV.III. THE ENCODER

Despite the correct functionality of the encoding block was demonstrated, it would

not be applicable for a 6-bit ADC. The encoding from thermometer to „one-hot‟ can

still be done because it does not demand too many hardware to be implemented

(only 64 NANDs) and an easy routing. However, the encoding from „one-hot‟ to Gray

code, which is simply an OR operation, becomes more complicated to be done with

the differential pairs. The use of the current architecture is not allowed because of

the small weight of each „one-hot‟ bit in the totality of the differential pairs and also

the current consumption would exponentially increase. Thus, the solution would be

an encoder made entirely by logical gates; this requires 31 ANDs and 30 2-input

ORs. Nevertheless, the parasitic capacitance attached to each thermometer bit

depends on the number of gates that load this particular bit. In this encoding, the

LSB would have a load 32 times greater than the MSB and will consequently be

slower.

IV.IV.IV. THE DEMULTIPLEXER

It was already known from the beginning that the integration of a demultiplexer

would introduce spectral noise components inside the useful bandwidth and the

measurements prove it. However, this design was adopted to allow making test

left right


measurements with the existing equipment. Currently, the design team at LAB is

working on a solution for this issue. It combines a scrambling circuit working at a

fast output data rate with a fast commercial FPGA where the final demultiplexing

stage is being performed. Consequently, the demultiplexer is not needed anymore

inside the chip and the spectral spurious it generates will be eliminated.This would

significantly improve the effective number of bits.

102 References

IV.V. REFERENCES

[4.1] Chao-Hsin Lu et al., “Bandwidth enhancement techniques for transimpedance

amplifier in CMOS technologies,” in Proceedings of the European Solid-State Circuit

Conference, Sept. 2001, ESSCIRC 2001, p. 174-177.

[4.2] Pelgrom, M.J.M. et al., “Matching properties of MOS transistors,” in IEEE

Journal of Solid-State Circuits, Oct. 1989, vol. 24, p. 1433-1439.

103

CHAPTER V - CONCLUSION

The conclusion will resume all

achievements of this work and also

the perspectives for further

improvements. At the end, the

publications originated in this work

are listed.

104 Theory and Motivations

V.I. THEORY AND MOTIVATIONS

The principles behind the A/D conversion have been presented and explained in

Chapter I. They allow the understanding of sampling theorem and the non-idealities

inherent to the conversion.

Some ADC architectures have been presented in Chapter II so that the best one

could be chosen for this design, considering the given application. SAR, pipeline

ADC and Flash architectures have been explained with their strengths and

weaknesses. Finally, the ADC uses a flash architecture for its rapidity and wide

bandwidth.

The wide bandwidth is a characteristic of the application in radio astronomy, like it

was presented in Chapter I. When observing cosmic signals in the millimeter and

sub-millimeter domains extremely wide bandwidths are used and subdivided in

narrow channels in order to perform the digitization. The same wideband

constraints have motivated this work because of the restricted bandwidths found in

commercial devices.

V.II. DESIGN AND IMPLEMENTATION

From Chapter III, the choices and solutions of this work have been presented. The

design phases of two different prototypes have been specified.

Initially, the TAH design, fabrication details and measurements have been

described. Measurements have confirmed the design methodology when the

expected performances have been found in the test bench. Considering the 5.8

effective bits of the TAH obtained during the measurements, it is not enough for the

6-bit application, which demands more than 6 effective bits from the TAH to not

limit the entire system performance. The information obtained in the tests, revealed

some improvement possibilities, which are explained at the end of Chapter III. This

is the new TAH which will be used for integration to the ADC. However, for ALMA

2nd generation instruments, 4 bits applications could be sufficient.

During Chapter IV, the ADC design has been presented. All functional blocks have

been described and a first 3-bit resolution prototype has been shown. In addition,

measurement activities have been explained in order to allow the understanding of

CHAPTER V - CONCLUSION 105

the debugging procedures used to comprehend all the different functionalities

inside the ADC.

The final best-case performance obtained in tests 2.35 effective bits at 7Gsps (which

corresponds to a figure of merit of 12pJ/conv. step) and 3.49GHzinput frequency is

far from the ideal but considering the challenges of this design it is acceptable. Also

all the information gathered during the measurements of the ADC, lets some good

perspectives for the next implementation. The circuit is better known but not

completely characterized.

Some more measurements must be performed to identify what is the cause for

degrading the spectral performance. The possibilities are the analog front-end (TAH

and Input Amplifier) the comparators and DFFs, and the clock. This procedure

could be, for example, increase the voltage supply of the referred functional blocks,

in order to increase the gain of the amplifiers and comparators and decrease the

clock jitter.

Overall, as a first prototype this circuit has already provided good information and

experience in ADC characterization and this is very useful for the further works,

although there is still some work to be done.

Moreover, some possibilities of improvements for the next implementations have

been presented in Chapter IV. They concern all functional blocks and are based on

the experience of measurements and simulations.

Finally, we mention that the CMOS 65nm technology would be well adapted for

space projects. This possibility has not been explored here, but the present

architecture and our 3-bit design could be used as the starting point of future

designs for space astronomy projects where a large number of bits is not required.

V.III. THE LIST OF PUBLICATIONS

The achievements of this work, in terms of ultra high frequency analog and mixed-

signal design, have been presented and published in several events and institutions

(3 international conferences, where two are from IEEE, 1 French national

conference and 1 international journal). The references of the publications are listed

in the following:

106 The List of Publications

D. Mattos, J.-B. Begueret, A. Baudry, “Design and fabrication of a fast,

multi-bits analog-to-digital converter for astrophysics and cosmology

applications”, in Young European Radio Astronomers Conference, YERAC

2010, Madrid, Spain (presentation without publication).

D. Mattos, J.-B. Begueret, A. Baudry, “Conception d‟un Convertisseur

Analogique-Numérique pour des Applications en Radioastronomie et

Cosmologie”, in Journées Nationales du Réseau Doctoral en Micro-

nanoélectronique, JNRDM 2011, Paris, France.

D. Mattos, P. Hellmuth, C. Recoquillon, S. Gauffre, P. Caïs, J-L. Pedroza, J-

B. Bégueret, A. Baudry, “An 8Gsps, 65nm CMOS Wideband Track-and-Hold,”

NEWCAS 2011,Bordeaux, France.

D. Mattos, P. Hellmuth, S. Gauffre, P. Caïs, J-L. Pedroza, J-B. Bégueret, A.

Baudry, “Design of an 8Gsps,65nmCMOS Wideband Flash ADC”, ICECS

2011,Beirut, Lebanon.

D. Mattos, P. Hellmuth, C. Recoquillon, S. Gauffre, P. Caïs, J-L. Pedroza, J-

B. Bégueret, A. Baudry, “Design of a 65 nm CMOS 8GHz wideband track-

and-hold, for radio astronomy and cosmology applications”, Analog

Integrated Circuits and Signal Processing Journal, vol. 73, issue3, December

2012.

REFERENCES 107

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amplifier in CMOS technologies,” in Proceedings of the European Solid-State Circuit

Conference, Sept. 2001, ESSCIRC 2001, p. 174-177.

[4.2] Pelgrom, M.J.M. et al., “Matching properties of MOS transistors,” in IEEE

Journal of Solid-State Circuits, Oct. 1989, vol. 24, p. 1433-1439.

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