Lessons for MEMS Test Engineers - Ira Feldman 111020
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Feldman Engineering
Semiconductor Wafer Test Technology and Trends:
Lessons for MEMS Test Engineers
Ira Feldman
October 20, 2011
MEMS Testing & Reliability Conference 2011 © 2011 Feldman Engineering Corp.
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Outline } Market Dynamics } Testing Semiconductors vs. MEMS } Cost of Test
} Semiconductor Solutions
} MEMS Challenges } MEMS @ Semiconductor Wafer Test Workshop } Conclusion
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MEM
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~ 5.5 B Units
“MEMS Roadmap: From Device to Function” Jean-Christophe Eloy, Semicon West 2011
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DRAM
MEM
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4 http://www.dramexchange.com/Market/market_activity.aspx
~ 17.4 B Units
in 2011
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Cost of Test – Constant Pressure
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5 “Wafer Level Testing – Challenges and Opportunities” Vikas Sharma, Intel Corporation
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Package Proliferation
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6 “Backend to the Front Line” William Chen, ASE Group, SWTW 2011
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Outline } Market Dynamics } Testing Semiconductors vs. MEMS } Cost of Test
} Semiconductor Solutions
} MEMS Challenges } MEMS @ Semiconductor Wafer Test Workshop } Conclusion
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Device Testing
Device Under Test
(DUT) Stimulus Response Correct?
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Traditional Wafer Probe Test Cell
Stimulus
Response
The
rmal
Electrical
DUT
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Verigy / Advantest
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Stimulus & Response - Traditional
Device Under Test
(DUT)
Electrical
Electrical
Thermal
• Semiconductors • Oscillators • MEMS switches • MEMS filters • MEMS oscillators
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Stimulus & Response - Optical
Device Under Test
(DUT)
Electrical
Electrical
Thermal
• Image Sensors • LEDs • Micro- / Pico -projectors (DLP, etc.) • Micro bolometers
Optical
Optical
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Stimulus & Response – MEMS Sensors
Device Under Test
(DUT)
Electrical
Electrical Thermal
• Accelerometers • Gyroscopes • Magnetic Compass • Microphones • Speakers • Pressure sensors …
Motion
Magnetic
Pressure
Pressure
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Stimulus & Response – Life Science + ?
Device Under Test
(DUT)
Electrical
Electrical
Thermal
• Valves • Pumps • Mixers • Micro reactors • Sensors • Micro explosives …
Mass
Mass
Optical
Optical
Mass include movement of material in / out of DUT such as fluids & gas. 13
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Device Testing
Device Under Test
(DUT) Stimulus Response Correct?
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Outline } Market Dynamics } Testing Semiconductors vs. MEMS } Cost of Test
} Semiconductor Solutions
} MEMS Challenges } MEMS @ Semiconductor Wafer Test Workshop } Conclusion
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Cost of Test Drivers
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Increased Cost
Increasing transistor
count
Increasing test
frequency
Tighter pad
pitches
Increasing probe count
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Semiconductor Cost - Test Solutions
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Test Reduction
Increased Parallelism
Test Partitioning
Lower Cost
Silicon Velocity
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MEM
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18 ww
w.b
obss
pace
race
rs.c
om
Conflicting & Counter Intuitive Solutions
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Semiconductor Cost - Test Solutions
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Test Reduction
Increased Parallelism
Test Partitioning
Lower Cost
Silicon Velocity
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- Test Escapes - Run time complexity + Statistical based sampling + Test elimination
Test Reduction
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- Increased probe card cost - Increased tester resources + Decreased handling time + Greater prober amortization + Reduced floor space + Increased Silicon Velocity
Increased Parallelism
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- Increased process steps - Increased process complexity + Optimized high-cost ATE
Test Partitioning
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MEM
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23 “Bemo – Nemo – Remo, The Trifurcation of the ATE Industry”, Jim Healy, Sony LSI Design, ATE Vision July 2011
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Outline } Market Dynamics } Testing Semiconductors vs. MEMS } Cost of Test
} Semiconductor Solutions
} MEMS Challenges } MEMS @ Semiconductor Wafer Test Workshop } Conclusion
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MEM
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Manual Alignment
Electroglas 2001 ca. 1982-5 www.vortexcontrolsystems.com 25
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Cantilever & Blade
Technoprobe
SV Probe
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Vestigial Microscope Hole
27 Verigy V5400 Testhead
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path for non-electrical stim
ulus?
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Vertical - Buckling Beam
Mann: SWTW Tutorial 2004
SV Probe “Trio”
FormFactor: “MEMS for ProbeCard Applications” Chong Chan Pin – Semicon Singapore 2010
JEM “VC” 28
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Vertical - Buckling Beam
MicroProbe: Apollo Vertical
JEM: VC
SV Probe: Trio 29
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MEMS - Vertical
Microfabrica MicroProbe
MicroProbe (Vx-MP)
FormFactor (T1)
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MEMS - Micro Cantilever
Microfabrica
http://www.mjc.co.jp/eng/ir/pdf/MJC070226-s.pdf
MJC (U Probe)
FormFactor (T3)
JEM 31
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Vertical Probe Head
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MicroProbe Apollo
Printed Circuit Board
Space Transformer
BGA (Solder Attach)
Upper Guide Plate
Lower Guide Plate
Spacer
Probes
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PCB
Stiffener
Probe Head
FormFactor CMOS Imaging Solution
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Outline } Market Dynamics } Testing Semiconductors vs. MEMS } Cost of Test
} Semiconductor Solutions
} MEMS Challenges } MEMS @ Semiconductor Wafer Test Workshop } Conclusion
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SWTW 2011
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"MSO - Multi-Site Optimizer" Kevin Fredriken
(SPA GmbH - Germany)
• MEMS device alternating rotation across wafer à required two probe passes.
• No probe of cap or wafer exclusion zone
• Developed four site probe card and stepping algorithm using MSO. Inclusive probing with multi-probes on some die.
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SWTW 2011
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"Probe to Pad Placement Error Correction for Wafer Level S-
Parameter Measurements" Steven Ortiz
(Avago Technologies - USA)
• FBAR structure – resonator plus cap wafer. Vias through cap wafer to resonator.
• Due to very high frequency and tight specification tolerance, very sensitive to location of probes on pad. à Implemented “calibration” structures to de-embed the measurements.
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SWTW 2011
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"Ghosting - Touchdown Reduction Using Alternate Site Sharing" Doron Avidar and Yossi Dadi (Micron - Israel)
When using large multisite arrays that need > 3 touchdowns / wafer, “ghosting” may save several touchdowns. Examples showed12 to 20% savings.
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Summary
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} Proven semiconductor cost reduction techniques } Not always intuitive } Require test engineering } Can be applied to MEMS
} MEMS wafer test challenge } Multi-site stimulus and response } Proper probe card architectures required } Solution integration support
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Resources
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} IEEE Semiconductor Wafer Test Workshop (SWTW) } http://www.swtest.org
} International SEMATECH Manufacturing Initiative (ISMI) Probe Card Cost Model } http://ismi.sematech.org/modeling/probeCOO.htm
} SEMI E35-0307 } Guide to Calculate Cost of Ownership (COO) Metrics for
Semiconductor Manufacturing Equipment
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Thank You!
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Ira Feldman [email protected]
Visit my blog
www.hightechbizdev.com for additional test resources.