Lecture11 Computer

7/28/2019 Lecture11 Computer

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The CPU and Memory

With slides from:

The Architecture of Computer Hardware andSystems Software:

An Information Technology Approach

3rd Edition, Irv Englander

Lecture 11 - CPU and Memory 2

CPU: 3 Major Components

ALU(arithmetic logic unit) Performs calculations and comparisons (data changed)

CU(control unit): performs fetch/execute cycle Functions:

Moves data to and from CPU registers and other hardwarecomponents (no change in data)

Accesses program instructions and issues commands to theALU

Subparts: Memory management unit: supervises fetching instructions and

data

I/O Interface: sometimes combined with memory managementunit as Bust Interface Unit

Registers Example: Program counter (PC) orinstruction pointer

determines next instruction for execution


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System Block Diagram


The Little Man Computer


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Concept of Registers

Small,permanentstorage locations within the

CPU used for a particular purpose

Manipulated directly by the Control Unit

Wired forspecific function

Size in bits or bytes (not MB like memory)

Can hold data, an address or an instruction

How many registers does the LMC have?


Registers

Use of Registers Scratchpad for currently executing program

Holds data needed quickly or frequently

Stores information about status of CPU and currentlyexecuting program

Address of next program instruction

Signals from external devices

General Purpose Registers

User-visible registers

Hold intermediate results or data values, e.g., loop counters

Equivalent to LMCs calculator

Typically several dozen in current CPUs


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Special-Purpose Registers

Program Count Register(PC)

Also called instruction pointer Instruction Register (IR) Stores instruction fetched from memory

Memory Address Register (MAR)

Memory Data Register (MDR)

Status Registers Status of CPU and currently executing program

Flags (one bit Boolean variable) to track conditionlike arithmetic carry and overflow, power failure,

internal computer error


Register Operations

Stores values from other locations

(registers and memory)

Addition and subtraction

Shift or rotate data Test contents for conditions such as

zero or positive


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Operation of Memory

Each memory location has a unique address

Address from an instruction is copied to the

MAR which finds the location in memory

CPU determines if it is a store or retrieval

Transfer takes place between the MDR and

memory

MDR is a two way register


Relationship between MAR,

MDR and MemoryAddress Data


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MAR-MDR Example


Visual Analogy of Memory


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Individual Memory Cell


Memory Capacity

Determined by two factors1. Number of bits in the MAR

LMC = 100 (00 to 99)

2K where K = width of the register in bits

2. Size of the address portion of the instruction 4 bits allows 16 locations 8 bits allows 256 locations

32 bits allows 4,294,967,296 or 4 GB

Important for performance Insufficient memory can cause a processor to

work at 50% below performance


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RAM: Random Access Memory

DRAM (Dynamic RAM)

Most common, cheap

Volatile: must be refreshed (recharged with power)

1000s of times each second

SRAM (static RAM)

Faster than DRAM and more expensive than

DRAM

Volatile

Frequently small amount used in cache memory

for high-speed access used


ROM - Read Only Memory

Non-volatile memory to hold software that isnot expected to change over the life of thesystem

Magnetic core memory

EEPROM

Electrically Erasable Programmable ROM Slower and less flexible than Flash ROM

Flash ROM Faster than disks but more expensive

Uses BIOS: initial boot instructions and diagnostics

Digital cameras


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Fetch-Execute Cycle

Two-cycle process because both

instructions and data are in memory

Fetch

Decode or find instruction, load from

memory into register and signal ALU

Execute

Performs operation that instruction requires

Move/transform data


LMC vs. CPU

Fetch and Execute Cycle


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Load Fetch/Execute Cycle

Program Counter incremented5. PC + 1 -> PC

Actual data copied into the

accumulator

4. MDR -> A

Address portion of the

instruction loaded in MAR

3. IR(address) -> MAR

Transfer the instruction to the

IR

2. MDR -> IR

Transfer the address from the

PC to the MAR

1. PC -> MAR


Store Fetch/Execute Cycle


Accumulator copies data into

MDR

4. A -> MDR*

*Notice how Step #4 differs for LOAD and STORE





IR

2. MDR -> IR


PC to the MAR

1. PC -> MAR


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ADD Fetch/Execute Cycle


Contents of MDR added to

contents of accumulator

4. A + MDR -> A





IR

2. MDR -> IR


PC to the MAR

1. PC -> MAR


LMC Fetch/Execute

SUBTRACT

PC MAR

MDR IR

IR[addr] MAR

A MDRA

PC + 1 PC

IN

PC MAR

MDR IR

IOR A

PC + 1 PC

OUT

PC MAR

MDR IR

A IOR

PC + 1 PC

HALT

PC MAR

MDR IR

BRANCH

PC MAR

MDR IR

IR[addr] PC

BRANCH on Condition

PC MAR

MDR IR

If condition false: PC + 1 PC

If condition true: IR[addr] PC


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Bus

The physical connection that makes it possible

to transfer data from one location in thecomputer system to another

Group of electrical conductors for carryingsignals from one location to another Line: each conductor in the bus

4 kinds of signals1. Data (alphanumeric, numerical, instructions)

2.Addresses

3. Control signals

4. Power (sometimes)


Bus

Connect CPU and Memory

I/O peripherals: on same bus as

CPU/memory or separate bus

Physical packaging commonly called

backplane Also called system bus orexternal bus

Example ofbroadcast bus

Part of printed circuit board called motherboard

that holds CPU and related components


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Bus Characteristics

Protocol

Documented agreement for communication

Specification that spells out the meaning of

each line and each signal on each line

Throughput, i.e., data transfer rate in

bits per second

Data width in bits carried simultaneously


Point-to-point vs. Multipoint

BroadcastbusExample:Ethernet

Plug-indevice

Shared amongmultiple devices


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Instructions

Instruction

Direction given to a computer Causes electrical signals to be sent through specific circuits

for processing

Instruction set Design defines functions performed by the processor

Differentiates computer architecture by the

Number of instructions

Complexity of operations performed by individual instructions

Data types supported

Format (layout, fixed vs. variable length)

Use of registers

Addressing (size, modes)


Instruction Elements

OPCODE: task

Source OPERAND(s)

Result OPERAND

Location of data (register, memory) Explicit: included in instruction

Implicit: default assumed

OPCODESource

OPERAND

Result

OPERAND

Addresses


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Instruction Format

Machine-specifictemplate that specifies

Length of the op code

Number of operands

Length of operands

Simple

32-bit

Instruction

Format


Instruction Types

Data Transfer (load, store) Most common, greatest flexibility

Involve memory and registers

Whats a word? 16? 32? 64 bits?

Arithmetic

Operators+ - / *

Integers and floating point

Logical or Boolean Relational operators: > < =

Boolean operators AND, OR, XOR, NOR, and NOT

Single operand manipulation instructions Negating, decrementing, incrementing


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More Instruction Types

Bit manipulation instructions

Flags to test for conditions

Shift and rotate

Program control

Stack instructions

Multiple data instructions

I/O and machine control


Register Shifts and Rotates


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Homework

Consider an extended LMC instruction set

that allows indirection:

LDI xx load indirectly from memory

xx indicates where in the memory to load from

STI xx store indirectly into the memory

xx indicates where in the memory to store

Try again the exercises given previously as

homework, where a variable number of

data needs to be stored in the memory


Extra-credit work

Mr. Smith and his wife invited four othercouples for a party. When everyone arrived,some people in the room shook hands withsome of the others. Of course, nobody shookhands with their spouse and nobody shook

hands with the same person twice. After that, Mr. Smith asked everyone how

many times they shook someones hand. Hereceived different answers from everybody.

How many times did Mrs. Smith shakesomeones hand ?

Lecture11 Computer

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