Lecture 7: Datapath - Princeton University Computer Science · Lecture 7: Datapath COS / ELE 375...
Transcript of Lecture 7: Datapath - Princeton University Computer Science · Lecture 7: Datapath COS / ELE 375...
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Lecture 7: Datapath
COS / ELE 375
Computer Architecture and Organization
Princeton University Fall 2015
Prof. David August
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Datapath
Datapath �The component of the processor that performs arithmetic operations� – P&H
Datapath
The collection of state elements, computation elements, and interconnections that together provide a conduit for the flow and transformation of data in the processor during execution. - DIA
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Datapath - Part of the Microarchitecture
Architecture • The ISA - the programmer�s view of the machine • Implementation independent, an interface
Microarchitecture • The lower-level implementation of the ISA • Design specific, an implementation
Example use of terminology • Architectural state: Register r5 • Microarchitectural state: Carry bit on the 5th 1-bit ALU
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Datapath Elements
• ALUs are just one datapath building block • What about the other elements?
Computational Elements • Combination Circuits • Outputs follow inputs • Familiar Example: ALU
State Elements • Sequential Circuits • Outputs change on clock edge • Familiar Example: A Register
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• Combinational - you had better know how to design it by now!!! • Refine for MIPS
• Zero equality test on all results - why? • Set on less than for slt instruction
Computation Element: ALU
A L U c o n t r o l 3
ALU Result Zero
ALU Control Function 000 AND 001 OR 010 add 110 subtract 111 set on less than
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• 16 à 32 bit Sign extender • Why is this necessary in MIPS?
• Hint:
Computation Element: Sign Extender
1 6 3 2 S i g n
E x t e n d
Implementation?
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• Not an ALU, just add • Why would we need this in MIPS to execute instructions?
Computation Element: Adder
A d d S u m
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Computational Element: The Magical Mux
• Mux is short for Multiplexer (Think: selector) • n input lines (of any common width) • m control wires to select • n = 2m
M u x
Control
in0
inn
out
m
Implementation?
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• Microarchitecture to implement architectural state • Built using D flip-flops • MIPS:
• Need to be able to read two operands at once • 2 source operands per instruction
State Element: Register File
R e g W r i t e
R e g i s t e r s W r i t e r e g i s t e r
R e a d d a t a 1
R e a d d a t a 2
R e a d r e g i s t e r 1 R e a d r e g i s t e r 2
W r i t e d a t a D a t a
D a t a R e g i s t e r n u m b e r s 5
5
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5-bits? 2 Reads? 1 Write?
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State Element: Register File Register Implementation
Falling edge triggered D flip-flop
D latch
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State Element: Register File Read Implementation
R e g W r i t e
R e g i s t e r s W r i t e r e g i s t e r
R e a d d a t a 1
R e a d d a t a 2
R e a d r e g i s t e r 1 R e a d r e g i s t e r 2
W r i t e d a t a D a t a
D a t a R e g i s t e r n u m b e r s 5
5
5
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State Element: Register File Write Implementation
R e g W r i t e
R e g i s t e r s W r i t e r e g i s t e r
R e a d d a t a 1
R e a d d a t a 2
R e a d r e g i s t e r 1 R e a d r e g i s t e r 2
W r i t e d a t a D a t a
D a t a R e g i s t e r n u m b e r s 5
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Know decoders
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State Element: Data and Instruction Memory
• Microarchitectural element to hold the architectural memory state
• See Appendix B for implementation details
M e m R e a d
M e m W r i t e
D a t a m e m o r y W r i t e
d a t a R e a d d a t a A d d r e s s
I n s t r u c t i o n m e m o r y
I n s t r u c t i o n a d d r e s s
I n s t r u c t i o n
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State Element: The Program Counter
• To hold the architectural PC state • Just like a single register
P C
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Our Complete Line of Products! There may be others, but this is good for MIPS
A L U c o n t r o l
R e g W r i t e
R e g i s t e r s W r i t e r e g i s t e r
R e a d d a t a 1
R e a d d a t a 2
R e a d r e g i s t e r 1 R e a d r e g i s t e r 2
W r i t e d a t a
A L U r e s u l t A L U
D a t a D a t a
R e g i s t e r n u m b e r s Z e r o 5
5
5 3
P C I n s t r u c t i o n
m e m o r y
I n s t r u c t i o n a d d r e s s
I n s t r u c t i o n A d d S u m
1 6 3 2 S i g n
e x t e n d
M e m R e a d
M e m W r i t e
D a t a m e m o r y W r i t e
d a t a
R e a d d a t a A d d r e s s
M u x
Control
in0
inn
out
m
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Fetching Instructions (no branching)
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The ALU (R-Type) Instructions
Consider: r1 = r2 - r3
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Load and Store Instructions
Consider: r1 = M[ r2 - 3 ]
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Composition of Memory and R-Type Datapath The Magic of the Mux
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Recall Fetch
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Now Add Instruction Fetch
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Now Add Instruction Fetch (ALU + MEM + Fetch)
Data and Instruction memory?
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Branch Instructions
Consider: Branch r1 == 0, TARGET
Why shift left by 2?
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Add Branch to Datapath (ALU + MEM + Fetch + Branch)
What will zero be connected to?
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MIPS Instruction Quirk • The Destination Register may be in different locations
• 11-15: Loads use rt • 16-20: All R-Types use rd
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Again, The Magic of the Mux!
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Ugh, what is going on here!?!
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Control vs. Datapath (Blurring the Line)
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What is Control?
Control �The component of the processor that commands the datapath, memory, and I/O devices according to the instructions of the program.� – P&H
Control
The component of the processor that commands the datapath, memory, and I/O devices according to the instructions of the program. - DIA
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Full Datapath with Control
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Summary and Next Steps
• The book doesn�t define datapath well • Computation and State elements compose datapath • Look for reuse across instruction types • Build minimal HW datapath with the magic of the mux
Next Steps • Need to define control • Understand Timing
• Single cycle • Multi-cycle
• Understand how to implement control
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For Next Time
• Review finite state machines: