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![Page 1: ECE 232 L12.Datapath.1 Adapted from Patterson 97 ©UCBCopyright 1998 Morgan Kaufmann Publishers ECE 232 Hardware Organization and Design Lecture 12 Datapath.](https://reader030.fdocuments.us/reader030/viewer/2022032523/56649d7d5503460f94a5fa03/html5/thumbnails/1.jpg)
ECE 232 L12.Datapath.1 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
ECE 232
Hardware Organization and Design
Lecture 12
Datapath Design(single-cycle)
www.ecs.umass.edu/ece/labs/vlsicad/ece232/spr2002/index_232.html
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ECE 232 L12.Datapath.2 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Outline
° Design a processor: step-by-step
° Requirements of the Instruction Set
° Components and clocking
° Assembling an adequate Datapath
° Controlling the Datapath
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ECE 232 L12.Datapath.3 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
The Big Picture: Where are We Now?
° The Five Classic Components of a Computer
° Today’s Topic: Design a Single Cycle Processor
Control
Datapath
Memory
ProcessorInput
Output
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ECE 232 L12.Datapath.4 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
The Big Picture: The Performance Perspective
° Performance of a machine is determined by:• Instruction count
• Clock cycle time
• Clock cycles per instruction
° Processor design (datapath and control) will determine:• Clock cycle time
• Clock cycles per instruction
° Today:• Single cycle processor:
- Advantage: One clock cycle per instruction
- Disadvantage: long cycle time
CPI
Inst. Count Cycle Time
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ECE 232 L12.Datapath.5 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
How to Design a Processor: step-by-step
° 1. Analyze instruction set => datapath requirements• the meaning of each instruction is given by the register transfers
• datapath must include storage element for ISA registers
- possibly more
• datapath must support each register transfer
° 2. Select set of datapath components and establish clocking methodology
° 3. Assemble datapath meeting the requirements
° 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
° 5. Assemble the control logic
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ECE 232 L12.Datapath.6 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
The MIPS Instruction Formats
° All MIPS instructions are 32 bits long. The three instruction formats:
• R-type
• I-type
• J-type
° The different fields are:• op: operation of the instruction
• rs, rt, rd: the source and destination register specifiers
• shamt: shift amount
• funct: selects the variant of the operation in the “op” field
• address / immediate: address offset or immediate value
• target address: target address of the jump instruction
op target address
02631
6 bits 26 bits
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
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ECE 232 L12.Datapath.7 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Step 1a: The MIPS-lite Subset for today
° ADD and SUB• addU rd, rs, rt
• subU rd, rs, rt
° OR Immediate:• ori rt, rs, imm16
° LOAD and STORE Word• lw rt, rs, imm16
• sw rt, rs, imm16
° BRANCH:• beq rs, rt, imm16
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
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ECE 232 L12.Datapath.8 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Logical Register Transfers
° RTL gives the meaning of the instructions
° All start by fetching the instruction
op | rs | rt | rd | shamt | funct = MEM[ PC ]
op | rs | rt | Imm16 = MEM[ PC ]
inst Register Transfers
ADDU R[rd] <– R[rs] + R[rt]; PC <– PC + 4
SUBU R[rd] <– R[rs] – R[rt]; PC <– PC + 4
ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4
LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4
STORE MEM[ R[rs] + sign_ext(Imm16) ] <– R[rt]; PC <– PC + 4
BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00
else PC <– PC + 4
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ECE 232 L12.Datapath.9 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Step 1: Requirements of the Instruction Set
° Memory• instruction & data
° Registers (32 x 32)• read RS
• read RT
• Write RT or RD
° PC
° Extender
° Add and Sub register or extended immediate
° Add 4 or extended immediate to PC
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ECE 232 L12.Datapath.10 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Step 2: Components of the Datapath
° Combinational Elements
° Storage Elements• Clocking methodology
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ECE 232 L12.Datapath.11 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Combinational Logic Elements (Basic Building Blocks)
° Adder
° MUX
° ALU
32
32
A
B32
Sum
Carry
32
32
A
B32
Result
OP
32A
B32
Y32
Select
Ad
der
MU
XA
LU
CarryIn
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ECE 232 L12.Datapath.12 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Storage Element: Register (Basic Building Block)
° Register• Similar to the D Flip Flop except
- N-bit input and output
- Write Enable input
• Write Enable:
- negated (0): Data Out will not change
- asserted (1): Data Out will become Data In
Clk
Data In
Write Enable
N N
Data Out
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ECE 232 L12.Datapath.13 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Storage Element: Register File
° Register File consists of 32 registers:
• Two 32-bit output busses:
busA and busB
• One 32-bit input bus: busW
° Register is selected by:• RA (number) selects the register to put on busA (data)
• RB (number) selects the register to put on busB (data)
• RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1
° Clock input (CLK) • The CLK input is a factor ONLY during write operation
• During read operation, behaves as a combinational logic block:
- RA or RB valid => busA or busB valid after “access time.”
Clk
busW
Write Enable
3232
busA
32busB
5 5 5RWRARB
32 32-bitRegisters
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ECE 232 L12.Datapath.14 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Storage Element: Idealized Memory
° Memory (idealized)• One input bus: Data In
• One output bus: Data Out
° Memory word is selected by:• Address selects the word to put on Data Out
• Write Enable = 1: address selects the memoryword to be written via the Data In bus
° Clock input (CLK) • The CLK input is a factor ONLY during write operation
• During read operation, behaves as a combinational logic block:
- Address valid => Data Out valid after “access time.”
Clk
Data In
Write Enable
32 32DataOut
Address
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ECE 232 L12.Datapath.15 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Clocking Methodology
° All storage elements are clocked by the same clock edge
° Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew
° (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time
Clk
Don’t Care
Setup Hold
.
.
.
.
.
.
.
.
.
.
.
.
Setup Hold
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ECE 232 L12.Datapath.16 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Step 3
° Register Transfer Requirements –> Datapath Assembly
° Instruction Fetch
° Read Operands and Execute Operation
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ECE 232 L12.Datapath.17 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
3a: Overview of the Instruction Fetch Unit
° The common RTL operations• Fetch the Instruction: mem[PC]
• Update the program counter:
- Sequential Code: PC <- PC + 4
- Branch and Jump: PC <- “something else”
32
Instruction WordAddress
InstructionMemory
PCClk
Next AddressLogic
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ECE 232 L12.Datapath.18 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
3b: Add & Subtract
° R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt
• Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields
• ALUctr and RegWr: control logic after decoding the instruction
32
Result
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs RtRd
AL
U
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
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ECE 232 L12.Datapath.19 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Register-Register Timing
Clk
PC
ALUctr
RegWr
busA, B
busW
Rs, Rt, Rd,Op, Func
Clk-to-Q
Instruction Memory Access Time
Old Value New Value
Old Value New Value
Delay through Control Logic
Register File Access TimeOld Value New Value
ALU Delay
Old Value New Value
Old Value New Value
New ValueOld Value
32Result
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb32 32-bitRegisters
Rs RtRd
AL
U
Register WriteOccurs Here
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ECE 232 L12.Datapath.20 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
3c: Logical Operations with Immediate° R[rt] <- R[rs] op ZeroExt[imm16] ]
32
Result
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs
RtRdRegDst
ZeroE
xt
Mu
x
Mux
3216imm16
ALUSrc
AL
U
11
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits rd?
immediate
016 1531
16 bits16 bits
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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ECE 232 L12.Datapath.21 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
3d: Load Operations
° R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16
11
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits rd
ExtOp
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs
RtRd
RegDst
Exten
der
Mu
x
Mux
3216
imm16
ALUSrcClk
Data InWrEn
32
Adr
DataMemory
32
AL
U
MemWr Mu
x
W_Src
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ECE 232 L12.Datapath.22 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
3e: Store Operations
° Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
ALUSrcExtOp
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
Rd
RegDst
Exten
der
Mu
x
Mux
3216imm16
Clk
Data InWrEn
32
Adr
DataMemory
MemWr
AL
U
32
Mu
x
W_Src
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ECE 232 L12.Datapath.23 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
3f: The Branch Instruction
° beq rs, rt, imm16
• mem[PC] Fetch the instruction from memory
• Equal <- R[rs] == R[rt] Calculate the branch condition
• if (COND eq 0) Calculate the next instruction’s address
- PC <- PC + 4 + ( SignExt(imm16) x 4 )
• else
- PC <- PC + 4
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
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ECE 232 L12.Datapath.24 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Datapath for Branch Operations
° beq rs, rt, imm16 Datapath generates condition (equal)
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
32
imm16
PC
Clk
00
Ad
der
Mu
x
Ad
der
4nPC_sel
Clk
busW
RegWr
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs Rt
Eq
ual
?
Cond
PC
Ext
Inst Address
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ECE 232 L12.Datapath.25 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Putting it All Together: A Single Cycle Datapath
imm
16
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
3216imm16
ALUSrcExtOp
Mu
x
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWrA
LU
Equal
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRtRs
=
Ad
der
Ad
der
PC
Clk
00Mu
x
4
nPC_sel
PC
Ext
Adr
InstMemory
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ECE 232 L12.Datapath.26 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
An Abstract View of the Critical Path° Register file and ideal memory:• The CLK input is a factor ONLY during write operation
• During read operation, behave as combinational logic:
- Address valid => Output valid after “access time.”
Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew
Clk
5
Rw Ra Rb
32 32-bitRegisters
RdA
LU
Clk
Data In
DataAddress
IdealData
Memory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
16Imm
32
323232
A
B
Nex
t A
dd
ress
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ECE 232 L12.Datapath.27 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Step 4: Given Datapath: RTL -> Control
ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal
Instruction<31:0>
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
Adr
InstMemory
DATA PATH
Control
Op
<21:25>
Fun
RegWr
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ECE 232 L12.Datapath.28 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Meaning of the Control Signals (see slide 28)° Rs, Rt, Rd and Imed16 hardwired into datapath
° nPC_sel: 0 => PC <– PC + 4; 1 => PC <– PC + 4 + SignExt(Im16) || 00
Adr
InstMemory
Ad
der
Ad
der
PC
Clk
00Mu
x
4
nPC_sel
PC
Extim
m16
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ECE 232 L12.Datapath.29 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Meaning of the Control Signals (see slide 28)
° ExtOp: “zero”, “sign”
° ALUsrc: 0 => regB; 1 => immed
° ALUctr: “add”, “sub”, “or”
° MemWr: write memory
° MemtoReg: 1 => Mem
° RegDst: 0 => “rt”; 1 => “rd”
° RegWr: write dest register
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
3216imm16
ALUSrcExtOp
Mu
x
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWr
AL
U
Equal
0
1
0
1
01
=
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ECE 232 L12.Datapath.30 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Control Signals
inst Register Transfer
ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4
ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”
SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__
ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__
LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__
STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__
BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4
ALUsrc = ___, Extop = __, ALUctr = ___, RegDst = ___, RegWr(?), MemtoReg(?), MemWr(?), nPC_sel =__
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ECE 232 L12.Datapath.32 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Step 5: Logic for each control signal
° nPC_sel <= if (OP == BEQ) then EQUAL else 0
° ALUsrc <= if (OP == “000000”) then “regB” else “immed”
° ALUctr <= if (OP == “000000”) then functelseif (OP == ORi) then “OR”elseif (OP == BEQ) then “sub” else “add”
° ExtOp <= _____________
° MemWr <= _____________
° MemtoReg <= _____________
° RegWr: <=_____________
° RegDst: <= _____________
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ECE 232 L12.Datapath.34 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Example: Load Instruction
32
ALUctr
Clk
busW
RegWr
32
32
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
3216imm16
ALUSrcExtOp
Mu
x
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWrA
LU
Equal
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRtRs
=
imm
16
Ad
der
Ad
der
PC
Clk
00Mu
x
4
nPC_sel
PC
Ext
Adr
InstMemory
sign ext
addrt+4
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ECE 232 L12.Datapath.35 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
An Abstract View of the Implementation
° Logical vs. Physical Structure
DataOut
Clk
5
Rw Ra Rb
32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress
IdealData
Memory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232
A
B
Nex
t A
dd
ress
Control
Datapath
Control Signals Conditions
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ECE 232 L12.Datapath.36 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
A Real MIPS Datapath (CNS T0)
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ECE 232 L12.Datapath.37 Adapted from Patterson 97 ©UCB Copyright 1998 Morgan Kaufmann Publishers
Summary
° 5 steps to design a processor• 1. Analyze instruction set => datapath requirements
• 2. Select set of datapath components & establish clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
• 5. Assemble the control logic
° MIPS makes it easier• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates
° Single cycle datapath => CPI=1, CCT => long
° Next time: implementing control