Lecture 1 2013 - KTH · 1 14-Jan 13-15 Ka439 Introduction. MOSFETs,Technology roadmap. Overview of...

IH2655 Design and Characterisation of Nano- and Microdevices

Lecture 1Introduction and technology roadmap

IH2655 Design and Characterisation of Nano- and Microdevices

• Introduction to IH2655• Brief historic overview

• Moore’s Law and the ITRS Roadmap

• MOS Transistor (re-cap)

• From Geometrical to Material-based scaling

• CMOS Process Flow

IH2655 SPRING 2013

Course PM

Subject: Advanced course of the physical and technological concepts used in modern CMOS and bipolar/BiCMOS fabrication.

Prerequisites: Semiconductor Devices (IH1611) or Semiconductor Theory and Device Physics (IH2651) or equivalent knowledge in semiconductor device physics.

Course content: 26 h lectures week 3-10 (see Daisy schedule). Approximately 8 h laboratory exercises (2 labs), to be scheduled in groups of 4-5.

Language: English

IH2655 SPRING 2013

Course PM cont’dLecturer and Course Director: Prof. Mikael Östling, Department of Integrated Devices

& Circuits (EKT), School of ICT, KTH. E-mail: [email protected], phone: 08-790 4301

Lectures will also be given by: Dr Christoph Henkel 08-790 4177, [email protected] Assoc. prof Gunnar Malm, [email protected], 08-790 4332, same department

Laboratory asisstants are Mr Eugenio Dentoni Litta, [email protected], and Mr Sam Vaziri, [email protected], same department.

Literature: Plummer, Deal and Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling. Prentice-Hall 2000, ISBN 0-13-085037-3. (725 kr THS Bookstore in Kista)

Examples from other VLSI books and journal articles

Strong Suggestion: Read chapters before class – Concept Tests will help you much more

Examination: Two written lab reports on time and 1 h Oral examination.Signup sheets for labs and exam through Daisy.

https://www.kth.se/social/course/IH2655/

NOTE: LAB REPORTS ARE DUE ONE WEEK AFTER THE LAB!

IF YOUR LAB REPORT IS LATE YOUR MAXIMUM GRADE IS E

Individual laboratory reports are required and please observe that any

signs of plagiarism will directly be reported to the Disciplinary board

Course PM cont’d

IH2655 SPRING 2013

Mikael Östling KTH

Schedule# Date Time Room Subject1 14-Jan 13-15 Ka439 Introduction. MOSFETs,Technology roadmap.

Overview of fabrication flow (M Östling)

2 15-Jan 10-12 Ka439 Wafer fabrication and silicon epitaxy(M Östling)

3 21-Jan 13-15 Ka439 Wafer clean and wet processing, (C Henkel)4 22-Jan 10-12 Ka439 Electrical characterization. (G Malm)5 28-Jan 13-15 Ka439 Thermal oxidation of silicon (C Henkel)6 29-Jan 10-12 Ka439 Annealing (FA & RTA)

Diffusion and ion implantation, (C Henkel)7 4-Feb 13-15 Ka439 Dry etching (M Östling)8 5-Feb 10-12 Ka439 Deposition of dielectrics and polysilicon

(C Henkel)9 11-Feb 13-15 Ka439 Microlithography (M Östling)10 12-Feb 10-12 Ka439 Metallization and contacts (M Östling)11 18-Feb 13-15 Ka439 Back-end processing (M. Östling)12 19-Feb 10-12 Ka439 Process integration: MOS and Bipolar13 25-Feb 13-15 Ka439 Sustainable fabrication (G Malm)14 26-Mar 10-12 Ka439 Nanostructures / nanophysics (M Östling)15 4-Mar 10-12 Ka439 Reserve time

IH2655 SPRING 2013

Microelectronic processingClean room environment Wafer level

Chip levelTransistor level

Source: InfineonSource: Infineon

SiO2source

gate

drain

…so why should you care if you plan to work in Nanoscience, MEMS, PV or Photonics?

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Top down AND Bottom Up

Source: website Univ. Wien

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IH2655: Lego for grown-ups

Baba, Nature Photonics 3, 190 - 192 (2009)

KTH

KTH

wafer

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IH2655 AimThis course is about the process technology used to manufacture

semiconductor devices. It aims to familiarize with the related technical vocabulary and to provide the students with a tool kit of fabrication

methods for a range of devices.

After the course the student should be able to

describe the technological processes involved in the fabrication of nano- and microelectronic devices and circuits

compare alternative fabrication methodsapply the knowledge to specific device requirements through careful

selection among a number of choicesassess pros and cons of different fabrication methods combine fabrication methods to develop complex process flows for functional

devices and circuits in a range of applications (e.g. transistors, solar cells, optoelectronics...)

IH2655 SPRING 2013

• Introduction to IH2655

• Brief historic overview• Moore’s Law and the ITRS Roadmap




IH2655 SPRING 2013

Brief retrospect：A great invention based on Sciences

Bardeen, Brattain, Shockley, First Ge-based bipolar transistor invented 1947, Bell Labs. Nobel prize 1956Atalla, First Si-based MOSFET invented 1958, Bell Labs.Kilby (TI) & Noyce (Fairchild), Invention of integrated circuits 1959, Nobel prizePlanar technology, Jean Hoerni, Fairchild, 1960First CMOS invented early 1960’s“Moore’s law” coined 1965, FairchildDennard, scaling rule presented 1974, IBMFirst Si technology roadmap published 1994, USA

W. Shockley

J. Bardeen

W. Brattain

1st point contact transistor -- by Bell Lab

Polycrystalline Ge1956 Nobel Physics Prize

Transistor=transfer + resistor--Transferring electrical signal across a resistor

Bardeen, Brattain, Shockley, First Ge-based bipolar transistor invented 1947, Bell Labs. Nobel prize 1956

Kilby (TI) & Noyce (Fairchild), Invention of integrated circuits 1959, Nobel prize

This marked the start of an amazing development -> Increasing integration of components

Kilby (TI) & Noyce (Fairchild), Invention of integrated circuits 1959, Nobel prize

Planar process

Invented by Jean Hoerni at Fairchild Semiconductor (late 50's)

Planar technology, Jean Hoerni, Fairchild, 1960

NMOS technology

Dennard, scaling rule presented 1974, IBM

First Si technology roadmap published 1994, USAStarted by Semiconductor Industry Association (SIA) in USA1994: creation of an American style roadmap

The National Technology Roadmap for Semiconductors (NTRS)

1998, the SIA became closer to its European, Japanese, Korean and Taiwanese counterparts by creating the first global roadmap

The International Technology Roadmap for Semiconductors (ITRS).

Today: Over 1000 companies and research institutions

First Si technology roadmap published 1994, USA

•System Drivers•Design•Test & Test Equipment•Process Integration, Devices, & Structures•RF and A/MS Technologies for Wireless Communications•Emerging Research Devices•Emerging Research Materials•Front End Processes

•Lithography•Interconnect•Factory Integration•Assembly & Packaging•Environment, Safety, & Health•Yield Enhancement•Metrology•Modeling & Simulation

Started by Semiconductor Industry Association (SIA) in USA1994: creation of an American style roadmap




Today: Over 1000 companies and research institutionsTeams for:


• Brief historic overview

• Moore’s Law and the ITRS Roadmap• From Geometrical to Material-based scaling


Gordon Moore’s originalIdeas in 1965

Source; Intel

“Moore’s law”: coined 1965, Fairchild

1965: Components per „integrated function“

Source: G.E. Moore, Cramming more components onto integrated circuits, Electronics, Volume 38, Number 8, April 19, 1965

“Moore’s law”: coined 1965, Fairchild

1975: Transistors per chip. Basis: Exponential behavior…

Source: G.E. Moore, No exponential is forever…, ISSCC, February 2003

“Moore’s law”: rewritten in 1975, INtel

... Driven by $$$...

“Moore’s law”: the real motivation


“Moore’s law”: enabled by scaling


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386 Pentium 4400410 µm 1 µm 0.1 µm

Human hair Red blood cell Bacteria Virus MOSFET


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MOSFET metrics provide additional advantage

A simple model for IDon is given by the MOSFET “Square-Law” Equation:

IDon = (W/L) (µox/tox) (VGS - VT)2


Chips are faster if the gate length L is reduced

IH2655 SPRING 2013

IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 4, NO. 2, MARCH 2005 , p153

Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications

Robert Chau et al


Transistors are found in processors, memories etc.Number of transistors grows exponentially, approaching 1,000,000,000!Continuous down-scaling of transistor dimensions

Source: Intel

“Moore’s law”: still going strong in 2010

Costs are rising exponentially, too!!!

“Moore’s law”: However! (or: The notorious „e“)


…limited by power dissipation.???

“Moore’s law”: …and its consequences


Yes, if P.continues exponentially !Quelle: Intel

“Moore’s law”: …and its consequences


“Moore’s law”: …not


ITRS Roadmap – Moore’s Heirs

•System Drivers•Design•Test & Test Equipment•Process Integration, Devices, & Structures•RF and A/MS Technologies for Wireless Communications•Emerging Research Devices•Emerging Research Materials•Front End Processes

•Lithography•Interconnect•Factory Integration•Assembly & Packaging•Environment, Safety, & Health•Yield Enhancement•Metrology•Modeling & Simulation

Started by Semiconductor Industry Association (SIA) in USA1994: creation of an American style roadmap




Today: Over 1000 companies and research institutionsTeams for:

ITRS Roadmap





• From Geometrical to Material-based scaling• CMOS Process Flow

IH2655 SPRING 2013

Mikael Östling KTH

Long-channel MOSFETs

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Mikael Östling KTH

MOSFET I-V characteristicsLinear region (small values of Vds):

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Mikael Östling KTH

MOSFET I-V characteristics

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Mikael Östling KTH

MOSFET I-V characteristicsSaturation region (Vds larger than Vdsat):

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Mikael Östling KTH

MOSFET I-V characteristics

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Mikael Östling KTH

Subthreshold characteristics

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Mikael Östling KTH

Channel mobility

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Mikael Östling KTH

Short-channel effect (SCE)

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Mikael Östling KTH

Constant-field scaling

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Mikael Östling KTH

Rules for constant-field scaling

NOTE:Cox is F/cm2

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Mikael Östling KTH

Rules for constant-field scaling

Chapter 3

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Mikael Östling KTH

Generalized scaling

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Mikael Östling KTH

Rules for generalized scaling

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Nonscaling effects

Thermal voltage does not scale => subthreshold nonscaling

Bandgap does not scale => depletion layer does not scale

Voltage level not scaled (E increases) => mobility decreases

Higher electric field=> higher power and lower reliability

Source/Drain doping can not be scaled=> higher resistance





• From Geometrical to Material-based scaling• CMOS Process Flow

MOSFET metrics provide additional leverage: Materials



“Moore’s law”: scaling parameters

Gate lengthGate width

geometric

Geometric scaling is determined by improvements in process technology

Geometric Scaling: Isolation modules 1/2

LOCOS(semirecessed)

Recessed oxidation (ROX) (fully recessed)

Pros: Improved geometric scalabilityHigher device density

Con: Increased process complexity

Bird’s head and beak in LOCOS and ROX exhibit 0.6 –0.4 m encroachment

Further process technology improvements

Shallow Trench Isolation (STI)

• High-density plasma fills etched and liner-oxidixed trenches with SiO2

Deep-trench isolation

• Trench isolation can be combined with silicon-on-insulator (SOI) wafers for nearly complete device isolation

Geometric Scaling: Isolation modules 2/2

Thermally grown, high quality liner oxide

Deposited, low quality filler oxide

Chemical Mechanical polishing planarization

Hard mask layers


„Happy Scaling“Gilbert DeclerckVLSI Symp. 2005

Industry guy

Researcher

Materialsbasedscaling

•SOI•High-k•Metal Gates•Strained Silicon•Germanium•Carbon Nanotubes•Graphene(!)

“Moore’s law”: still going strong in 2010 – Why?

MOSFET metrics provide additional leverage: Materials



“Moore’s law”: old & new scaling parameters

MobilityDielectric constant Oxide thickness

Gate lengthGate width

“old”geometric “new”

material

All scaling parameters are determined by improvements in process technology

“Moore’s law”: still going strong in 2010 – Why?

Source: fabtech.org / Sigma Aldrich

Today: New materials in connection with improvements in process technology

IH2655 SPRING 2013

Strained silicon & SiGeA transistor built with strained silicon. The silicon is “stretched out” because of the natural tendency for atoms inside compounds to align with one another. When is silicon is deposited on top of a substrate with atoms spaced farther apart, the atoms in silicon stretch to line up with the atoms beneath, stretching – “straining” – the silicon. In the strained silicon, electrons experience less resistance and flow up to 70 percent faster, which can lead to chips that are up to 35 percent faster – without having to shrink them. Image Reproduced with Permission of IBM Almaden Research Center, IBM.

Intel 45nm dual-core processor die

http://www.intel.com/pressroom/kits/45nm/photos.htm

Processors on an Intel 45nm Hafnium-based High-k Metal Gate ''Penryn'' Wafer photographed with an original Intel Pentium processor die. Using an entirely new transistor formula, the new processorsincorporate 410 million transistors for each dual core chip, and 820 million for each quad core chip. The original Intel Pentium Processor only has 3.1 million transistors.

CMOS structures

• Substrate selection: moderately high resistivity, (100) orientation, P type.• Wafer cleaning• Thermal oxidation (≈ 40 nm)• Silicon Nitride LPCVD deposition (≈ 80 nm)• Photoresist spinning and baking (≈ 0.5 - 1.0 μm)

CMOS Process Flow

• Mask #1 patterns the active areas• Silicon Nitride is dry etched• Photoresist is stripped

CMOS Process Flow

• Field oxide is grown using a LOCOS/ROX process• Typically 90 min @ 1000 °C in H2O grows ≈ 0.5 μm

CMOS Process Flow

• Mask #2 blocks a B+ implant to form the wells for the NMOS devices • Typically 1013 cm-2 @ 150-200 KeV

CMOS Process Flow

• Mask #3 blocks a P+ implant to form the wells for the PMOS devices• Typically 1013 cm-2 @ 300+ KeV

CMOS Process Flow

• ”Annealing”• A high temperature drive-in produces the “final” well depths and

repairs implant damage• Typically 4-6 hours @ 1000 °C - 1100 °C

CMOS Process Flow

• Mask #4 is used to mask the PMOS devices• An Implant is done on the NMOS devices• Typically a 1-5 x 1012 cm-2 B+ implant @ 50 - 75 KeV

CMOS Process Flow

• Mask #4 is used to mask the PMOS devices• A VTH adjust implant is done on the NMOS devices• Typically a 1-5 x 1012 cm-2 B+ implant @ 50 - 75 KeV

CMOS Process Flow

• Mask #5 is used to mask the NMOS devices• A VTH adjust implant is done on the PMOS devices,• Typically 1-5 x 1012 cm-2 As+ implant @ 75 - 100 KeV.

CMOS Process Flow

• The thin oxide over the active regions is stripped• A high quality gate oxide grown• Typically 3 - 5 nm, which could be grown in 0.5 - 1 hrs @ 800 °C in O2• Note: Today this could be entirely different for high end technology (high-k)

CMOS Process Flow

• Polysilicon is deposited by LPCVD ( ≈ 0.5 μm)• An unmasked P+ or As+ implant dopes the poly (typically 5 x 1015 cm-2)• Note: Today this could be a metal gate

CMOS Process Flow

• Mask #6 is used to protect the MOS gates• The poly is plasma etched using an anisotropic etch

CMOS Process Flow

• Mask #7 protects the PMOS devices• A P+ implant forms the LDD regions in the NMOS devices• Typically 5 x 1013 cm-2 @ 50 KeV

CMOS Process Flow

• Mask #8 protects the NMOS devices• A B+ implant forms the LDD regions in the PMOS devices• Typically 5 x 1013 cm-2 @ 50 KeV

CMOS Process Flow

• Conformal layer of SiO2 is deposited (typically 0.5 μm)

CMOS Process Flow

• Anisotropic etching leaves “sidewall spacers” along the edges of the poly gates

CMOS Process Flow

• Mask #9 protects the PMOS devices• An As+ implant forms the NMOS source and drain regions • Typically 2-4 x 1015 cm-2 @ 75 KeV

CMOS Process Flow

• Intermetal dielectric and second level metal are deposited and defined in the same way as level #1.

• Mask #14 is used to define contact vias and Mask #15 is used to define metal 2

• A final passivation layer of Si3N4 is deposited by PECVD and patterned with Mask #16

• This completes the CMOS structure

CMOS Process Flow

Final result of the process flow: One NMOS and one PMOS device, BUT...They were made in parrallel and we can make 1 Billion other at the same time

CMOS Process Flow

Lecture 1 2013 - KTH · 1 14-Jan 13-15 Ka439 Introduction. MOSFETs,Technology roadmap. Overview of...

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