1

Short Channel MOS Transistor

Kaushik Roy

Purdue UniversityDept. of ECE

kaushik@purdue.edu

2

Topics• Long channel MOSFET: review

– Strong inversion (linear, saturation mode)

• Short channel MOSFET– Velocity saturation– Vt roll-off– Drain induced barrier lowering– Series resistance– Narrow width effect– Weak inversion (Vt, S-swing)

2

3

Transistor

DrainSource

Gate

Kuroda, IEDM panelBody

4

Compact Modeling• We already know how to run SPICE. Why

do we need to learn about models?– SPICE can accurately model the device

using many parameters (30-100)– SPICE is nothing other than a matrix solver

(KCL, KVL, linearized I-V equations)• We need a reasonable compact model

– To reason about circuit parameters (functionality, delay, power, robustness, …)

– For hand/computer (e.g. Matlab) optimization– To check the SPICE simulation

3

5

Basic Operation (1)

• Device is in cut-off region• Simply, two back-to-back reverse biased pn diodes.

6

Basic Operation (2)

• With a positive gate bias, electrons are pulled toward the positive gate electrode

• Given a large enough bias, the electrons start to “invert”the surface (pn type), a conductive channel forms

• Threshold voltage Vt

4

7

Basic Operation (3)

• Current flows from drain to source with a positive drain voltage

• What is current in terms of Vgs, Vds, Vbs?

8

Assumptions

• Current is controlled by mobile charge in the channel• Gradual channel: variation of E-field mainly perpendicular

to the channel• v= eE (not true in short channel devices) • Gen. & recomb. current is negligible: same Ids across

channel

5

9

MOS Current

• From EE559, Qn= Cox(Vgs-Vt-V(y))• By Ohm’s law, Ids= Qn • v • W

= Cox(Vgs-Vt-V(y)) • eE • W= Cox(Vgs-Vt-V(y)) • e • (dV(y)/dy) • W

Ids • dy= Cox(Vgs-Vt-V(y)) • e • W • dV(y)

10

MOS Current

• Integrate this over the channelIds • dy= Cox(Vgs-Vt-V(y)) • e • W • dV(y)Ids • L= eCoxW ((Vgs-Vt) Vds-0.5Vds

2)

Ids = eCoxW/L ((Vgs-Vt) Vds-0.5Vds2) : linear mode

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11

MOS Current

• Qn= Cox(Vgs-Vt-V(y)) what if V(y) > Vgs-Vt

• Pinch-off: channel near drain disappears– Electrons which move along the channel to the pinch-off region are

sucked across by the field, and enter the drain– Current through the channel is fixed

Ids = eCoxW/(2L) (Vgs-Vt)2 : saturation mode

12

Bulk Charge Model

( )( )

tcoefficieneffectbodyC

Cm

m

VVV

m

VV

LW

CI

VmVVVL

WCI

ox

dep

tgsdsat

tgsoxed

dsdstgsoxed

−+=

−=

−=

−−=

:1

,2

21

2

2

µ

µ

• More accurate than the square law model• Considers inversion charge and bulk depletion charge• Due to body effect across the channel

7

13

Channel Length Modulation

dso VLL ζ−=

• Pinch-off depletion layer width increases as the drain voltage increases

• Extreme case of this is punch-through

)1( dsdsatdso

odsatds VI

VLL

II λζ

+×=−

×=

14

Simulation versus Model (NMOS)

• The square-law model doesn’t match well with simulations• Only fits for low Vgs, low Vds (low E-field) conditions

8

15

Simulation versus Model (PMOS)

• Not as bad as the NMOS device• Still large discrepancies at high E-field conditions

16

Simulation versus Model (Ids vs. Vgs)

• Saturation current does not increase quadratically• The simulated curves looks like a straight line• Main reason for discrepancy: velocity saturation

9

17

Velocity Saturation

• E-fields have gone up as dimensions scale• Unfortunately, carrier velocity in silicon is limited• Electron velocity saturates at a lower E-field than holes• Mobility ( e=v/E) degrades at higher E-fields• Simple piecewise linear model can be used

18

Velocity Saturation

csat

cnn

c

e

EEforv

EEfor

EE

Ev

>=

<

+

= 1

1

µ

e

satc

vE

µ2=

[Toh, Ko, Meyer, JSSC, 8/1988]

• Modeled through a variable mobility• n=1 for PMOS, n=2 for NMOS• To get an analytical expression, let’s assume n=1

must be determined for a given Vgs

for larger Vgs (almost linear)↑↓ ce

ce

E

E

,

,

µµ

10

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Velocity Saturation

LEV

VmVVV

LW

CI

dVEW

IymVVVWCdyI

W

Edy

dVdy

dVymVVVC

WE

EE

ymVVVCI

c

ds

dsdstgsoxeds

ce

dstgseoxds

c

e

tgsox

c

etgsoxds

+×

−−=∴

−−−=

×

+

×−−=

×+

×−−=

1

12

)(

))((

1

))((

1))((

2

µ

µµ

µ

µ

• Plug it into the original current equation

20

Velocity Saturation Point

0=ds

dsdV

dI

1)/()(21

1)/()(21)(

)/()(211

/)(2

+−+

−−+−=

−++−

=

LmvVV

LmvVVVVWvCI

LmvVV

mVVV

sattgse

sattgsetgssatoxdsat

sattgse

tgsdsat

µµ

µ

m

VV

LW

CI

m

VVV

L

tgsoxedsat

tgsdsat

2

)( 2−=

−=

∞→

µ)(

)/()(2

0

tgssatoxdsat

etgssatdsat

VVWvCI

mVVLvV

L

−=

−=

→

µ

Long channel device Short channel device

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21

Simulation versus Model

• Model incorporating velocity saturation matches fairly well with simulation

22

Alpha Power Law

αµ )(2 tgsoxeds VVC

LW

I −=

• Simple empirical model for short channel MOS

• Parameter is between 1 and 2• =1-1.2 for short channel

devices• Parameters and Vt are fitted

to measured data for minimum square error fitted Vt can be different from physical Vt

[Sakurai and Newton, JSSC 1990]

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23

Improving Short Channel MOS Model• MOS current model

= square law device (long channel)+ body effect across channel (bulk charge model, long

channel)+ channel length modulation (long channel)+ velocity saturation (short channel)

• Vt model= standard expression (long channel)+ body effect (body bias, long channel)+ Vt roll-off (barrier lowering, short channel)+ Drain induced barrier lowering (short channel)+ ...

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Remember the Standard Vt Equation?

ox

BsiaBfbt C

qNVV

φεφ

222 ++=

• Detailed derivation given in Taur’s book• Basically, three terms

– Flat band voltage– 2 B: the magic number for on-set of inversion– Oxide voltage

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25

Body Effect (Back Bias)

ox

sbBsiaBfbt

sbox

sbBsiasbBfbt

ox

BsiaBfbt

C

VqNVV

VC

VqNVVV

C

qNVV

+++=

−+

+++=

++=

φεφ

φεφ

φεφ

222

222

2220

• Body effect degrades transistor stack performance• However, we need a reasonable body effect for post silicon

tuning techniques• Reverse body biasing, forward body biasing

Drain

Gate

Source

Body

+-Vsb

Vsb > 0 : RBBVsb < 0 : FBB

26

Body Effect (Back Bias)

• Vt can be adjusted by applying FBB or RBB– Essential for low power and high performance – Will talk about body biasing extensively later on

14

27

0

1

2

3

4

5

6

0.925 1 1.075 1.15 1.225Normalized frequency

No

rmal

ized

leak

age

0%20%40%60%80%

100%D

ie c

ount

NBB

ABB

Accepted dies:

0%

110C1.1V

Body Biasing for Process Compensation

NBB

ABB

Body bias: controllability

to Vt

28

Substrate Sensitivity

Cox

Cdep

VG

p-type Si

n+ poly-Si

n+ n+

depletion region

VG

CIRCUIT MODELDEVICE

VD

Wdep

ysensitivitsubstrateC

C

dVdV

ox

dep

Vsb

t

sb

:0

==

Some ppl call this the body coeff.ox

oxox

B

Sia

dep

Sidep

tC

qNW

C

εφ

εε

=

==4

Vsb Vsb

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Short Channel Effect: Vt roll-off

• Ability of gate & body to control channel charge diminishes as L decreases, resulting in Vt-roll-off and body effect reduction

n+ poly gate

p-type body

n+ source n+ drain

Short Channel

n+ source n+ drain

n+ poly gate

p-type body

Long Channel

depletion

Ec Ec

Charge sharingCharge sharing

Vt

Leff

3 L variation

• 3 Vt variation increases in short channel devices

Short Channel Effect: Vt roll-off

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31

n+ source n+ drain

n+ poly gate

p-type body

Long Channel

• Increase in VDS reduces Vt and increases Vt-roll-off: DIBL

n+ poly gate

p-type body

n+ source n+ drain

Short Channel

depletion

Short Channel Effect: Drain Induced Barrier Lowering (DIBL)

Ec Ec

Vds ↑↑↑↑ Vds ↑↑↑↑

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Vt

Leff

DIBL+Vt roll-off(Vds=Vdd)

Vt roll-off (Vds~0V)

Short Channel Effect: Drain Induced Barrier Lowering (DIBL)

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33

• DIBL coefficient

• DIBL increases leakage current• Dynamic Vdd can reduce leakage because of DIBL

Short Channel Effect: DIBL

Vgs (NMOS) Vgs (PMOS)

log(

I ds)

log(

I ds)

ds

td V

V∆∆=λ

Vds=0.1V

Vds=2.0V

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Short Channel Vt Equation

7.2

2 )9.2)(15.0)(012.0(2.2

−

−

+++=

mXmWmTmL

jsdoxd µµµµ

λ

L

X

XW j

jb

−+−= 1

211λ

[Poon, IEDM, 1973]

[Ng, TED, 1993]

ox

BsiaBfbt C

qNVV

φεφ

222 ++= (Long channel Vt equation)

dsdsbBsaox

bBfbt VVqN

CVV λφελφ −+++= )2(22

18

35

Improving Short Channel MOS Model• MOS current model

= square law device (long channel)+ body effect across channel (bulk charge model, long

channel)+ channel length modulation (long channel)+ velocity saturation (short channel)

• Vt model= standard expression (long channel)+ body effect (body bias, long channel)+ Vt roll-off (barrier lowering, short channel)+ Drain induced barrier lowering (short channel)+ ...

36

Transistor Scaling Challenges - Xj

0.4

0.5

0.6

0.7

0.8

0 50 100 150 200Junction Depth (nm)

I DN

(mA

/ µµ µµm

)

0.1

0.2

0.3

0.4

0.5

I DP

(mA

/ µµ µµm

)NMOS

PMOS

0

0.05

0.1

0.15

0.2

0 50 100 150 200Junction Depth (nm)

LM

ET

( µµ µµm

)

90

100

110

120

130R

EX

T( ΩΩ ΩΩ

µµ µµm

)

LMET

REXT

RC

RSE Rsalicide

SalicidePoly-Si Salicide

S. Asai et al., 1997.

S. Thompson et al., 1998.S. Thompson et al., 1998.

19

37

Effect of Series Resistance

38

Effect of Series Resistance(10nm Device)

20

39

Sub-Threshold Conduction

• NPN BJT is formed in sub-threshold region• Only difference with a real BJT is that the base voltage is

controlled through a capacitive divider, and not directly by a electrode

• Like in a BJT, current is exponential to Vbe

40

Sub-Threshold Current

( )( )

)1(12

kTqV

mkTVVq

Boxeffd

dstgs

eemqTk

CL

WI

−−

−−

= µ

21

41

Sub-Threshold Swing

• Smaller S-swing is better• Ideal case: m=1 (Cox>>Csub)

– Fundamental limit = 1 * 26mV * ln10 = 60 mV/dec @ RT

– Can only be achieve by device geometry (FD-SOI)• Typical case: m 1.3

– S = 1.3 * 26mV * ln10 80 mV/dec @ RT– At worst case temperature (T=110C), S 100 mV/dec

ox

dep

C

Cmdec

mVq

kTmS +== 1,)(10ln

42

Vdd and Vt Scaling

As Vt decreases, sub-threshold leakage increases Leakage is a barrier to voltage scaling

Performance vs Leakage:

VT ↓↓↓↓ IOFF ↑↑↑↑ ID(SAT) ↑↑↑↑

)()( 3 TGSSAToxeffD VVCWKSATI −∝ υ

22 )()( TGS

eff

effD VVK

L

WSATI −∝

qmkTV

eff

effOFF

T

eKL

WI /

1

−

∝

VGSVTL VTH

log(

I DS)

IOFFL

IOFFH

22

43

Vdd and Vt Scaling• Vt cannot be scaled indefinitely due to increasing leakage

power (constant sub-threshold swing)• Example

CMOS device with S=100mV/dec has Ids=10 A/ m @ Vt=500mVIoff=10 A/ m x 10-5 = 0.1 nA/ m

Now, consider we scale the Vt to 100mVIoff=10 A/ m x 10-1 = 1 A/ m

Suppose we have 1B transistors of width 1 mIsub=1 A/ m x 1B x 1 m = 100 A !!

44

S-Swing & Substrate Sensitivity

1

1,10ln

−==

+==

mC

C

dVdV

C

Cm

qkT

mS

ox

dep

Vsb

t

ox

dep

sb

ox

oxox

B

Sia

dep

Sidep

tC

qNW

C

εφ

εε

=

==4

Cox

Cdep

VG

p-type Si

n+ poly-Si

n+ n+

depletion region

VG

VD

Wdep

Vsb Vsb

( )( ) ↓ ↓ ↓↓↓

↑ ↑ ↑↑↑

sensitivtysubStorNm

sensitivtysubStorNm

oxa

oxa

.

.(good)

(good)

(bad)

(bad)

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45

Leakage Components

[Keshavarzi, Roy, and Hawkins, ITC 1997]

Gate

Source Drain

n+n+

Bulk

Reverse Bias Diode& BTBTGate Induced Drain

Leakage (GIDL)

Gate Oxide Tunneling

Punchthrough

Weak Inversion Current,Drain Induced Barrier Loweringand Narrow Width Effect

p-sub

46

Gate Oxide Tunneling Leakage

0 2 4 6 8 10 12

Gate Voltage (V)

10-7

103

100

1E-071E-061E-051E-041E-031E-02

1E+00

1E+021E+03

0 2 4 6 8 10 12

2.5nm

3.0nm

3.5nm 5.1nm7.6nm

C. Hu, 1996.

I GA

TE(A

/cm

2 )

IOFF

IGATE

N+ Gate

e-

P- SubstrateElectrical Tox = Physical Tox + 1nm

50% poly depletion, 50% quantum effectProblem in analog (diff pairs, current mirror), domino

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47

Gate Oxide Tunneling Leakage• Quantum mechanics tells us that there is a finite

probability for electrons to tunnel through oxide• Probability of tunneling is higher for very thin

oxides• NMOS gate leakage is much larger than PMOS• Gate leakage has the potential to become one of

the main showstoppers in device scaling

ox

tddox

EB

oxgate tVV

EeAEI ox−==

−,2

48

Band-to-Band Tunneling LeakageEC

EC

EV

EV

p(+)-side

n(+)-side

q(Vbi+Vapp)

S/D junction BTBT Leakage

• Reversed biased diode band-to-band tunneling– High junction doping: “Halo” profiles– Large electric field and small depletion width at the junctions

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49

Gate Induced Drain Leakage (GIDL)• Appears in high E-field region under gate/drain

overlap causing deep depletion• Occurs at low Vg and high Vd bias• Generates carriers into substrate from surface

traps, band-to-band tunneling• Localized along channel width between gate and

drain• Thinner oxide, higher Vdd, lightly-doped drain

enhance GIDL• High field between gate and drain increases

injection of carriers into substrate

50

Punch Through

• If the channel length becomes too short, the drain side depletion region can touch the source side

• Reduces the barrier for electron injection from source to drain

• Sub-surface version of weak inversion conduction

26

51

Narrow Width Effect

Vt

WChannel

Gate

Side view of MOS transistor

Extra depletion region

• Depletion region extends outside of gate controlled region• Opposite to Vt roll-off• Depends on isolation technology

width

52

Leakage Components

[IEEE press, 2000]

27

53

Temperature Dependence• Mobility degrades at higher temperatures

– Scattering increases with vibrating atoms– Temp change from 27C to 130C decreases current to 0.65. – The circuit will run 1.6 times slower.

• Vt decreases at higher temperatures– Electrons on the source side gain more energy– Sub-threshold leakage will increase– The circuit will run faster

• Question: What happens to circuit performance at high temperatures? Slower or Faster?

54

Positive Temperature Dependence

• Depending on Vdd and Vt, positive dependency can occur– Advantageous phenomenon for low Vdd design– Will change the design validation process for worst case

conditions

K. Kanda, JSSC 2001

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55

Summary IC designers should be aware of the technology

issues Short channel behaviors

Velocity saturation Vt roll-off Drain induced barrier lowering Series resistance Leakage: sub-threshold, gate, BTBT, punchthrough Positive temperature dependence Gate depletion, quantum confinement

The issues can be dealt with at different levels of abstraction (technology, circuits, CAD, architecture, software, etc)