Lec7 SAP-1

UST-ECE COMP305

engradc (c) 2009

SAP-1

Microcomputer

(Simple As Possible)

Architecture

UST-ECE COMP305

engradc (c) 2009

Program

Counter

Input and MAR

16 x 8 RAM

Instruction

Register

Controller/

Sequencer

Accumulator A

Adder/

Subtracter

B Register

Output

Register

Binary

Display

8

8

8 4

4

8

8

8

4

8

8

4

12

W bus 8

8

8

4 8

CP CLK CLR EP

LM

CLK

CE

LI CLK CLR EI

CLK CLK CLR CLR

LA CLK

EA

SU

EU

LB CLK

LO CLK

CPEPLMCE LIEILAEA SUEULBLO

UST-ECE COMP305

engradc (c) 2009

Program Counter

Part of control unit that counts from 0000

to 1111.

Its job is to send to the memory the

address of the next instruction to be

fetched and executed.

It is also known as instruction pointer. BACK

UST-ECE COMP305

engradc (c) 2009

Input and MAR

It includes address and data switch

registers.

Switch register allow you to send 4

address bits and 8 data bits to the RAM.

The memory address register (MAR) is

part of SAP-1 memory.

BACK

UST-ECE COMP305

engradc (c) 2009

RAM (Random Access Memory)

The RAM is 16 x 8 static TTL RAM.

It allows to store a program and data in the

memory before a computer run.

BACK

UST-ECE COMP305

engradc (c) 2009

Instruction Register

It is part of control unit.

The contents of the instruction register are

split into two nibbles. The upper nibble is a

two - state output that goes directly to the

block labeled controller/sequencer. The

lower nibble is a three-state output that is

read onto the W bus when needed.

BACK

UST-ECE COMP305

engradc (c) 2009

Controller-Sequencer

The 12 bits that come out of the controller-

sequencer form a word controlling the rest

of the computer. The 12 bits are called

control word/ control bus.

CON = CPEPLMCE LIEILAEA SUEULBLO

BACK

UST-ECE COMP305

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Accumulator (A)

It is a buffer register that stores

intermediate answers during a computer

run.

It has two outputs; the two-state output

goes to the adder/subtracter, the three-

state output goes to the W bus.

BACK

UST-ECE COMP305

engradc (c) 2009

Adder / Subtractor

When SU is low it will perform addition,

otherwise subtraction.

The adder/subtracter is asynchronous; its

contents can change as soon as the input

words change.

BACK

UST-ECE COMP305

engradc (c) 2009

B Register

It is another buffer register, used in

arithmetic operations.

The two-state output of the B register

drives the adder/subtracter, supplying the

number to be added or subtrahend from

the contents of the accumulator.

BACK

UST-ECE COMP305

engradc (c) 2009

Output Register

The output register is often called an

output port because processed data can

leave the computer through this register.

BACK

UST-ECE COMP305

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Binary Display

It is a row of 8 light emitting diodes, it

shows the contents of the output

register/port.

The result displayed is in the binary form.

BACK

UST-ECE COMP305

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SAP-1 INSTRUCTION SET

LDA (Load Accumulator)

LDA 8H

ADD (Add)

ADD 9H

SUB (Subtract)

SUB AH

OUT

HLT

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MEMORY REFERENCE

INSTRUCTIONS

LDA

ADD

SUB

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INSTRUCTION SET

SUMMARY Mnemonic Operations

LDA Load RAM data into accumulator

ADD Add RAM data to accumulator

SUB Subtract RAM data from accumulator

OUT Load accumulator data into output

register

HLT Stop processing

UST-ECE COMP305

engradc (c) 2009

SAP-1 Programming

Mnemonic Operation Code

(Op-code)

LDA 0000

ADD 0001

SUB 0010

OUT 1110

HLT 1111

UST-ECE COMP305

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Instruction = XXXX XXXX

Example: ADD 9H 0001 1001

Instruction field

Address field

SAP-1 Programming

UST-ECE COMP305

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LDA FH 0000 1111

ADD EH 0001 1110

HLT 1111 XXXX

Assembly Language Machine Language

Source Program Object Program

SAP-1 Programming

UST-ECE COMP305

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SAP-1 INSTRUCTION CYCLE

Fetch Cycle

Address State

Increment State

Memory State

Execution Cycle

UST-ECE COMP305

engradc (c) 2009

Clk

t1 t2 t3 t4 t5 t6 t7

t1

t2

t3

t4

t5

t6

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Address State (t1)

PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B

REG

OUTPUT

REG

DISPLAY


UST-ECE COMP305

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Increment State (t2)

PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B

REG

OUTPUT

REG

DISPLAY


UST-ECE COMP305

engradc (c) 2009

Memory State (t3) PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B

REG

OUT

REG

DISPLAY


UST-ECE COMP305

engradc (c) 2009

LDA (t4) PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B

REG

OUT

REG

DISPLAY


UST-ECE COMP305

engradc (c) 2009

LDA (t5) PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B

REG

OUT

REG

DISPLAY


UST-ECE COMP305

engradc (c) 2009

LDA (t6) PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B REG

OUT REG

DISPLAY


UST-ECE COMP305

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ADD/SUB (t4) PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B

REG

OUT

REG

DISPLAY


UST-ECE COMP305

engradc (c) 2009

ADD/SUB (t5) PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B

REG

OUT

REG

DISPLAY


UST-ECE COMP305

engradc (c) 2009

ADD/SUB (t6) PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B

REG

OUT

REG

DISPLAY


UST-ECE COMP305

engradc (c) 2009

OUT (t4) PC

MAR

RAM

IR

CON

ACC

ADDER

SUBTRACTER

B

REG

OUT

REG

DISPLAY


UST-ECE COMP305

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SAP-1 FETCH Micro-operation

STATE CON ACTIVE BITS

t1 5E3H EP, LM

t2 BE3H CP

t3 263H CE, LI

BACK

UST-ECE COMP305

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SAP-1 EXECUTE Micro-operation

MACRO State CON ACTIVE

LDA t4 1A3H LM, EI

t5 2C3H CE, LA

t6 3E3H NONE

ADD t4 1A3H LM,EI

t5 2E1H CE, LB

t6 3C7H LA,EU

SUB t4 1A3H LM,EI

t5 2E1H CE,LB

t6 3CFH LA, SU,EU

OUT t4 3F2H EA,LO

t5 3E3H NONE

t6 3E3H NONE

UST-ECE COMP305

engradc (c) 2009

Machine Cycle

Number of clock cycles needed to

complete one fetch and execute cycle.

Eg. In SAP-1 the six T-states is the

machine cycle

UST-ECE COMP305

engradc (c) 2009

Instruction Cycle

Number of clock cycles needed to finish

the fetch and execute cycle of an

instruction

Instruction cycle > Machine cycle

Eg. In SAP-1, the

machine cycle = instruction cycle

UST-ECE COMP305

engradc (c) 2009

Problems

Write an assembly-language program that

performs this operation:

8 + 4 -3 + 5 2

(Use addresses BH to FH for the data)

Convert the program and data in the

previous program into machine language.

Express the result in both binary and

hexadecimal form.

Lec7 SAP-1

Documents

Transcript of Lec7 SAP-1