Lab Mano Final

DIGITAL ELECTRONICS LAB MANUAL ECE / CIET

CIRCUIT DIAGRAM

TRUTH TABLE:

K MAP SIMPLIFICATION

0 1

0 0 1

1 1 0

Sum= xy’+x’y Carry= xy

1

Input Outputx y Carry Sum0 0 0 00 1 0 11 0 0 11 1 1 0

0 1

0 0 0

1 0 1


Ex. No 1a DESIGN AND IMPLEMENTATION OF HALF ADDER USING LOGIC GATES

AIM To Design and implementation the Half Adder using logic gates.

APPARATUS REQUIRED

S. No Apparatus Range Qty

1. IC 7408, IC 7486, - Each 1

2. Resister 330 Ω 1

3. LED - 1

4. Bread Board - 1

5. Connecting wires - As required

THEORY :

A Combinational circuit which performs addition of two bits is called a

half adder. It consists of two bit inputs (x and y) and two outputs (Sum and

Carry). Sum is LSB Bit and Carry is MSB bit. The truth table gives the relation

between input and output variable for half adder operation.

PROCEDURE

1. Check all the given components working properly.

2. Connect the circuit as per the circuit diagram.

3. Give all possible logical inputs as per the truth table.

4. Observe the logical output and verify with your truth table.

RESULT:

Thus the Half adder was designed and implemented using logic gates.

2


CIRCUIT DIAGRAM

TRUTH TABLE:


0 1

0 0 1

1 1 0

diff= xy’+x’y barow= xy’

3

Input Outputx y barrow diff0 0 0 00 1 0 11 0 1 11 1 0 0

0 1

0 0 0

1 1 0


Ex. No 1b DESIGN AND IMPLEMENTATION OF HALF SUBTRACTOR USING LOGIC GATES

AIM To Design and implement Half Subractor using logic gates.

APPARATUS REQUIRED


1. IC 7408, IC 7404,IC 7486

- Each 1


3. LED - 1

4. Bread Board - 1


THEORY :

A Half Subtractor is a Combinational circuit that subtracts two bits and

produces their difference. It also has an output to specify if a 1 has been

borrowed. Let us designate minuned bit as A and the subtrahend bit as B. The

result of operation A-B for all possible values of A and B is given in the truth

table.

PROCEDURE





RESULT:

Thus the Half Subractor was designed and implemented using logic gates.

4


CIRCUIT DIAGRAM

TRUTH TABLE:

Inputs Outputsx y z Carry Sum0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1


00 01 11 10

0 0 1 0 1

1 1 0 1 0

Sum= x xor y xor z Carry= xy+xz+yz

=((x xor y )and z )or(x and y)

5

00 01 11 10

0 0 0 1 0

1 0 1 1 1


Ex. No 1c DESIGN AND IMPLEMENTATION OF FULL ADDER USING LOGIC GATES

AIM To Design and implementation the Full Adder using logic gates.

APPARATUS REQUIRED


1. IC 7408, IC 7486,IC7432

- Each 1


3. LED - 1

4. Bread Board - 1


FULL ADDER :

A Full Adder is a combinational logic circuit that performs the arithmetic

sum of three binary input bits. It consists of three inputs (x, y & z) Two of the input

variable denoted by x & y represent the two significant bits to be added. The third

input z represents the carry from the previous lower significant position. It

consists of two outputs they are Sum and Carry. Sum is LSB Bit and Carry is

MSB bit. The truth table gives the relation between inputs and output variables for

full adder operation

PROCEDURE





RESULT:

Thus the Full adder was designed and implemented using logic gates.

6


CIRCUIT DIAGRAM

TRUTH TABLE:

Input OutputA B Bin Borrow Difference0 0 0 0 00 0 1 1 10 1 0 1 10 1 1 1 01 0 0 0 11 0 1 0 01 1 0 0 01 1 1 1 1


00 01 11 10

0 0 1 0 1

1 1 0 1 0

Sum= x xor y xor z Carry= x’y+x’z+yz

=((x xor y )’ and z )or(x’ and y)

7

00 01 11 10

0 0 1 1 1

1 0 0 1 0


Ex. No 1d DESIGN AND IMPLEMENTATION OF FULL SUBRACTOR USING LOGIC GATES

AIM To Design and implementation the Full subractor using logic gates.

APPARATUS REQUIRED


1. IC 7408, IC 7486,IC 7404, IC7432

- Each 1


3. LED - 1

4. Bread Board - 1


FULL SUBTRACTOR :

A full subtractoris a combinational circuit that performs a

subtraction between two bits, taking into account borrow of the lower significant

stage. This circuit has three input and two outputs. The three input are A,B, cin

denote the minuend,subtrahend and previous borrow repectively .The two

outputs D and Bout represent the difference and output borrow respectively

PROCEDURE





RESULT:

Thus the Full Subractor was designed and implemented using logic gates.

8


CIRCUIT DIAGRAM

TRUTH TABLE:

BCD CODE EXCESS 3 CODE

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

9


Ex. No 2 a DESIGN AND IMPLEMENTATION OF BCD TO EXCESS 3 USING LOGIC GATES

AIM To Design and implement BCD to Excess 3 code converter using logic

gates.

APPARATUS REQUIRED


1. IC 7408, IC 7404, IC7432

- Each 1


3. LED - 4

4. Bread Board - 1


THEORY

The availability of a large variety of codes for the same discrete elements

of information results in the use of different codes by different digital systems. It is

sometimes necessary to use the output of one system as the input to another. A

conversion circuit must be inserted between the two systems compatible even

though each uses a different binary code. Digital systems can be designed to

process data in discrete form only

Excess 3 Code is a modified form of a BCD number. The Excess 3 code

can be derived from the natural BCD code by adding 3 to each coded number.

For example Decimal 12 can be represented in BCD as 0001 0010 . Now adding

3 to each digit we get excess 3 Code 01000101. With this information truth table

for BCD to Excess 3 code converter can be determined.

10



00 01 11 10

00 1 1

01 1 1

11 X X X X

10 1 X X

E0=B0’ E1=B0B1+ B0’B1’

00 01 11 10

00 1 1 1

01 1

11 X X X X

10 1 X X

E2=B2’B1+B2’B0+B2B1’B0’ E3=B3+B2B1+B2B0

11

00 01 11 10

00 1 1

01 1 1

11 X X X X

10 1 X X

00 01 11 10

00

01 1 1 1

11 X X X X

10 1 1 X X


PROCEDURE





RESULT:

Thus the BCD to Excess 3 was designed and implemented using logic gates.

.

12


CIRCUIT DIAGRAM

13


Ex. No 2 b DESIGN AND IMPLEMENTATION OF EXCESS 3TO BCD USING LOGIC GATES

AIM To Design and implement Excess 3 to BCD code converter using logic

gates.

APPARATUS REQUIRED


1. IC 7408 - 3

2. IC 7404 1

3. IC7432 1

4. IC7486 1


6. LED - 5

7. Bread Board - 1


THEORY






process data in discrete form only. It is sometimes convenient to use Gray codes.

TRUTH TABLE:

14


EXCESS 3 CODE BCD CODE

E3 E2 E1 E0 B4 B3 B2 B1 B0

0 0 0 0 X X X X X

0 0 0 1 X X X X X

0 0 1 0 X X X X X

0 0 1 1 0 0 0 0 0

0 1 0 0 0 0 0 0 1

0 1 0 1 0 0 0 1 0

0 1 1 0 0 0 0 1 1

0 1 1 1 0 0 1 0 0

1 0 0 0 0 0 1 0 1

1 0 0 1 0 0 1 1 0

1 0 1 0 0 0 1 1 1

1 0 1 1 0 1 0 0 0

1 1 0 0 0 1 0 0 1

1 1 0 1 1 0 0 0 0

1 1 1 0 1 0 0 0 1

1 1 1 1 1 0 0 1 0

15


Excess 3 Code is a modified form of a BCD number. The Excess 3 code

can be derived from the natural BCD code by adding 3 to each coded number.

For example Decimal 12 can be represented in BCD as 0001 0010 . Now adding

3 to each digit we get excess 3 Code 01000101. With this information truth table

for BCD to Excess 3 code converter can be determined.

16



00 01 11 10

00 X X X

01

11 1 1 1

10

B4=E3E2(E1+E0) B3=E3(E2E1’E0’+E2’E1E0)

00 01 11 10

00 X X X

01 1

11

10 1 1 1

B2=E3E2’E1’+E3E2’E0’ B1=(E3’+E2’) (E1 XOR E0)

00 01 11 10

00 X X X

01 1 1

11 1 1

10 1 1

B0=EO’

17

00 01 11 10

00 X X X

01

11 1

10 1

00 01 11 10

00 X X X

01 1 1

11 1

10 1 1


PROCEDURE





RESULT:

Thus the Excess 3 to BCD was designed and implemented using logic

gates.

18


CIRCUIT DIAGRAM

TRUTH TABLE:

BINARY GODE GRAY CODEB3 B2 B1 B0 G3 G2 G1 G00 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

19


Ex. No 2 c DESIGN AND IMPLEMENTATION OF BINARY TO GRAY CODE CONVERTER USING LOGIC GATES

AIM To Design and implement the binary to gray code converter using logic

gates.

APPARATUS REQUIRED


1. IC 7486, - 1


3. LED - 4

4. Bread Board - 1


THEORY







The advantage of Gray codes over Binary codes is that only one bit in the code

group changes when going from one number to the next. Gray codes are used in

application where the normal sequence of the binary number may produce an

error or ambiguity during the transition from one number to the next. If binary

numbers are used a change from 0111 to 1000 may produce an intermediate

erroneous number 1001 if the right most bit takes more time to change the other

three bits. Gray code eliminates this problem since only one bit changes in value

during any transition between any two numbers.

20



00 01 11 10

00 0 1 0 1

01 0 1 0 1

11 0 1 0 1

10 0 1 0 1

G0=B1 XOR B0 G1=B2 XOR B1

00 01 11 10

00 0 0 0 0

01 1 1 1 1

11 0 0 0 0

10 1 1 1 1

G2=B3 XOR B2 G3=B3

21

00 01 11 10

00 0 0 1 1

01 1 1 0 0

11 1 1 0 0

10 0 0 1 1

00 01 11 10

00 0 0 0 0

01 0 0 0 0

11 1 1 1 1

10 1 1 1 1


1. The MSB of the gray numbers is the same as the MSB of the Binary

number so write as such.

2. To obtain the next gray digit, perform an exclusive – OR operation

between the first two binary bits.

3. Similarly, third digit is obtained by XORing 2nd & 3rd binary digit and so on.

PROCEDURE





RESULT:

Thus the binary to gray code converter was designed and implemented

using logic gates.

22


CIRCUIT DIAGRAM

TRUTH TABLE:

GRAY GODE BINARY CODEG3 G2 G1 G0 B3 B2 B1 B00 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

1 0 0 0 1 1 1 1

1 0 0 1 1 1 1 0

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 0 1 0

23


Ex. No 2 d DESIGN AND IMPLEMENTATION OF GRAY TO BINARY USING LOGIC GATES

AIM To Design and implement Gray to Binary code converter using logic gates.

APPARATUS REQUIRED


1. IC 7486, - 1


3. LED - 4

4. Bread Board - 1


THEORY







The advantage of Gray codes over Binary codes is that only one bit in the code

group changes when going from one number to the next. Gray codes are used in

application where the normal sequence of the binary number may produce an

error or ambiguity during the transition from one number to the next. If binary

numbers are used a change from 0111 to 1000 may produce an intermediate

erroneous number 1001 if the right most bit takes more time to change the other

three bits. Gray code eliminates this problem since only one bit changes in value

during any transition between any two numbers.

24



00 01 11 10

00 0 1 0 1

01 1 0 1 0

11 0 1 0 1

10 1 0 1 0

B0= G3 XOR G2 XOR G1 XOR GO B1=G3 XOR G2 XOR G1

00 01 11 10

00 0 0 0 0

01 1 1 1 1

11 0 0 0 0

10 1 1 1 1

B2=G3 XOR G2 B3=G3

25

00 01 11 10

00 0 0 1 1

01 1 1 0 0

11 0 0 1 1

10 1 1 0 0

00 01 11 10

00 0 0 0 0

01 0 0 0 0

11 1 1 1 1

10 1 1 1 1


PROCEDURE





RESULT:

Thus the Gray to Binary code was designed and implemented using logic

gates.

26


. CIRCUIT DIAGRAM

TRUTH TABLE:

SUBNIBBLE A NIBBLE B SUM/DIFFERENCE

CARRY/BORROW

A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 C4

0 0 0 1 1 1 0 1 0 1 1 0 1 0

0 1 0 0 0 1 0 0 0 0 0 0 0 1

1 0 1 1 1 0 1 0 1 0 0 0 1 0

1 1 0 0 1 1 0 1 1 0 0 1 0 1

27


Ex. No 3 a DESIGN AND IMPLEMENTATION OF FOUR BIT BINARY ADDER/ SUBRACTOR

AIM To Design and implement the four bit Binary Adder/ Subractor using

IC7483.

APPARATUS REQUIRED


1. IC 7486 , IC 7483 - Each 1


3. LED - 5

4. Bread Board - 1


THEORY

The addition and subtraction operations can be combined into one circuit

with the help of control input (SUB). To add the nibbles, SUB is to be made 0.To

subtract B4 B3 B2 B1 from A4 A3 A2 A1 , SUB is to be made 1. EXOR gates

function as controlled inverters. When SUB =1, B4B3 B2 B1 is complemented.

Now A4 A3 A2 A1,, complemented version of B4B3 B2 B1 and 1 at Ciin pin are added

together. Thus 2’s complement of subtrahend, is added with the minuend. If

minuend is less than subtrahend , the obtained output will be the 2’s complement

of difference.

28


29


PROCEDURE



3. Make SUB=0 and verify whether it works as a nibble adder.

4. Make SUB=1and verify whether it works as a nibble Subractor

5. Repeat steps 3 and 4 for other nibbles



RESULT:

Thus the four bit Binary Adder/ Subractor was designed and implemented

using IC7483.

30


CIRCUIT DIAGRAM

TRUTH TABLE:

NIBBLE A NIBBLE B BCD SUM CARRY

A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 C4

0 0 1 1 1 0 1 0 1 1 0 1 0

1 0 0 0 1 0 0 0 0 0 0 0 1

1 1 1 1 0 1 0 1 0 1 0 0 1

0 0 0 1 0 0 1 1 0 1 0 0 0

31


Ex. No 3 b DESIGN AND IMPLEMENTATION OF BCD ADDER

AIM To Design and implement the BCD Adder using IC7483.

APPARATUS REQUIRED


1. IC 7483 - 2

2. IC 7408 - 1


4. LED - 5

5. Bread Board - 1


THEORY

A BCD adder adds two BCD digits and produces a sum digit in BCD.

The two decimal digits, together with the input carry, are first added in the top 4

bit adder to produce the binary sum. When the output carry is equal to one ,

binary 0110 is added to the binary sum through the bottom 4 bit adder. The

output carry generated from the bottom adder can be ignored , since it supplies

information already available at the output carry terminal.

32


33


PROCEDURE



3. Make SUB=0 and verify whether it works as a nibble adder.

4. Make SUB=1and verify whether it works as a nibble Subractor

5. Repeat steps 3 and 4 for other nibbles



RESULT:

Thus the BCD Adder was designed and implemented using IC7483.

34


.CIRCUIT DIAGRAM

TRUTH TABLE:

35

BINARY WORDS A&B OUTPUTS

A1 A0 B1 B0 A>B A=B A<B0 0 0 0 0 1 0

0 0 0 1 0 0 1

0 0 1 0 0 0 1

0 0 1 1 0 0 1

0 1 0 0 1 0 0

0 1 0 1 0 1 0

0 1 1 0 0 0 1

0 1 1 1 0 0 1

1 0 0 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 0 1 0

1 0 1 1 0 0 1

1 1 0 0 1 0 0

1 1 0 1 1 0 0

1 1 1 0 1 0 0

1 1 1 1 0 1 0


Ex. No 4 a DESIGN AND IMPLEMENTATION OF TWO BIT MAGNITUDE COMPARATOR

AIM To Design and implement the two bit magnitude comparator

APPARATUS REQUIRED


1. IC 7408 - 2

2. IC 7404 - 1

3. IC 7432 - 1


5. LED - 3

6. Bread Board - 1


THEORY

Magnitude comparator is a logic circuit, which compares two binary

numbers and gives the result. It compares two input binary numbers (binary word

A&B) and gives three Outputs (A>B, A=, A<B)

If A is greater than B, a logic HIGH appears in A>B output. If A is less than B, a

logic HIGH appears in A<B output. If A is equal to B, a logic HIGH appears in A=B

output.

36



00 01 11 10

00

01 1

11 1 1 1

10 1 1

A>B = A0B1’B0’+A1B1’+A1A0B0’ A=B = (A0B0)’ (A1B1)’

00 01 11 10

00 1 1 1

01 1 1

11

101

A>B = A1’A0’B0+A0’B1 B0+A1’B1’

37

00 01 11 10

00 1

01 1

11 1

10 1


PROCEDURE





RESULT:

Thus the two bit magnitude comparator was designed and implemented

using logic gates.

.

38


CIRCUIT DIAGRAM

TRUTH TABLE:

Comparing input

Cascading Input Output

AB I(A>B) I(A=B) I(A<B) (A>B) (A=B) (A<B)A>B X X X 1 0 0

A=B

1 0 0 1 0 0X 1 X 0 1 00 0 1 0 0 10 0 0 1 0 11 0 1 0 0 0

A<B X X X 0 0 1

39


Ex. No 4 b DESIGN AND IMPLEMENTATION OF 8 BIT MAGNITUDE COMPARATOR

AIM To Design and implement the eight bit magnitude comparator

APPARATUS REQUIRED


1. IC 7485 - 2


3. LED - 3

4. Bread Board - 1


THEORY

Magnitude comparator is a logic circuit, which compares two binary numbers and

gives the result. It compares two input binary numbers (binary word A&B) and

gives three Outputs (A>B, A=, A<B)

If A is greater than B, a logic HIGH appears in A>B output. If A is less than B, a

logic HIGH appears in A<B output. If A is equal to B, a logic HIGH appears in A=B

output. In the case of 8 bit comparator using IC74682,

If A>B a logic low appears at pin no.1 (A>B, output)

If A=B a logic low appears at pin no.19 (A=B, output)

If A<B a logic high appears at both pin nos.19&1 (A=B, output)

8 bit comparison is obtained by cascading two 7485 IC’s as shown in the logic

diagram.The outputs of 1st IC 7485 i.e [ A>B,A=B,A<B ] are given to the

respective I(A>B), I(A=B),I(A<B) of 2nd IC7485. Depending upon the input condition the

corresponding output of the 2nd IC 7485 goes high.

A 8-bit comparator is obtained by cascading 2 IC 7465 in series as

shown. The o/p of first comparator is given as cascade input to the second

40


comparator .The 8-bit comparator Output is available at the output of the second

comparator.

41


PIN DIAGRAM

GND

876

VCC

IC 7485

3 42 51

B3 1(A<B) 1(A=B) 1(A>B) A>B A=B

A0B1A1A2B2A3

A<B

B0

910111213141516

42


PROCEDURE





RESULT:

Thus the 8 bit magnitude comparator was designed and implemented

using IC 7485.

43


CIRCUIT DIAGRAM

TRUTH TABLE:

Input Output

No of High data

i/p (I0 – I7)PE PO E O

Even 1 0 1 0

Odd 1 0 0 1

Even 0 1 0 1

Odd 0 1 1 0

X 1 1 0 0

X 0 0 1 1

44


Ex. No 5 DESIGN AND IMPLEMENTATION OF 16 BIT ODD/ EVEN PARITY CHECKER AND GENERATOR

AIM To Design and implement the 16 bit odd/ even parity checker and

generator

APPARATUS REQUIRED


1. IC 74180 - 1


3. LED - 2

4. Bread Board - 1


THEORY

The 74180 is a 9- bit Parity generator or checker commonly used to detect errors in high speed transmission or data retrieval systems. Both even and odd parity enable inputs and parity outputs are available for generating or checking parity on 8- bits.

In the function table , true active High or true active – low parity can be generated at both the Even or Odd outputs .

Active High Parity:

True active- High parity is established with Even parity enable input (PE) set high and Odd parity enable input (PO) set Low.

Active Low Parity:

True active low parity is established when PE is low and PO is High .When both the enable inputs are at same logic level , both outputs will be forced to the opposite logic level.

45


PIN DIAGRAM

GND

810

76

VCC912

IC 74180

11

3 4

1314

2 51

I6 I7 PE P0 Ee E0

I0I1I2I3I4I5

46


Parity Checking :

Parity Checking of a 9 bit word ( 8- bit plus parity ) is possible by using the two enable input plus an inverter as the ninth data

Checking – Active High Parity :

Ninth data input is tied to the PO input. Inverter is connected between PO and PE

Checking – Active Low Parity :

Ninth data input is tied to the PE input. Inverter is connected between PO and PE

Expansion to larger word size is accomplished by serially cascading the 74180 in 8- bit increments. The Even and odd parity outputs of the first stages are connected to the corresponding PO and PE inputs , respectively of the succeeding stage.

PROCEDURE





RESULT:

Thus the 8 bit magnitude comparator was designed and implemented

using IC 74180.

47


CIRCUIT DIAGRAM

TRUTH TABLE:

S1 S0 Y0 0 I00 1 I11 0 I21 1 I3

48


Ex. No 6 a DESIGN AND IMPLEMENTATION OF 4x1 MULTIPLEXER USING LOGIC GATES

AIM To Design and implement the 4X1 Multiplexer using logic gates.

APPARATUS REQUIRED


1. IC 7411 - 1

2. IC 7404 - 1


4. LED - 1

5. Bread Board - 1


THEORY

Multiplexer is a combinational circuit which can select any one of the inputs and route it to the output . A multiplexer has data input lines, data select lines and output. The logic symbol of a 4 line to 1 line MUX is shown. According to the two bit binary code on the data select inputs, corresponding data input line will be selected and routed to output. For example if s1s0 is 00, D0 will be selected , if s1s0 is 01, D1 will be selected and so on. From the truth table it can be seen that output.

Y= D0 S1’S0’ + D1S1’S0 + D2S1S0’ +D3S1S0

This Boolean expression can be realised using gates.

PROCEDURE





RESULT:

Thus the 4X1 Multiplexer was designed and implemented using logic

gates.

49


CIRCUIT DIAGRAM

TRUTH TABLE:

S3 S2 S1 S0 Y0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

1 1 1 1 I15

50


Ex. No 6 b DESIGN AND IMPLEMENTATION OF 16x1 MULTIPLEXER USING IC 74150

AIM To Design and implement the 16X1 Multiplexer using IC 74150.

APPARATUS REQUIRED


1. IC 74150 - 1


3. LED - 1

4. Bread Board - 1


THEORY

IC74150 is a 16 line to 1 MUX. It has 16 data inputs D0 through D15 and 4

data select inputs. The output is the complement of the input data. Strobe input

active low. For example if ABCD is 0001 , the output will be D1

PROCEDURE





RESULT:

Thus the 4X1 Multiplexer was designed and implemented using IC74150.

51


CIRCUIT DIAGRAM

TRUTH TABLE:

S1 S0 o/p0 0 D00 1 D11 0 D21 1 D3

52


Ex. No 6 c DESIGN AND IMPLEMENTATION OF 1X4 DEMULTIPLEXER USING LOGIC GATES

AIM To Design and implement the 1X4 Demultiplexer using logic gates.

APPARATUS REQUIRED


1. IC 7411 - 1

2. IC 7404 - 1


4. LED - 4

5. Bread Board - 1


THEORY

Demultiplexer does the reverse operation of the Multiplexer. The

data on a line is distributed on any one of the output line according to the binary

code on data select lines. The logic symbol of a 1 to 4 line demultiplexer is

shown. When the input on data select inputs S1S0 is 00 , data on the data line

will be available on D0 output , so on.

PROCEDURE





RESULT:

Thus the 1X4 Demultiplexer was designed and implemented using logic

gates.

53


CIRCUIT DIAGRAM

TRUTH TABLE:

S3 S2 S1 S0 O/P0 0 0 0 D0

0 0 0 1 D1

0 0 1 0 D2

0 0 1 1 D3

0 1 0 0 D4

0 1 0 1 D5

0 1 1 0 D6

0 1 1 1 D7

1 0 0 0 D8

1 0 0 1 D9

1 0 1 0 D10

1 0 1 1 D11

1 1 0 0 D12

1 1 0 1 D13

1 1 1 0 D14

1 1 1 1 D15

54


Ex. No 6 d DESIGN AND IMPLEMENTATION OF 1X16 DEMULTIPLEXER USING IC 74150

AIM To Design and implement the 16X1 Multiplexer using IC 74154.

APPARATUS REQUIRED


1. IC 74154 - 1


3. LED - 16

4. Bread Board - 1


THEORY

IC74154 is a 1 to 16 demultiplexer. It has a data input D and 16 output Y0

through Y15 and an active low strobe input. The data select inputs ABCD decides

the output pin at which the data should be available. For example if ABCD is

0001,data input will be available at Y1.

PROCEDURE





RESULT:

Thus the 1X16 Demultiplexer was designed and implemented using

IC74154.

55


CIRCUIT DIAGRAM

TRUTH TABLE:

D3 D2 D1 DO X Y

1 0 0 0 0 0

0 1 0 0 0 1

0 0 1 0 1 0

0 0 0 1 1 1

56


Ex. No 7 a DESIGN AND IMPLEMENTATION OF 4X2 ENCODER USING LOGIC GATES

AIM To Design and implement the 4X2 encoder using logic gates.

APPARATUS REQUIRED


1. IC 7432 - 1


3. LED - 2

4. Bread Board - 1


THEORY

Encoder is an combinational circuit that performs inversion

operation of decoder. An encoder has 2n input lines and n output lines. The

output lines generate the binary code corresponding to the input value. The

encoder is implemented using OR gate.

PROCEDURE





RESULT:

Thus the 4x2 Encoder was designed and implemented using logic gates.

57


CIRCUIT DIAGRAM

TRUTH TABLE:

D0 D1 D2 D3 D4 D5 D6 D7 D8 Q0 Q1 Q2 Q30 1 1 1 1 1 1 1 1 1 1 1 0

1 0 1 1 1 1 1 1 1 1 1 0 1

1 1 0 1 1 1 1 1 1 1 1 0 0

1 1 1 0 1 1 1 1 1 1 0 1 1

1 1 1 1 0 1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1 1 1 0 0 1

1 1 1 1 1 1 0 1 1 1 0 0 0

1 1 1 1 1 1 1 1 1 0 1 1 1

1 1 1 1 1 1 1 0 1 0 1 1 0

1 1 1 1 1 1 1 1 0 0 1 0 1

58


Ex. No 7 b DESIGN AND IMPLEMENTATION OF ENCODER USING IC 74147

AIM To Design and implement the encoder using IC 74147.

APPARATUS REQUIRED


1. IC 74147 - 1


3. LED - 4

4. Bread Board - 1


THEORY

Encoder is an combinational circuit that performs inversion operation of

decoder. An encoder has 2n input lines and n output lines. The output lines

generate the binary code corresponding to the input value. The encoder is

implemented using OR gate.

PROCEDURE





RESULT:

Thus the encoder was designed and implemented using IC74147.

59


CIRCUIT DIAGRAM

60


Ex. No 7 C DESIGN AND IMPLEMENTATION OF 2X4 DECODER USING LOGIC GATES

AIM To Design and implement the 2X4 decoder using logic gates.

APPARATUS REQUIRED


1. IC 7432 - 1


3. LED - 2

4. Bread Board - 1


THEORY

A Decoder, which has an n-bit binary input code and a one activated o/p

out of 2n Output code is called biary Decoder. A binary decoder is used when it is

necessary to activate exactly one of 2n o/p’s based on n-bit value. In the truth

table of 2 to 4 decoder, if enable input is 1 (EN =1) One and only one of the o/p’s.

y0 to y3 is active for a given input .the o/p y0 is active ,when output A=B=0, the o/p

y1 is active ,when i/p A=o and B=1 .If enable input is 0 , (i.e.) EN =0 ,then all the

o/p’s are 0.Decoder Circuits are commonly used for binary to decimal conversion.

BCD to decimal Decoder is also referred as 1 of 10 decoder, as only one of the

ten outputs lines is high or low at a time.

61


TRUTH TABLE:

S1 S0 D3 D2 D1 DO

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

62


PROCEDURE





RESULT:

Thus the 2X4 Decoder was designed and implemented using logic gates.

63


CIRCUIT DIAGRAM

TRUTH TABLE:

A B C D D0 D1 D2 D3 D4 D5 D6 D7 D80 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 1 1 0 1 1 1 1 1 1 1

0 0 1 0 1 1 0 1 1 1 1 1 1

0 0 1 1 1 1 1 0 1 1 1 1 1

0 1 0 0 1 1 1 1 0 1 1 1 1

0 1 0 1 1 1 1 1 1 0 1 1 1

0 1 1 0 1 1 1 1 1 1 0 1 1

0 1 1 1 1 1 1 1 1 1 1 1 1

1 0 0 0 1 1 1 1 1 1 1 0 1

1 0 0 1 1 1 1 1 1 1 1 1 0

64


Ex. No 7 d DESIGN AND IMPLEMENTATION OF DECODER USING IC 7445

AIM To Design and implement the decoder using IC 7445.

APPARATUS REQUIRED


1. IC 7445 - 1


3. LED - 4

4. Bread Board - 1


THEORY

A Decoder, which has an n-bit binary input code and a one activated o/p

out of 2n Output code is called biary Decoder. A binary decoder is used when it is

necessary to activate exactly one of 2n o/p’s based on n-bit value. In the truth

table of 2 to 4 decoder, if enable input is 1 (EN =1) One and only one of the o/p’s.

y0 to y3 is active for a given input .the o/p y0 is active ,when output A=B=0, the o/p

y1 is active ,when i/p A=o and B=1 .If enable input is 0 , (i.e.) EN =0 ,then all the

o/p’s are 0.Decoder Circuits are commonly used for binary to decimal conversion.

BCD to decimal Decoder is also referred as 1 of 10 decoder, as only one of the

ten outputs lines is high or low at a time.

PROCEDURE





RESULT:

Thus the decoder was designed and implemented using IC7445.

65


CIRCUIT DIAGRAM

66


Ex. No 8 a DESIGN AND IMPLEMENTATION OF 4 BIT RIPPLE COUNTER

AIM To Design and implement the 4 bit ripple counter.

APPARATUS REQUIRED


1. IC 7476 - 2


3. LED - 4

4. Bread Board - 1


THEORY

Asynchronous counter consists of series connections of flipflops JK type,

With each flipflop connected to clock pulse of the next higher order flipflop. The

Flipflop holding the least significant bit receives the incoming count pulse. It is

obvious that the lower order bit Q0 is complemented with each count pulse.

When Q0 goes from 1 to 0, it complements Q1. When Q1 goes from 1 to 0 it

complements Q2 and so on. The output transition of Q3 if connected to next

stage will not trigger the next flipflop since it goes from 0 to 1. The flipflop

changes one at a time in rapid succession and the signal propagates through the

counter in ripple fashion and some times called as ripple counter.

In the circuit satup all flipflopa are clocked by the Q output of the

preceeding flipflop. JK inputs of all the F/F are connected to a high state.A Ripple

counter comprising of n F/F can be used to Count upto 2n pulses. The counter

gives a natural binary count from 0 to 15 and resets to initial condition on the 16 th

input pulse.

67


TRUTH TABLE:

68

CLOCKOUTPUTS

Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

16 0 0 0 0


PROCEDURE



3. Apply Count Pulse to the circuit.

4. Observe the output and verify with your truth table.

RESULT:

Thus the 4 bit ripple counter was designed and implemented using JK flip

flop.

69


CIRCUIT DIAGRAM

70


Ex. No 8 b DESIGN AND IMPLEMENTATION OF MOD 10 COUNTER

AIM To Design and implement the MOD 10 counter.

APPARATUS REQUIRED


1. IC 7476 - 2

2. IC 7400 - 1


4. LED - 4

5. Bread Board - 1


THEORY










The Circuit of the decade counter is similar to 4 bit ripple counter but with

the aid of the logic circuit, the count is limited to 9 . As soon as the count 1010

takes place , a NAND gate clears the F/F and Counting restarts from 0 .

71


TRUTH TABLE:

72

CLOCKOUTPUTS

Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0


PROCEDURE





RESULT:

Thus the MOD 10 counter was designed and implemented using JK flip

flop.

73


CIRCUIT DIAGRAM

74


Ex. No 8 c DESIGN AND IMPLEMENTATION OF MOD 12 COUNTER

AIM To Design and implement the MOD 12 counter.

APPARATUS REQUIRED


1. IC 7476 - 2

2. IC 7400 - 1


4. LED - 4

5. Bread Board - 1


THEORY










MOD 12 counter requires 4 stages of F/F. Here , the count is

limited to 11. As soon as the count 1100 takes place, a NAND gate clears the

F/F and the Counting restarts from 0.

75


TRUTH TABLE:

76

CLOCKOUTPUTS

Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 0 0 0 0


PROCEDURE





RESULT:

Thus the MOD 12 counter was designed and implemented using JK flip

flop.

77


CIRCUIT DIAGRAM

CLR

CLK

M

HIGH

Q0 Q1 Q2

U4B345

6U2A

7473J

14

CLK1

K3

Q12

Q13CL

2U4A

7411

12

1312

U6A

7404

1 2

U1A

7473J

14

CLK1

K3

Q12

Q13CL

2

U1B

J7

CLK5

K10

Q9

Q8CL

6

U3A

7486

1

23

U5A

7432

1

23

78


Ex. No 9 DESIGN AND IMPLEMENTATION OF SYNCHRONOUS UP DOWN COUNTER

AIM To Design and implement the Synchronous up down counter.

APPARATUS REQUIRED


1. IC 7476 - 2

2. IC 7411 - 1

3. IC 7432 - 1

4. IC 7404 1


6. LED - 3

7. Bread Board - 1


THEORY

A circuit of a 3-bit synchronous up-down counter and a table of its sequence

are shown below. Similar to an asynchronous up-down counter, a synchronous

up-down counter also has an up-down control input. It is used to control the

direction of the counter through a certain sequence

for both the UP and DOWN sequences, Q0 toggles on each clock pulse.

for the UP sequence, Q1 changes state on the next clock pulse when

Q0=1.

for the DOWN sequence, Q1 changes state on the next clock pulse when

Q0=0.

for the UP sequence, Q2 changes state on the next clock pulse when

Q0=Q1=1.

for the DOWN sequence, Q2 changes state on the next clock pulse when

Q0=Q1=0.

79


TRUTH TABLE:

Present state Next State JK F/F Inputs

Mode Q2 Q1 Q0 Q2 Q1 Q0 J0 K0 J1 K1 J2 K2

0 0 0 0 0 0 1 1 X 0 X 0 X

0 0 0 1 0 1 0 X 1 1 X 0 X

0 0 1 0 0 1 1 1 X X 0 0 X

0 0 1 1 1 0 0 X 1 X 1 1 X

0 1 0 0 1 0 1 1 X 0 X X 0

0 1 0 1 1 1 0 X 1 1 X X 0

0 1 1 0 1 1 1 1 X X 0 X 0

0 1 1 1 0 0 0 X 1 X 1 X 1

1 1 1 1 1 1 0 X 1 X 0 X 0

1 1 1 0 1 0 1 1 X X 1 X 0

1 1 0 1 1 0 0 X 1 0 X X 0

1 1 0 0 0 1 1 1 X 1 X X 1

1 0 1 1 0 1 0 X 1 X 0 0 X

1 0 1 0 0 0 1 1 X X 1 0 X

1 0 0 1 0 0 0 X 1 0 X 0 X

1 0 0 0 1 1 1 1 X 1 X 1 X

80


PROCEDURE



3. Apply Up=1 and clock pulse.

4. Apply Up=0, Down=1 and clock pulse


81



00 01 11 10

00 0 1 X X

01 0 1 X X

11 1 0 X X

10 1 0 X X

J1 = M’ Q0 + M Q0’ K1 = M’Q0 + MQ0’

00 01 11 10

00 0 0 1 0

01X X X X

11X X X X

101 0 0 0

J2 = M’Q1Q0 + MQ1’Q0’ K2 = MQ1’Q0’ + M’Q1Q0

82

00 01 11 10

00 X X 1 0

01 X X 1 0

11 X X 0 1

10 X X 0 1

00 01 11 10

00X X X X

010 0

1 0

111 0 0 0

10X X X X


RESULT:

Thus the Synchronous counter was designed and implemented using JK

flip flop.

83


CIRCUIT DIAGRAM

TRUTH TABLE:

CLK SI S01 1 x2 0 x3 1 x4 1 15 0 06 0 17 1 1

84


Ex. No 10 a DESIGN AND IMPLEMENTATION OF SISO

AIM To Design and implement the SISO using D flip flop.

APPARATUS REQUIRED


1. IC 7474 - 2


3. LED - 1

4. Bread Board - 1


THEORY

A register is simply a group of flip flops that can be used to store a binary

number. A shift register is nothing but a register which accepts a binary number

and shifts it. The data can be entered to the shift register either in serial or

parallel. Similarly, the output can be taken from it either in parallel. Since there

are two ways to shift data into a shift register and similarly two ways to shift data

out of register, four basic register types can be constructed viz, serial in serial

out(SISO), parallel in serial out(PISO), serial in parallel out(SIPO) and parallel in

parallel out (PIPO)shift register. It allows the data to enter serially. The output

data can be available in parallel or serial

PROCEDURE



3. Give serial inputs SI and clock to the circuit.

4. Observe the logical output S0 and verify with your truth table.

RESULT:

Thus the SISO was designed and implemented using D flip flop.

85


CIRCUIT DIAGRAM

TRUTH TABLE:

CLK SI P0 P1 P2 P31 1 1 X X X2 0 0 1 X X3 1 1 0 1 X4 1 1 1 0 15 0 0 1 1 06 0 0 0 1 17 1 1 0 0 1

86


Ex. No 10 b DESIGN AND IMPLEMENTATION OF SIPO

AIM To Design and implement the SIPO using D flip flop.

APPARATUS REQUIRED


6. IC 7474 - 2


8. LED - 4

9. Bread Board - 1


THEORY









data can be available in parallel or serial In this type of shift register data can be

fed in serial or parallel using the mode control pin. Output can be taken serial or

in parallel. Serial input is fed through A input and parallel input is fed through

ABCD. Serial output is taken from QD and parallel output from QA QB QC QD.

87


88


PROCEDURE



3. Give serial inputs SI and clock to the circuit.

4. Observe the logical output S0 and verify with your truth table.

RESULT:

Thus the SIPO was designed and implemented using D flip flop.

89


CIRCUIT DIAGRAM

90


Ex. No 10 c DESIGN AND IMPLEMENTATION OF PISO

AIM To Design and implement the PISO using D flip flop.

APPARATUS REQUIRED


11. IC 7474 - 2


13. LED - 1

14. Bread Board - 1


THEORY










PROCEDURE



3. Give serial inputs and clock to the circuit.


RESULT:

Thus the PISO was designed and implemented using D flip flop.

91


CIRCUIT DIAGRAM

92


Ex. No 10 d DESIGN AND IMPLEMENTATION OF PIPO

AIM To Design and implement the PIPO using D flip flop.

APPARATUS REQUIRED


16. IC 7474 - 2


18. LED - 4

19. Bread Board - 1


THEORY










PROCEDURE



3. Give serial inputs and clock to the circuit.


RESULT:

Thus the PIPO was designed and implemented using D flip flop.

93

Lab Mano Final

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