L14 Placement and Routing

7/31/2019 L14 Placement and Routing

1/40

Massachusetts Institute of Technology

1

L14 Physical Design

6.375 Spring 2007

Ajay Joshi


2/40

6.375 S rin 2007 L14 2

RTL design flow

RTLSynthesis

HDL

netlist

Logicoptimization

netlist

Library/modulegenerators

physicaldesign

layout

manualdesign

a

b

s

q0

1

d

clk

a

b

s

q0

1

d

clk


3/40

6.375 S rin 2007 L14 3

Physical design overall flow

Placement

Cost Estimation

Routing RegionDefinition

Global Routing

Compaction/clean-up

Detailed Routing

Cost Estimation

Write Layout Database

Floorplanning

Partitioning

Improvement

Cost EstimationImprovement

Improvement


4/40

6.375 S rin 2007 L14 4

PartitioningDecompose a large complex system into

smaller subsystemsDecompose hierarchically until eachsubsystem is of manageable size

Design each subsystem separately to speedup the processMinimize connection between twosubsystems to reduce interdependency


5/40

6.375 S rin 2007 L14 5

Partitioning at different levels*

* Sherwani 92


6/40

6.375 S rin 2007 L14 6

Partitioning example*

* Sherwani 92


7/406.375 S rin 2007 L14 7

Partitioning problemObjective:

Minimize interconnections between partitionsMinimize delay due to partitioning

Constraints

Number of terminals in each subsystem (Count (V i)


8/406.375 S rin 2007 L14 8

Kernighan-Lin algorithmInput: Graph representation of the circuit

Output: Two subsets of equal sizesBisecting algorithm :

Initial bisection

Vertex pairs which gives the largest decrease incutsize are exchangedExchanged vertices are lockedIf no improvement is possible and some vertices

are still unlocked then vertices which give smallestincrease are exchanged


9/406.375 S rin 2007 L14 9

K-L algorithm example*

* Sherwani 92


10/406.375 S rin 2007 L14 10

Partitioning methodsTop-down partitioning

Iterative improvementSpectral basedClustering methodsNetwork flow basedAnalytical basedMulti-level

Bottom-up clustering

Unit delay modelGeneral delay modelSequential circuits with retiming


11/406.375 S rin 2007 L14 11


Placement

Cost Estimation


Global Routing

Compaction/clean-up

Detailed RoutingCost Estimation


Floorplanning

Partitioning

Improvement


Improvement


12/406.375 S rin 2007 L14 12

FloorplanningOutput from partitioning used for

floorplanningInputs:

Blocks with well-defined shapes and areaBlocks with approximated area and no particularshapeNetlist specifying block connections

Outputs:

Locations for all blocks


13/406.375 S rin 2007 L14 13

Floorplanning problem*Objectives

Minimize areaReduce wirelengthMaximize routabilityDetermine shapes

of flexible blocksConstraints

Shape of each blockArea of each block

Pin locations foreach blockAspect ratio

* Sung Kyu Lim


14/406.375 S rin 2007 L14 14

Slicing floorplan sizing*General case: all modules are soft macros

Phase 1: bottom-upInput floorplan tree, modules shapesStart with a sorted shapes list of modulesPerform vertical_node_sizing andhorizontal_node_sizingOn reaching the root node, we have a list ofshapes, select the one that is best in terms of area

Phase 2: top-downTraverse the floorplan tree and set modulelocations

* Sung Kyu Lim


15/406.375 S rin 2007 L14 15

Sizing example*

* Sun K u Lim


16/406.375 S rin 2007 L14 16

Floorplanning AlgorithmsStockmeyer algorithm

Simulated annealingLinear programmingSequence-pair based floorplanning


17/406.375 S rin 2007 L14 17

Floorplanning - Encounter


18/406.375 S rin 2007 L14 18


Placement

Cost Estimation


Global Routing

Compaction/clean-up



Floorplanning

Partitioning

Improvement


Improvement


19/406.375 S rin 2007 L14 19

PlacementThe process of arranging circuit components

on a layout surfaceInputs : Set of fixed modules, netlistOutput : Best position for each module based

on various cost functionsCost functions include wirelength, wireroutability, hotspots, performance, I/O pads


20/406.375 S rin 2007 L14 20

Good placement vs Bad placement*

* S. Devadas

Good placementNo congestionShorter wiresLess metal levelsSmaller delayLower power dissipation

Bad placementCongestionLonger wire lengthsMore metal levelsLonger delayHigher power dissipation


21/406.375 S rin 2007 L14 21

Simulated annealing algorithmGlobal optimization technique

Cooling schedule is adoptedAn action performed at each new temperatureEstimate the cost associated with an action

If new cost < old cost accept the actionIf new cost > old cost then accept the actionwith probability p

Probability p depends on a temperatureschedule Higher p at higher temperature


22/406.375 S rin 2007 L14 22

Annealing curve

* Sherwani 92


23/406.375 S rin 2007 L14 23

Placement using simulated annealingUse initial placement results e.g. random

placementTwo stage process*

Stage 1Modules moved between different rows and same rowModule overlaps allowedStage two begins when temperature falls below a certainvalue

Stage 2

Module overlaps removedAnnealing continued, but interchange adjacent modulesin the same row

* Sechen DAC86


24/406.375 S rin 2007 L14 24

Placement methodsConstructive methods

Cluster growth algorithmForce-directed methodAlgorithm by GotoMin-cut based algorithm

Iterative improvement methodsPairwise exchangeSimulated annealing Timberwolf

Genetic algorithmAnalytical methods

Gordian, Gordian-L


25/406.375 S rin 2007 L14 25

Placement - Encounter


26/406.375 S rin 2007 L14 26

Optimized placement - Encounter


27/406.375 S rin 2007 L14 27


Placement

Cost Estimation


Global Routing

Compaction/clean-up



Floorplanning

Partitioning

Improvement


Improvement


28/406.375 S rin 2007 L14 28

RoutingConnect the various standard cells using

wiresInput:

Cell locations, netlist

Output:Geometric layout of each net connecting variousstandard cells

Two-step process

Global routingDetailed routing


29/406.375 S rin 2007 L14 29

Global routing vs detailed routing*

* Sung Kyu Lim


30/406.375 S rin 2007 L14 30

Routing problem formulationObjective

100% connectivity of a systemMinimize areaMinimize wirelength

ConstraintsNumber of routing layersDesign rulesTiming (delay)

CrosstalkProcess variations


31/40

6.375 S rin 2007 L14 31

Maze routing - example

* Sung Kyu Lim


32/40

6.375 S rin 2007 L14 32

Maze routingMainly for single-layer routing

StrengthsFinds a connection between two terminals if itexists

WeaknessLarge memory required as dense layoutSlow

Application global routing, detailed routing


33/40

6.375 S rin 2007 L14 33

Routing algorithmsGlobal routing

Maze routingCong/Preas algorithm Spanning tree algorithmSteiner tree algorithm

Detailed routing2-L Channel routing: Basic left-edge algorithmY-K algorithm


34/40

6.375 S rin 2007 L14 34

Detailed routing - Encounter


35/40

6.375 S rin 2007 L14 35

Critical path - Encounter


36/40

6.375 S rin 2007 L14 36

Specialized routing

* Sherwani 92


37/40

6.375 S rin 2007 L14 37

Clock distribution - Encounter


38/40

6.375 S rin 2007 L14 38

Power routing*

*6.884 Spring 2005


39/40

6.375 S rin 2007 L14 39

Power distribution issues

Noise in power supplyIR drop (static)L di/dt (transient)

ElectromigrationSolution: decoupling capacitance, wirematerial

Kaveh Shakeri


40/40

SummaryLooked at the physical design flow

Involved several stepsPartitioningFloorplanningPlacementRouting

Each step can be formulated as anoptimization problem

Need to go through 2 or more iterations ineach step to generate an optimized solution

L14 Placement and Routing

Documents

Transcript of L14 Placement and Routing