IEEE TRANSACTIONS ON NANOBIOSCIENCE, VOL. 13, NO. 1, …considers placement with variation, and it...

IEEE TRANSACTIONS ON NANOBIOSCIENCE, VOL. 13, NO. 1, MARCH 2014 3

Physical-Level Synthesis for Digital Lab-On-a-ChipConsidering Variation, Contamination, and Defect

Chen Liao and Shiyan Hu, Senior Member, IEEE

Abstract—Microfluidic lab-on-a-chips have been widely utilizedin biochemical analysis and human health studies due to highdetection accuracy, high timing efficiency, and low cost. Theincreasing design complexity of lab-on-a-chips necessitates thecomputer-aided design (CAD) methodology in contrast to theclassical manual design methodology. A key part in lab-on-a-chipCAD is physical-level synthesis. It includes the lab-on-a-chipplacement and routing, where placement is to determine thephysical location and the starting time of each operation androuting is to transport each droplet from the source to the desti-nation. In the lab-on-a-chip design, variation, contamination, anddefect need to be considered. This work designs a physical-levelsynthesis flow which simultaneously considers variation, con-tamination, and defect of the lab-on-a-chip design. It proposes amaze routing based, variation, contamination, and defect awaredroplet routing technique, which is seamlessly integrated into anexisting placement technique. The proposed technique improvesthe placement solution for routing and achieves the placementand routing co-optimization to handle variation, contamination,and defect. The simulation results demonstrate that our techniquedoes not use any defective/contaminated grids, while the techniquewithout considering contamination and defect uses 17.0% of thedefective/contaminated grids on average. In addition, our routingvariation aware technique significantly improves the averagerouting yield by 51.2% with only 3.5% increase in completiontime compared to a routing variation unaware technique.

Index Terms—Contamination, defect, lab-on-a-chip design au-tomation, physical-level synthesis, variation.

I. INTRODUCTION

T HE microfluidic lab-on-a-chip allows the automation ofmany traditional laboratory procedures in biochemistry

[2], [3]. It has been widely used in different applications dueto its advantages in sample holding, reagent mixing, separa-tion and detection, etc. [4], [5]. For example, the microfluidiclab-on-a-chip is applied in the electrochemical real-time moni-toring of glucose and oxygen in [6] and vitro hepatotoxicity in[7]. Meanwhile, there are also some works on the human healthrelated research. For example, the proteomic analysis for cer-vical cancer based onmicrofluidic lab-on-a-chips is given in [8].There are generally two types of lab-on-a-chips. The first

type is based on the usage of continuous fluid flow, permanentlyetched micropumps, microvalves, and microchannels, while

Manuscript received September 03, 2012; revised September 20, 2013; ac-cepted December 04, 2013. Date of current version February 27, 2014. Asteriskindicates corresponding author.*C. Liao is with the Department of Electrical and Computer Engineering,

Michigan Technological University, Houghton, MI 49931 USA (e-mail:[email protected]).S. Hu is with the Department of Electrical and Computer Engineering,

Michigan Technological University, Houghton, MI 49931 USA (e-mail:[email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TNB.2013.2294943

Fig. 1. The schematic of a lab-on-a-chip [1], [9]–[11].

the second type is based on the discrete droplets. The discretedroplet based lab-on-a-chip is a scalable system with a twodimensional array and the independently controllable droplets[9]. Each droplet is transported, stored, mixed, reacted, oranalyzed in a discrete manner using a standard set of basicinstructions. The complex procedures, such as chemical syn-thesis or biological assays, can be built up step by step. Theusage of discrete droplets also leads to the reconfigurabilitythat the same location can be used for operations at differenttime intervals [9]. Refer to Fig. 1 [1], [9]–[11] for the schematicof lab-on-a-chip [1], [9]–[11]. The droplets containing thebiochemical samples are between two electrified plates. In theelectrowetting based lab-on-a-chip, through modulating theexternal electric potential the droplets can be moved to anyplace in the lab-on-a-chip [12].It is well known that compared to manual integrated circuit

(IC) design, the computer-aided design (CAD) methodologiescan largely reduce the design efforts. CAD methodologieshave not been widely used in commercial lab-on-a-chips.However, the increasing design complexity and decreasing sizewill invoke a shift from the manual lab-on-a-chip design to alab-on-a-chip CAD [1], [9], [13]. A key part in the lab-on-a-chipCAD flow is the lab-on-a-chip physical-level synthesis, whichincludes placement and routing. Lab-on-a-chip placement isto determine the physical location and the starting time ofeach operation such that the overall completion time is min-imized satisfying the precedence constraint, non-overlappingconstraint and resource constraint. Precedence constraint de-fines the temporal relationship between operations through asequencing graph. Non-overlapping constraint ensures that nooperations can be performed during the same time period at thesame location. Resource constraint is that the operations sharingsome resources can be scheduled at the same time period only ifthere are enough available resources [1]. Lab-on-a-chip routing

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4 IEEE TRANSACTIONS ON NANOBIOSCIENCE, VOL. 13, NO. 1, MARCH 2014

Fig. 2. Illustration of lab-on-a-chip placement and routing.

is to transport the droplets from the source to the destinationto ensure the successful completion of the operations suchthat the routing length is minimized while satisfying timingconstraint and fluidic constraint. Timing constraint specifiesthe maximum timing of a droplet transporting from the sourceto the destination. Fluidic constraint states that the minimumspacing between two droplets is one grid [14]. As shown inFig. 2, each operation can be treated as a three-dimensional(3-D) module, decided by and , where plane is itsspace and is the time duration of this operation. Together withthe reconfigurability of lab-on-a-chips, a 3-D module librarycan be designed on biochemical operations [1], [9]. Theseoperations/modules need to be placed at the 3-D space, and thedroplets are transported from the source to destination, whereboth of the source and destination can be either an operation ora reservior/dispensing port.Contamination and defect also need to be considered during

lab-on-a-chip physical-level synthesis [15]. Contamination inlab-on-a-chip is caused by liquid residue of the transportationbetween different operations [15]. The contaminated gridsusually need to wait for a certain time before they can beused for routing again. The defect considered in this workis those due to a failure source, which is defined as the ab-normality leading to a defect in the fabrication process. Thefailure source could be foreign particles, stiction, and so on[16], [17]. The defective grids cannot be used for routing atany time. Fig. 3 shows an illustration of contaminated gridand defective grid. Contamination aware and defect toleranttechnique in microfluidic lab-on-a-chip has been studied inthe literature of lab-on-a-chip CAD. A contamination awarealgorithm for droplet routing in lab-on-a-chip is proposedin [15]. [18] considers the cross-contamination problems onpin-constrained lab-on-a-chips during the lab-on-a-chip designflow. [19] proposes a unified synthesis method that simulta-neously consider defect tolerant architectural synthesis anddefect aware physical design for lab-on-a-chip. [17] designs adefect tolerant methodology based on graceful degradation anddynamic reconfiguration for lab-on-a-chip design.On the other hand, the biochemical reaction is sensitive to

variations [1], [20], [21]. For example, the temperature variationcould lead to the operation completion time variation. [3] indi-cates that the variability in biochemical operations can impactthe correctness of the biochemical application. [22] describesthat the temperature variations are an important concern since

Fig. 3. An illustration of routing with timing constraint, considering contam-ination and defect. The routing needs to avoid the contaminated grid and de-fective grid. The gray route may violate the timing constraint since the routinglength might be greater than , e.g., .

Fig. 4. (a) An example of placement and routing. The lower left corner of amodule can be placed at a grid. (b) The module could have variational height,and is touching with each other. Thus, there is no space for its routing, whichleads to the failure of routing.

some DNA would denature at inappropriate temperature. Thelab-on-a-chip routing needs to consider operation completiontime variation. Fig. 4 shows that without considering variation,a grid which is supposed to be used for routing may be oc-cupied by the module with variational height, and could leadto the failure of routing [21], [23]. However, the traditionallab-on-a-chip routing does not consider the variation. Note thatthis work is different from [1] in the following aspects. [1] onlyconsiders placement with variation, and it does not considerrouting. In contrast, this work considers placement and routingco-optimization with variation, and also considers contamina-tion and defect.In this work, a lab-on-a-chip physical-level synthesis is

proposed considering variation, contamination, and defect. Themain contribution of the paper is summarized as follows.• This work proposes a lab-on-a-chip physical-level syn-thesis flow which simultaneously considers all the impactsof variation, contamination, and defect.

• A maze routing based, variation, contamination, and de-fect aware droplet routing technique is proposed and inte-grated into the placement technique in [1]. It improves theplacement solution in order to satisfy all the constraints forrouting, which is the main reason for the routing yield im-provement. This realizes the placement and routing co-op-timization and enhances the lab-on-a-chip CAD tool.

• The simulation is performed on a set of standard test-cases. Without considering variation, the routing yieldis very small. With considering variation, our technique

LIAO AND HU: PHYSICAL-LEVEL SYNTHESIS FOR DIGITAL LAB-ON-A-CHIP 5

can successfully route the droplets while satisfying therouting yield constraint. It significantly improves theaverage routing yield by 51.2% with only 3.5% increasein completion time.

• Our technique does not use any defective/contaminatedgrids, while the technique without considering contamina-tion and defect uses 17.0% of the defective/contaminatedgrids on average.

II. PRELIMINARIES

A. Problem Formulation

A lab-on-a-chip performs biochemical reactions/operationsthrough manipulating droplets which contain the biochemicalreactants. Recall that each biochemical operation can be consid-ered as a three-dimensional (3-D) module decided by and, where plane is its space and is its duration. In practice,the movement of droplets is manipulated at discrete intervals,and the biochemical operations are scheduled at discrete time.Thus, a lattice is laid onto the 3-D space and divides the space toa set of unit grids, which are the lab-on-a-chip routing grids. Thedroplets can only be moved through these grids, and a modulecan only be placed at a grid. Fig. 2 gives an illustration.In the lab-on-a-chip placement, it is to determine the phys-

ical location and the starting time of each operation such thatthe overall completion time is minimized while satisfying theprecedence constraint, non-overlapping constraint and resourceconstraint. Precedence constraint defines the temporal relation-ship between operations through a sequencing graph. Non-over-lapping constraint ensures that no operations can be performedduring the same time period at the same location. Resourceconstraint is that the operations sharing some resources can bescheduled at the same time period only if there are enough avail-able resources [1].In the traditional lab-on-a-chip routing, given a set of sources

and destinations, the droplets are manipulated to transport fromits source to the destination, while satisfying timing constraintand fluidic constraint. The source and destination can be eithera module or a reservoir/dispensing port. Dispensing port is aplace on the chip for some droplet generation. Timing constraintspecifies the maximum timing of a droplet transporting from thesource to the destination [14]. Fluidic constraint states that theminimum spacing between two droplets is one grid [14].As the routing procedure is neglected when performing the

lab-on-a-chip placement in some previous works [1], [11], theplacement solution may have no space for routing, which resultsin the negative effect on the physical-level synthesis. Since it re-quires to satisfy the fluidic constraint for routing, which statesthat the minimum space between two droplets or routing pathsis at least one grid, the two modules close to each other needto keep the distance of at least two unit grids. Otherwise, it isconsidered as non-routable placement. Fig. 5 shows such an ex-ample. Thus, if a placement solution has no space to route, onecould improve the placement to make it routable, which meansthat there is space for routing and the updated placement satis-fies the precedence constraint, non-overlapping constraint andresource constraint.

Fig. 5. An example of non-routable placement solution for testcase vitro3–1using [1].

Given an initial placement solution consisting of a set ofmodules specified by some lengths, widths and heights, and thesources and destinations, our physical-level synthesis problemwithout considering variation aims to improve the placementsolution to be routable, and route each droplet from its sourceand destination, such that the timing constraint and fluidicconstraint are satisfied. In addition, the contamination anddefect also need to be considered during routing.On the other hand, the biochemical reaction is sensitive

to many variations [21]. Thus, the case that the biochemicalreaction completion time can have variation necessitates thelab-on-a-chip routing considering variation. Since each modulecan be considered as a 3-D module as mentioned above, for amodule , it can be decided by , where

and respectively denote its length, widthand height. Note that the height is the time needed to performthe corresponding biochemical operation. Refer to Fig. 4. Thecompletion time variation affects the height of the module

. Define the resultant height to be variational height,denoted by . The model in [1] defines

(1)

where is the variational range for the height of themodulefollowing Gaussian distribution, is a user defined parameterwhich can adjust the induced variation to the module,. Larger , larger variation. When , it leads to a de-sign without considering variation, and when , it leadsto worst-case design. Note that in (1), with any fixed , theheight of module will be a constant [1]. To explore the besttradeoff between the routing yield and CAD design solutionquality using different , a search needs to be applied throughvarying . In our simulation, the search of is performed from0.1 to 1.0 with a step size of 0.1.Given a physical-level synthesis solution, which consists of

the routing solution integrated with a placement, we call therouting with the placement under an operating condition a phys-ical-level synthesis sample. Note that in the placement problemin [1], a sample is only associated with a placement solution,while in our problem, a sample is associated with a physical-level synthesis solution. Recall that given a large number ofthose physical-level synthesis samples, routing yield is defined


as the ratio of the number of samples not violating any constraintover the total number of samples. The high routing yield is de-sired since this means that the design is good for most operatingconditions. In the physical-level synthesis problem consideringvariation, a routing yield constraint is given, which is between0% and 100%, and one targets to compute a physical-level syn-thesis solution satisfying the routing yield constraint. It is alsoclear that the variation is different from contamination and de-fect. Our problem is formulated as follows.1) Physical-Level Synthesis for Lab-On-a-Chip Consid-

ering Variation, Contamination and Defect: Given an initialplacement solution consisting of a set of modules specifiedby lengths, widths, and variational heights, and the sourcesand destinations, our physical-level synthesis problem aimsto improve the placement solution to be routable, and decidethe transporting route for each droplet from its source to thedestination such that the timing constraint, fluidic constraintand the routing yield constraint are satisfied, while avoiding thedefective and contaminated grids.

B. Multi-Scale Technique for Placement Considering Variation

We first briefly overview themulti-scale variation aware tech-nique for placement proposed in [1] since our technique will beseamlessly integrated to the initial placement solution generatedusing [1]. Recall that [1] only considers variation aware place-ment but not routing.In [1], the placement problem is defined as follows. Given a

set of 3-D modules, each of which is specified by some length,width, and variational height, and a fixed chip area, to decide thephysical locations of the module with minimum overall com-pletion time such that the non-overlapping, resource and sched-uling constraints are satisfied, and the placement yield constraintis also satisfied. Note that placement yield in [1] refers to theratio of the number of placement samples not leading to anyoverlap over the total number of placement samples. This place-ment yield is different from our routing yield. In its proposedtechnique, the lab-on-a-chip placement problem is formulatedas an integer linear programming (ILP) problem. A lattice is laidonto the 3-D space and divides the space to a set of unit grids.The left lower corner of each module will be placed at one andonly one grid, satisfying all the constraints. Each grid can be oc-cupied by no greater than one module. In the ILP in [1], thereare a large number of variables associated with grids, modulesand constraints. Refer to [1] for details of the ILP formulation.Given a large lab-on-a-chip, the ILP may contain too many vari-ables and constraints, which largely degrades the efficiency incomputation [1]. Thus, the multi-scale technique consisting ofgrid coarsening for speedup and fine-scale tuning to improve thecompletion time is proposed.1) Grid Coarsening: In the original ILP, the lower left corner

of each module allows to be placed at any grid, as long as theconstraints are satisfied. This results in a large number of thevariables in ILP which cannot be efficiently solved. Thus, tospeedup ILP solving, the grid coarsening is proposed in [1]. Ingrid coarsening, the grid size is coarsened by a factor of , whichmeans that the modules are only allowed to be placed at the grid

Fig. 6. (a) An example of grid coarsening of -dimension, with . Forsimplicity, the illustration is in 2-D, i.e., and coordinates. (b) A possiblefine-scale tuning solution for (a). The total completion time is reduced.

location with the coordinates of a multiple of . For example,if one sets along -dimension, the modules can be onlyplaced at a coordinate of the multiple of 4 along -dimension.2) Fine-Scale Tuning: Fine-scale tuning is utilized in [1] to

recover the solution quality loss in grid coarsening. Take -di-mension for example. After grid coarsening, the ILP is solvedand a coarsened placement solution can be obtained. The solu-tion quality can be degraded. However, as shown in the exampleof coarsened placement solution in Fig. 6(a), somemodules maybe able to be pushed down to improve solution quality. Thus,a set iterations of tuning is performed. Suppose the lower leftcorner of a module is placed at in -dimension. Define thelocal region of this module to be between andin -dimension, where is an integer and . For example,the local region of module 5 in Fig. 6(a) is between 0 and 4 in-dimension. For the -th iteration, define all the lines at in-dimension the -th front line. In the -th iteration, the moduleswhose lower left corners are placed below are fixed, andthose placed above will search a location with less comple-tion time in their local region while satisfying all constraints.Consider Fig. 6 as an example. In the first iteration, module 1,module 2, module 3, and module 4 are fixed as the coarsenedplacement solution and the other modules will be tuned. Eachfront line will be handled in an iteration, until all front lines arehandled. An improved placement will be obtained. Refer to [1]for details.

III. THE PROPOSED PHYSICAL-LEVEL SYNTHESIS TECHNIQUECONSIDERING VARIATION

An optimization technique for lab-on-a-chip physical-levelsynthesis considering variation, contamination, and defect isproposed. It considers routing variations and is seamlessly inte-grated to the placement technique in [1]. Note that in the phys-ical-level synthesis, the routing and placement largely impacteach other, and our technique performs routing during place-ment optimization. Fig. 7 shows an example that the placementand routing interacts with each other during fine-tuning. Fig. 8gives the flow chart of the algorithm. Basic routability checkis to check whether the grid coarsening placement solution hasspace for routing and satisfies all the constraints for placement.If not, the perturbation will be performed in order to pass thebasic routability check.


Fig. 7. Two different fine-tuned solutions show that placement and routing interacts with each other during fine-tuning procedure. (a) An initial routing andplacement solution. (b) One possible fine-tuned solution. (c) The other possible fine-tuned solution.

Fig. 8. The flow chart of the proposed physical-level synthesis algorithm con-sidering variation.

A. Maze Routing for Lab-On-a-Chip Routing ConsideringContamination and Defect

Maze routing is a standard routing technique in VLSI CAD,and it has also been used for biochip routing such as in the works[15], [24], [25]. Maze routing divides the entire routing spaceinto a set of unit grids, part of which might be blocked or already

Fig. 9. An example to illustrate the defective grid and contaminated grid in2-D, i.e., and coordinates.

occupied by the existing routes, and continues to increase theconcentric circles centering at the source until one circle reachesthe destination [26]. If each grid is associated with a weight, themaze routing is also able to compute a minimum weight route.[25] also utilizes maze routing for lab-on-a-chip routing. How-ever, it does not consider variation, contamination, and defect.In our problem, given a source and a destination, 3-D maze

routing is utilized to compute the route. Each grid in the 3-Dspace is associated with an equal weight unless specified. If thegrid is occupied by a module or an existing route, a large weightwill be then assigned such that no other route passing throughthis grid will be the minimum weight route. A route with theminimum weight among all possible routes will be chosen asthe best/shortest route for transporting the droplet. Note that inour context, when route along the -dimension, the maze routingchooses the route upward but not downward due to that -dimen-sion represents the time.


Fig. 10. Different module variational heights result in different physical-level synthesis samples. A fine–scale tuning solution is shown in Fig. 7(b), which issample 1 of routing and placement. It satisfies the timing constraint and fluidic constraint. (a) Sample 2 violates the fluidic constraint. (b) Sample 3 has no spacefor routing. (c) Sample 4 satisfies the timing constraint and fluidic constraint.

The proposed maze routing based technique can handle thefluidic constraint in the following way. Recall that fluidic con-straint states that the minimum spacing between two droplets isone grid. When a route is chosen to transport the droplet, all thegrids adjacent to the grids on this route will be assigned with alarge weight. It guarantees that these grids will not be chosenany more such that the fluidic constraint is satisfied. The pro-posed technique can also handle the timing constraint. Given thetiming constraint , when routing length in a route is greaterthan , this route will be discarded. As shown in Fig. 3, thereare two routes frommodule 1 to module 2, i.e., the black one andthe gray one. The gray one may violate the timing constraintsince the routing length might be greater than . Thus, thegray one will not be kept.The proposed technique can handle the contamination and

defect. Given a set of defective grids with certain coordinationin the lab-on-a-chip, these grids cannot be used for routing

for all the time. Given a set of contaminated grids with certaincoordinations, these grids need to be disabled for routing fora certain time. For example, a contaminated grid is at ,and the wash time to clear the contamination is , then the grids

cannot be used in therouting. Thus, the proposed technique will assign a large weightto these grids to avoid using these grids. Fig. 9 gives an example,in which the contaminated grid cannot be used in routing forat least 2 time units, and the defective grid cannot be used inrouting at all.

B. Physical-Level Synthesis Considering Variation

Recall that multi-scale optimization technique in [1] onlyconsiders placement. In fine-scale tuning for placement, themodules below the current front line are fixed, and the modulesabove the current front line can explore better placement intheir local regions. The above procedure neglects the routing,and thus the design could be unroutable. Based on the initialplacement solution generated using [1], our synthesis techniqueseamlessly integrates routing to the multi-scale placementoptimization.At a high level, our technique for physical-level synthesis

performs routing in each front line of the fine-scale tuning. Theorder of routes for each pair of modules is determined by the

topological order in the precedence graph. If the fine-scale tuneddesign for -th front line is routable such that all the constraintsare satisfied, the fine-scale tuned solution is taken instead of theoriginal design. Otherwise, this solution will not be taken. Dueto that [1] does not consider routing, it could happen that evenbefore fine-scale tuning, the design is not routable. In this case,some perturbation of the modules will be performed to makeit routable and satisfy all constraints. After processing the lastfront line, the feasible solution is returned as the solution.In detail, the initial coarsened placement is utilized as the

input. The basic routability check is first performed to seewhether it is routable. If not, some perturbation of the moduleswill be performed. In our simulation, the technique tries tomove up some adjacent modules, or moves some adjacentmodules to other unoccupied and non-adjacent space with thesame -dimension. After that, it starts with the first front line.The modules whose lower left corner below the first front lineare fixed as in the initial coarsened solution, and the others willsearch a better placement in their local regions. The routingwill be performed after the search. If the resulting routing cansatisfy the fluidic constraint, timing constraint as well as therouting yield constraint, this solution will be kept. Otherwise,this solution will be discarded. It will then proceed to next frontline, i.e., second front line. The above procedures are iterateduntil all the front lines are processed. A synthesized solutionwith the routing and tuned placement can be obtained, satis-fying all the constraints including the routing yield constraints.The routing yield constraint is checked during fine-scale

tuning to handle variation. To evaluate routing yield, the tech-nique of Latin Hypercube sampling is utilized. Refer to [27] forthe details. Given a physical-level synthesis solution, a set ofmodule variational heights are generated according to Gaussiandistribution. Some variational heights would lead to the failureof the design due to that a grid initially assigned for the routingmay be occupied by the module. Fig. 4 gives an example.When a new solution is obtained after proceeding to -th frontline, the routing yield of this design will be computed. Therouting yield constraint is that, if the routing yield is greaterthan the user defined number, e.g., 99%, this solution is taken,and the algorithm proceeds to next front line. Otherwise, thissolution will be discarded and the previous solution is kept.


TABLE ITHE COMPARISON OF ROUTE WITHOUT V AND ROUTE WITH V. COMPL. TIME REFERS TO THE OVERALL COMPLETION TIME OF THE LAST MODULE IN THESOLUTION OF THE LAB-ON-A-CHIP PLACEMENT AND ROUTING. R. LENGTH IS THE TOTAL ROUTING LENGTH WHICH IS THE TOTAL NUMBER OF GRIDS NEEDEDFOR THE TRANSPORTATION OF DROPLETS IN THIS DESIGN. R. YIELD IS ROUTING YIELD. CPU REFERS TO THE RUNTIME IN SECONDS. COMPL. TIME INCREASE

IS COMPUTED THROUGH COMPARING THE COMPLETION TIME OF ROUTE WITHOUT V AND ROUTE WITH V. R. YIELD IMPR. IS THE ROUTING YIELDIMPROVEMENT COMPUTED THROUGH COMPARING THE ROUTING YIELD OF ROUTE WITHOUT V AND ROUTE WITH V

Fig. 11. (a) One routing solution for vitro3–1 using ROUTE without V. Thedroplets are transported from the sources to the destinations. A pair of sourceand destination, and the corresponding routing are painted by the same color.(b) One routing solution for vitro3–1 using ROUTE with V.

Consequently, after each round of fine-scale tuning, the designcan satisfy the routing yield constraint. Fig. 10 gives an illus-tration. A fine-scale tuning solution is computed from a gridcoarsening solution in Fig. 7(a). Suppose that there are fourphysical-level synthesis samples due to the different modulevariational heights. Two samples violate the constraints, andthus the routing yield will be only 50%, which is less than 99%.Since the routing yield constraint is not satisfied, this fine-tunedsolution will be discarded. Only the solutions satisfying therouting yield constraint will be kept.

IV. SIMULATION RESULTS

In the simulation, the proposed physical synthesis techniqueis implemented in C++, and tested on a Pentium IV machinewith 1.86 GHz CPU and 3 GB main memory. We conduct thesimulation on a set of standard testcases used in [1], [11] wherevitro refers to some clinical diagnostic procedure, i.e., multi-plexed in-vitro diagnostics on human physiological fluids [28].Since there is no previous work considering all of variation, con-tamination, and defect, for comparison a set of simulations areconducted for comparison through skipping some constraints.The techniques considered in the simulation are listed as fol-

lows.• ROUTE with V: the proposed technique considering vari-ation.

• ROUTE without V: the proposed technique withoutrouting yield constraint.

• ROUTE with V, D/C: the proposed technique consideringvariation, contamination, and defect.

TABLE IITHE SIMULATION RESULTS OF PROTEIN DILUTION BIOASSAY. COMPL. TIMEREFERS TO THE OVERALL COMPLETION TIME OF THE LAST MODULE IN THESOLUTION OF THE LAB-ON-A-CHIP PLACEMENT BY GRID COARSENING. R.LENGTH IS THE TOTAL ROUTING LENGTH WHICH IS THE TOTAL NUMBER OFGRIDS NEEDED FOR THE TRANSPORTATION OF DROPLETS IN THIS DESIGN.

R. YIELD IS ROUTING YIELD

In the simulation, Gaussian distribution is utilized for varia-tion distribution. Note that other distributions can also be han-dled in our technique. The in Gaussian distribution is set to

. Thus, is 10% and the variational range is set to 10%of . It coarsens the time dimension by a factor of onfor the first 4 testcases and on for the last 6 testcases,since this setting obtains the best tradeoff between runtime andsolution quality. The simulation results of ROUTE without Vand ROUTE with V are summarized in Table I. The followingobservations can be made.• Without considering variation, the optimization solutionsusing both of ROUTE without V and ROUTE with V areroutable. That is, all the droplets can be transported fromtheir source to destination while satisfying the timing con-straint and fluidic constraint. Refer to Fig. 11 for a routingsolution of vitro3–1 using ROUTEwithout V and a routingsolution using ROUTE with V.

• With considering variation, ROUTE with V is always ableto satisfy all design constraints, including routing yieldconstraint. In contrast, ROUTE without V cannot satisfythe routing yield constraint. For example, the routing yieldimprovement of vitro1–1 is as high as 85.0%.

• The average routing yield improvement of all the testcasesis 51.2%. The designs using ROUTE with V satisfyingrouting yield constraint demonstrates that they are insen-sitive to the variation.

• In terms of overall completion time, compared to ROUTEwithout V, ROUTEwithV computes the solutions with lesscompletion time for vitro1–3 and vitro1–4, while ROUTEwith V computes the solution with more completion timefor the other testcases.

• It can be seen that there is a tradeoff between overall com-pletion time and routing yield. ROUTE without V reducessome completion time in the design but its routing yield


TABLE IIITHE COMPARISON OF ROUTE WITH V AND ROUTE WITH V, D/C. # OF D, C REFERS TO THE NUMBER OF DEFECTIVE GRID AND CONTAMINATED GRID.COMPL. TIME REFERS TO THE OVERALL COMPLETION TIME OF THE LAST MODULE IN THE SOLUTION OF THE LAB-ON-A-CHIP PLACEMENT AND ROUTING.R. LENGTH IS THE TOTAL ROUTING LENGTH WHICH IS THE TOTAL NUMBER OF GRIDS NEEDED FOR THE TRANSPORTATION OF DROPLETS IN THIS DESIGN.R. YIELD IS ROUTING YIELD. VIOLATION PERCENTAGE REFERS TO THE NUMBER OF DEFECTIVE/CONTAMINATED GRIDS USED IN THE ROUTING OVER THE

TOTAL NUMBER OF DEFECTIVE/CONTAMINATED GRIDS

is much worse. Although ROUTE with V may need morecompletion time, the average completion time increase isonly 3.5%, while the average routing yield improvementcan be 51.2%.

• The routing length for the droplet transportation ofROUTE with V is longer than that of ROUTE without V.This is due to that considering the variation, the modulescould have larger distance between each other.

• The runtime of ROUTE with V is similar to ROUTEwithout V.

The proposed algorithm is also conducted on the testcase ofprotein dilution bioassay in [13]. The simulation results are sum-marized as Table II. Both designs without and with consideringvariation have similar total completion time and routing length.However, the design without considering variation only has arouting yield of 5%, and that with considering variation has arouting yield of 100%.To demonstrate that ROUTE with V can handle contamina-

tion and defect in the lab-on-a-chip, we also conduct a set of sim-ulations considering contamination and defect using ROUTEwith V, D/C. A set of five defective grids and five contaminatedgrids are arbitrarily selected among all the grids before simula-tion. Table III summarizes the simulation results. The followingobservations can be made.• The contamination and defect have some impact on theoverall completion time of all the testcases. For example,for the design vitro1–1, the completion time increases to77. This is due to the fact that the defective and contami-nated grids are arbitrarily generated, and the placement ofmodules and routing may need more space to avoid thesegrids. However, some increase of completion time is rea-sonable in order to keep all the modules/operations effec-tive.

• The average violation percentage of ROUTE with V, D/Cis 0%, while that of ROUTE with V is 17.0%. It showsthat most of the routings in ROUTE with V are not validsince the defective/contaminated grids are used. In con-trast, ROUTE with V, D/C avoids using those grids andcan obtain the successful solution.

• The routing yield is as good as the previous designs usingROUTE with V, showing that ROUTE with V, D/C is ableto well handle the contamination and defect.

• Since a few grids cannot be utilized for routing, this resultsin the increase of routing length.

V. CONCLUSION

This work designs a physical-level synthesis flow forlab-on-a-chip which simultaneously considers all of variation,contamination, and defect. It proposes the maze routing based,variation, contamination, and defect aware droplet routingtechnique, which is seamlessly integrated into the placementtechnique in [1]. The simulation results demonstrate that theproposed technique can route the droplets using a small numberof grids considering contamination and defect. It does not useany defective/contaminated grids, while the technique withoutconsidering contamination and defect uses 17.0% of the defec-tive/contaminated grids on average. On the other hand, withoutconsidering variation the routing yield is very small. Withconsidering variation, our routing technique can successfullyroute the droplets for a set of standard testcases while satisfyingthe routing yield constraint with only a little increase of com-pletion time. Compared to that without considering variation,the average routing yield improvement is as high as 51.2%while the average completion time increase is only 3.5%.

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Chen Liao received the Ph.D. degree in electricalengineering from theDepartment of Electrical andComputer Engineering, Michigan TechnologicalUniversity, Houghton, MI, USA, in 2013. She is cur-rently a Senior ASIC Design Engineer with MarvellSemiconductor, Santa Clara, CA, USA. Her researchinterests are in the area of computer-aided design ofVLSI circuits and combinatorial optimizations. Sheserves as Area Editor for the International Journalof Electronics and Communications. She receivedthe Richard Newton Graduate Scholarship from the

Design Automation Conference (DAC) in 2009.

Shiyan Hu (SM’10) received the Ph.D. degreein computer engineering from Texas A&M Uni-versity, College Station, TX, USA, in 2008. Heis currently an Assistant Professor in the Depart-ment of Electrical and Computer Engineering atMichigan Technological University, Houghton, MI,USA, where he serves as the Director of MichiganTech VLSI CAD Research Lab. He was a VisitingProfessor with IBM Austin Research Lab duringSummer 2010.His research interests are primarily in computer-

aided design for VLSI circuits and embedded system for smart home. He haspublished over 50 journal and conference papers. He has served as the AssociateEditor for the International Journal of Electronics and Communications (Else-vier), the Guest Editor for IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICSand ACM Transactions on Embedded Computing Systems, the Technical Pro-gram Committee (TPC) chair for DAC Ph.D. Forum in 2013, the TPC subcom-mittee chairs for DAC 2014 and ICCAD 2011, and the TPC members for anumber of conferences such as DAC, ICCAD, ISPD, ISQED, ISVLSI, SOCC,ICM, and ISCAS.

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