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ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 1
International Technology Roadmap for Semiconductors
2006 ITRS Update/ORTC Product Models Status[Including 2Q06 SIA/SICAS* Industry Technology Capacity Demand Analysis]
For Public 12/04/06 Conference Ambassador Hotel - Hsin Chu, Taiwan
(Draft Rev 2, 11/20/06 – corrections foils #10,11)* Semiconductor Industry Association / Semiconductor Industry Capacity Statistics
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 2
Moore’s Law & MoreMore than Moore: Diversification
Mo
re M
oo
re:
Min
iatu
riza
tio
nM
ore
Mo
ore
: M
inia
turi
zati
on
Combining SoC and SiP: Higher Value SystemsBas
eli
ne
CM
OS
: C
PU
, M
emo
ry,
Lo
gic
BiochipsSensors
ActuatorsHV
PowerAnalog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm...V
130nm
90nm
65nm
45nm
32nm
22nm...V
Information Processing
Digital contentSystem-on-chip
(SoC)
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
Beyond CMOS
2005 ITRS Executive Summary Fig 5
Traditional ORTC Models
Source: 2005 ITRS Document online at: http://www.itrs.net/Links/2005ITRS/Home2005.htm
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 3
ORTC Overview – 2006 Update ITRS - Unchanged• One standard TWG table technology trend header
– 2006 ITRS Update tables continue to use DRAM stagger-contacted M1 as typical industry lithography driver
– Transitioned to product-oriented technology trend drivers and cycles*• ORTC Table 1a,b - MPU/ASIC M1 Half-Pitch Trend
– Stagger-contacted, same as DRAM– 2.5-year Technology Cycle* (.5x/5yrs) – 180nm/2000; 90nm/2005; 45nm/2010(equal DRAM)– Then continue on a 3-year Technology Cycle*, equal to DRAM 2010-2020
• ORTC Table 1a,b - STRJ Flash Poly (Un-contacted dense lines)– 2-year Technology Cycle* (0.5x/4yrs)– 180nm/2000; 130nm/2002; 90nm/2004; 65nm/2006– Then 3-year Technology Cycle* 1 year ahead of DRAM ’06-’20
• ORTC Table 1a,b – MPU/ASIC Printed Gate Length per FEP and Litho TWG ratio relationship to Final Physical Gate Length - 2005 ITRS targets (3-year cycle* after 2005)
• TWG table Product-specific technology trend driver header items are added to individual TWG tables from ORTC Table 1a&b
• Chip Size Models are connected to proposals and historical trends, incl. new Flash Model
– Function Size [Logic Gate; SRAM Cell; Dram Cell; Flash Cell (SLC, MLC)]– Functions/Chip [Flash; DRAM; High Performance (hp) MPU; Cost Perf. (cp) MPU]– Chip Size [hp MPU; cp MPU; DRAM; Flash]
*Note: Cycle = time to 0.5xlinear scaling every two
cycle periods ~ 0.71x/ cycle
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 4
2005 Definition of the Half Pitch - unchanged[No single-product “node” designation; DRAM half-pitch still litho driver; however,
other product technology trends may be drivers on individual TWG tables]
Metal Pitch
Typical DRAM/MPU/ASIC Metal Bit Line
DRAM ½ Pitch = DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Poly
Pitch
Typical flash Un-contacted Poly
FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/2
8-16 Lines
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 5
Production Ramp-up Model and Technology Cycle Timing
Vo
lum
e (P
arts
/Mo
nth
)
1K
10K
100K
Months0-24
1M
10M
100M
Alpha
Tool
12 24-12
Development Production
Beta
Tool
Production
Tool
First
Conf.
Papers
First Two Companies
Reaching Production
Vo
lum
e (W
afer
s/M
on
th)
2
20
200
2K
20K
200K
Source: 2005 ITRS - Exec. Summary Fig 3
Fig 3 Unchanged
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 6
2005 ITRS Flash Poly Half-Pitch Technology: 2.0-year cycle until 1yr ahead of DRAM @65nm/’06
3-Year Technology Cycle2-Year Technology Cycle [’98-’06 ]
Year of Production
Technology -UncontactedPoly H-P (nm)
2003 20052001
65 223245 16
2008
20062002[Actual]
20042000[Actual]
90130180
76107151 5057 13
201520122009 2018
201620132010 2019 2020
2005 ITRS MPU M1 Half-Pitch Technology: 2.5-year cycle; then equal DRAM @45nm/2010
Year of Production
Technology- ContactedM1 H-P (nm)
157 136 119 103 78 68 59 52
201620132010 2019[July’08][July’02] 20052000
201820152012 2020
[130]180 [ 65]90 2232 1645
2008200620032001 2002 2004 2007 2009
2.5-Year Technology Cycle3-2-Yr Cycle] 3-Year Technology Cycle
14
2006 (’05-’20) ITRS Technology Trends DRAM M1 Half-Pitch : 3-year cycle
3-Year Technology Cycle2-Year Technology Cycle [‘98-’04]
Year of Production
Technology - ContactedM1 H-P (nm)
201820152012 2020
201620132010 2019
2003 20052001
65 223245 16
20082006 2009
20072002[Actual]
20042000[Actual]
90130180
80107151 71 57 50 14
All unchanged
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 7
Figure 8 ITRS Product Technology Trends - unchangedFig 7&8 Simplified – Option 1
2005 ITRS Product Technology Trends - Half-Pitch, Gate-Length
1.0
10.0
100.0
1000.0
1995 2000 2005 2010 2015 2020
Year of Production
Pro
du
ct H
alf-
Pit
ch, G
ate-
Len
gth
(n
m)
DRAM M1 1/2 Pitch
MPU M1 1/2 Pitch(2.5-year cycle)
Flash Poly 1/2 Pitch
MPU Gate Length -Printed
MPUGate Length -Physical
MPU M1.71X/2.5YR
Nanotechnology (<100nm) Era Begins -1999
GLpr IS =1.6818 x GLph
2005 - 2020 ITRS Range
MPU & DRAM M1& Flash Poly
.71X/3YR
Flash Poly.71X/2YR
Gate Length.71X/3YR
Before 1998 .71X/3YR
After 1998.71X/2YR
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 8
Fig 4 2005 ITRS Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution
Fea
ture
Siz
e (H
alf
Pitc
h) (m
)
Year
0.01
0.1
1
10Source: SICAS**W.P.C.= Total Worldwide Wafer Production Capacity (Relative Value *)
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2005. The area of each of the production capacity bars corresponds to the relative share of the Total MOS IC production start silicon area for that range of the feature size (y-axis). Data is based upon capacity if fully utilized.
1997 1998 1999 2000 2001 2002 2003 200620052004 2007Source: 2005 ITRS - Exec. Summary Fig 4
W.P.CW.P.CW.P.CW.P.CW.P.CW.P.C W.P.C W.P.C W.P.C >0.7m
0.7-0.4m
0.4-0.3m
0.3- 0.2m
0.2- 0.16m
<0.12m
0.16-.12m
<0.
4m
<0.
4m
<0.
3m
<0.
3m
<0.
2m
<0.
2m
<0.
16m
<0.
16m
<0.
12m
(Fea
ture
Siz
e o
f R
epo
rted
Tec
hn
olo
gy
Cap
acit
y o
f S
ICA
S P
arti
cip
ants
)
3-Year Cycle 3-Year Cycle2-Year Cycle
= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual = 2005 ITRS DRAM Contacted M1 Half-Pitch Target
** Source: The data for the graphical analysis were supplied by the Semiconductor Industry Association (SIA) from their Semiconductor Industry Capacity Statistics (SICAS). The SICAS data is collected from worldwide semiconductor manufacturers (estimated >90% of Total MOS Capacity) and published by the Semiconductor Industry Association (SIA), as of July, 2005. The detailed data are available to the public online at the SIA website, http://www.sia-online.org/pre_stat.cfm .
SIA/SICAS Data**: 1-yr
delay from ITRS Cycle Timing
to 25% of MOS IC Capacity
127nm
180nm
255nm
360nm
510nm
720nm
90nm
ITRSTechnology
Cycle
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 9
MOS Capacity by Dimensions
0.0200.0400.0600.0800.0
1000.01200.01400.01600.01800.0
3Q03
4Q03
1Q04
2Q04
3Q04
4Q04
1Q05
2Q05
3Q05
4Q05
1Q06
2Q06
WSp
W x
1000
>=0.7µ
<0.7µ >=0.4µ
<0.4µ >=0.3µ
<0.3µ >=0.2µ
<0.2µ >=0.16µ
<0.16µ
<0.16µ >=0.12µ
<0.12µ
2-yrs to >20% of Total MOS for 0.71x Technology Reduction Cycle
SICAS 90nm Capacity Tracking Kickoff – 2Q06 Update
Source: SIA/SICAS Report: www.sia-online.org/pre_statistics.cfm
~32% of Total MOS
0.30 to 0.25u to.21u
0.42 to 0.36u to.30u
0.60 to 0.51u to.42u
0.85 to 0.72u to.60u
0.11 to 0.090u to 0.075un
0.15 to 0.13u to.11un-1
0.21 to 0.18u to.15un-2
Next TBD?:20%
1Q07?(2yr Cycle)
1Q08?3yr Cycle
<0.075 to 0.065u to.053u
n+1 [available 2Q07]
0.71x
Technology Demand2-year Cycle
Continues!
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 10
1Q
0719972007
MOS Capacity by Wafer-size
0.0200.0400.0600.0800.0
1000.01200.01400.01600.01800.0
3Q03
4Q03
1Q04
2Q04
3Q04
4Q04
1Q05
2Q05
3Q05
4Q05
1Q06
2Q06
WSpW
x100
0(8
inch e
quiva
lents) < 200mm
200mm
300mm
SICAS 300m Capacity Tracking – 2Q06 Update
300mm/1Q04(3yrs after Intro)
200mm/1Q97SICAS Tracking Begins
(7yrs after Intro)
11 years intro-introWafer Generation
Source: SIA/SICAS Report: www.sia-online.org
2004 –Happy
10th Anniv.SICAS!
11.6%CAGR
2005 20062003 2004 2005 2006
2Q06: 300mm = 25% of Total MOS200mm = 62% of Total MOS
<200mm = 14% of Total MOS
12.0%YoY
93.1%YoY
1Q
97
4Q
971997
Waf
er S
tart
s
p
er W
eek
(1K
)
362.7[44%]
821.4[100%]
277.4[38%]
728.2[100%]
[Total MOS only – 8” Equivalent]
12.8%YoY
30.8%YoY
1Q97-1Q06Total MOS9.1% CAGR
1Q97-1Q06200mm
15.3% CAGR
17.4%Equiv. YoY
(3 Qtrs)
43.0%Equiv. YoY
(3 Qtrs)
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 11
2005 ITRS Product Function Size Trends - Cell Size, Logic Gate(4t) Size
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
2000 2005 2010 2015 2020
Year of Production
Cel
l, L
og
ic G
ate
Siz
e(u
m2
)
DRAM Cell Size (u2)
Flash Cell Size (u2)SLC(NEW)
Flash Eqv.bit Size(u2)MLC(NEW)
MPU SRAM Cell Size(6t)(u2)
MPU Gate Size (4t)(u2)
Note for Flash: SLC = Single-Level-Cell Size
MLC =Multi-Level-Cell
(Electrical Equivalent) Cell Size
2005 - 2020 ITRS Range
Figure 9 ITRS Product Function Size - unchangedFig xx Simplified
(@ 2 MLC bits/physical cell area)
Flash: 4f2 LastDesign Physical AreaFactor Improvement
DRAM: 6f2 LastDesign Area
Factor Improvement
Logic Gate: NODesign Area
Factor Improvement(Only Scaling)
SRAM: GradualDesign Area
Factor Improvement
Flash: (MLC @ 2 bits/cell =
2f2 EquivalentArea Factor)
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 12
2005 ITRS Product Technology Trends Functions/Chip
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020
Year of Production
Pro
duct
Fun
ctio
ns/C
hip
(Gig
a (1
0^9)
- b
its, t
rans
isto
rs )
Flash Bits/Chip (Gbits) Single-Level-Cell(SLC )
Flash Bits/Chip (Gbits) Multi-Level-Cell(MLC)
MPU GTransistors/Chip - high-performance(hp)
MPU GTransistors/Chip - cost-performanc(cp)
DRAM Bits/Chip (Gbits)
Average Industry "Moores Law"
Chip Size Trends – 2005 ITRS Functions/Chip Model - unchanged
Past Future2005 - 2020 ITRS Range
AverageIndustry 1970-2020
“Moore’s Law”2x Functions/chip
Per 2 years
(@Volume Production, Affordable Chip Size**)
** Affordable Production
Chip Size Targets:DRAM, Flash < 145mm2
hp MPU < 310mm2
cp MPU < 140mm2
** Example Chip Size Targets:1.1Gt P07h MPU
@ intro in 2004/620mm2
@ prod in 2007/310mm2
** Example Chip Size Targets:0.39Gt P07c MPU
@ intro in 2004/280mm2
@ prod in 2007/140mm2
MPU ahead or =“Moore’s Law”2x Xstors/chipPer 2 years Thru 2010
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 13
2005 ITRS Product Technology Trends - Functions per Chip
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1995 2000 2005 2010 2015 2020
Year of Production
Pro
du
ct F
un
ctio
ns/
Ch
ip[
Gig
a (1
0^9)
- b
its,
tra
nsi
sto
rs ]
Flash Bits/Chip (Gbits)Single-Level-Cell (SLC )
Flash Bits/Chip (Gbits)Multi-Level-Cell (MLC)
MPU GTransistors/Chip -high-performance (hp)
MPU GTransistors/Chip -cost-performanc (cp)
DRAM Bits/Chip (Gbits)
Average Industry "Moores Law"
2005 - 2020 ITRS Range
AverageIndustry 1970-2020
“Moore’s Law”2x Functions/chip
Per 2 years
Figure 10 ITRS Product Functions per Chip - unchanged
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 14Past Future 2005 - 2020 ITRS Range
2005 Proposal ITRS DRAM Chip Size Model(Rev 1K, 06/23/05)
0
100
200
300
400
500
600
700
1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025
Year of Introduction and Production
(mm
2) DRAM Introduction Chip Size
Sawada Production Chip Size IS
4 chips per Litho Field @ 572mm2 = 143mm2
(22x6.5)
4G 8G 32G 64G16G
Bits/
chip: 128G64M
Bits/
chip:
256M
128G
1G 2G
4G
8G 32G 64G
16G
256G 1T
512M
Prod Cell Area Efficiency (CAE) = 63%-56%
Intro Cell Area Efficiency (CAE) = 73%-75%
90 64 45 22 1632 11 8
5 chips per Litho Field @ 704mm2 = 141mm2
(22x6.4)
WAS/IS: 128180255360
128M
32G
16G
4G
8G
2G
32G
16G
64G2G
8.0 6.011 8.0 8.0 8.0 6.0 6.0 6.06.0DRAM Des.
Factor: 11 6.0 6.0
DRAM
Max Litho Field 2005 ITRS (4x) : 834mm2 (26x32)
2 C
hip
s p
er
Ma
x L
itho
Fie
ld 2
00
5
ITR
S (
4x)
: 4
17
m2
(2
6x
16
)2005:
Chip Size Trends – 2005 ITRS DRAM Model – unchanged
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 15Past Future 2005 - 2020 ITRS Range
2005 Proposal ITRS Flash chip Size (NEW) Model (Allan)(Rev 1K, 06/23/05)
0
100
200
300
400
500
600
700
1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025
Year of Introduction and Production
(mm
2)
Flash SLC Production Chip Size
4 chips per Max Affordable Litho Field @
572mm2 = 143mm2 (22x6.5)
Flash Prod Cell Area Efficiency (CAE) = 67%
Flash Intro Cell Area Efficiency (CAE) =TBD -
no model
5 chips per Max Affordable Litho Field @
704mm2 = 141mm2 (22x6.4)
Flash
Bits/chip: 4G 8G 16G 32G 64G 128G256M 1G64M 2G
16 4.032 8.0 4.0 4.0 4.0 4.0 4.04.0 Flash SLC
Des.Factor: 4.0 4.0
128180255360Flash: 90 64 45 22 1632 11 8WAS/IS: 128180255360
8.0 6.011 8.0 8.0 8.0 6.0 6.0 6.06.011 6.0 6.0
90 64 45 22 1632 11 8
DRAM
HP
DRAM Des.
Factor:
2005:Chip Size Trends – 2005 ITRS Flash Model - unchanged
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 16
Past Future 2005 - 2020 ITRS Range
Chip Size Trends – 2005 ITRS MPU Model - unchanged
0
100
200
300
400
500
600
700
1995 1998 2001 2004 2007 2010 2013 2016 2019 2022 2025
Year of Introduction and Production
(mm
2)
MPU hp Production Chip Size
MPU cp Production Chip Size
MPU hp Introduction Chip Size
MPU cp Introduction Chip Size
DRAM
HP
8G
SRAM Cell Efficiency= 60%Logic Gate Efficiency = 50%
p13c1.5Bt
p16c3.1
p19c p22c
800
Max Litho Field 2005 ITRS (4x): 834mm2 (26x32)
2 C
hips
per
Max
Lith
o F
ield
20
05 IT
RS
(4x
): 41
7m2
(26x
16)
p07h1.1Bt
p10h2.2Bt
p07h
1.1Bt
p16h p19h p22hp10h
2.2Bt
p13h
4.4Bt
p02h276Mt
p00h138Mt
p98h69Mt
p04h552Mt
p10c768Mt
hp MPU = 82% SRAM Transistors, 18% Core Logic Transistors
cp MPU = 58% SRAM Transistors, 42% Core Logic Transistors
p02h
276Mt
p04h
552Mt
26% / 2yrsChip Size Growth
p04c192Mt
p02c96Mt
p00c48Mt
p07c384Mt
p07c384Mt
p10c768Mt
p04c96Mt
p02c96Mt
p00c48Mt
p13c1.5Bt
Affordable hp MPU prod Target: 310mm2
Affordable cp MPU prod Target: 140mm2
90 64 45 22 1632 11 8WAS/IS: 12818025536090 68 45 22 1632 11 8 MPU: 136180255360 [2.5yr Technology Cycle
2000-2010]
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 17
Summary – 2006 Update• DRAM Model stagger-contacted M1 unchanged from 2005 ITRS (3-year
cycle* after 2004).• MPU M1 stagger-contact half-pitch unchanged on a 2.5-year cycle*
through 2010/45nm, then 3-year cycle*.• Flash Model un-contacted poly half-pitch unchanged on 2-year cycle* to
1 year ahead of DRAM (contacted) in 2006, then 3-year cycle*.• Printed MPU/ASIC Gate Length is set by FEP and Litho TWGs ratio
agreement, but Physical GL targets unchanged and on 3-year cycle* beginning 2005.
• Industry Technology Capacity (SICAS) [updated to 2Q06 published status] continues on a on 2-year cycle rate at the leading edge.
• Total MOS Capacity is growing ~12% CAGR (SICAS), and 300mm Capacity Demand has ramped to 25% of Total MOS.
• Historical unchanged chip size models “connected” to Product scaling rate models, and include design factors, function size, and array efficiency targets
• The average of the industry product “Moore’s Law” is met or exceeded by the ITRS Memory Product Model targets throughout 2005-2020 ITRS timeframe - unchanged
[* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 18
Backup
Note: ITRS Table Colorization Code Referenceunchanged:
Manufacturable solutions exist, and are being optimized
Manufacturable solutions are known Interim solutions are known
Manufacturable solutions are NOT known
Source: 2005 ITRS Documents online at: http://www.itrs.net/Links/2005ITRS/Home2005.htm
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 19
2006 ITRS Update - Overall Roadmap Technology CharacteristicsSummary [page 1 of 2]
The International Technology Roadmap for Semiconductors (ITRS) Overall Roadmap Technology Characteristics (ORTC) section provides both originating guidance from ORTC Product Models and also consolidates items from other ITRS Technology Working Group (TWG) tables.Table 1a-h Product Generations (DRAM, Flash, MPU/ASIC) and Chip Size Model Technology Trends —There are no changes from the 2005 ORTC Technology Trend and Product Models, and there are also no changes to the 2005 Product Performance Models provided by the Design TWG. As a result, the ORTC Tables 1a-i, which are sourced from those models, remain unchanged. There are some corrections made to the line item labels: 1) various cell area and transistor area labels, which were incorrectly labeled as “mm2” in the 2005 tables, instead of “um2”; and 2) Flash Memory bits per cm2 labeled “Gbits/cm2” (Giga-bits/ cm2) rather than “Bits/cm2.” The remaining changes to ORTC tables for the 2006 Update are derived from corresponding changes to TWG tables, which are used as the various source line items for consolidation in the ORTC. A review of these TWG-related ORTC Tables is included below.Table 2a&b Lithographic-Field and Wafer-Size Trends —Lithography field size trends are unchanged. Wafer generation targets (450mm target to begin in 2012 on 11-year cycle) remain unchanged by the International Roadmap Committee (IRC). It is important to note that dialogue is underway between semiconductor manufacturers and suppliers to assess standards and productivity improvement options on 300mm and 450mm generations. Economic analysis of option scenarios is also underway to examine the required R&D cost, benefits, return-on-investment, and funding mechanism analysis and proposals.Table 3a&b Performance of Packaged Chips: Number of Pads and Pins —Internal chip pad counts for both I/O and power and ground remain unchanged (2:1 ratio I/O-to-power/ground for high-performance MPU; 1:1 ratio for high-performance ASIC). After assessment of the progress in the back-end assembly and packaging industry, the Assembly and Packaging (A&P) TWG increased their numerical targets and trends for the maximum pin counts, increasing pressure on future packaging costs. Table 4a&b Performance and Package Chips: Pads, Cost —The A&P TWG increased the area array flip chip pad spacing targets by 10–20%. The two-row staggered-pitch targets have increased 10–20% in the near termand the three-row staggered-pitch targets have increased 10–50% in the near term. Both pitch targets remain unchanged in the long term. Cost-per-pin targetsare adjusted by the A&P TWG, to reflect estimates and response to cost challenges.
ITRS Winter Conference 2006 The Ambassador Hotel Hsin Chu Taiwan 20
2006 ITRS Update - Overall Roadmap Technology CharacteristicsSummary [continued page 2 of 2]
Table 4c&d Performance and Package Chips: Frequency On-chip Wiring Levels —The A&P TWG adjusted the chip-to-board (off-chip) frequency targets in the 2011–2020 range to remain below the Design/Process Integration (PIDS) targets for on-chip frequency. The Design/PIDS targets for on-chip frequency remain unchanged in the 2006 Update. The Interconnect TWG leaves the number of on-chip wiring levels unchanged.Table 5a&b Electrical Defects —The MPU and DRAM defect targets are adjusted by the Yield Enhancement TWG to reflect their new 2006 Update models and trends, in which both random defects/cm2 and the number of mask levels have leveled off through 2020 at smaller long range targets.Table 6a&b Power Supply and Power Dissipation —There are no changes to the PIDS TWG MPU and DRAM targets for voltage. The A&P TWG kept the maximum power per square centimeter targets unchanged through 2018. The 2019 and 2020 targets, which increased in the 2005 table, are constant in the update table. The maximum Watts (calculated by the ORTC table for specific product maximum production start chip sizes) are also now constant targets in 2019 and 2020.Table 7a&b Cost —The “tops-down” semiconductor market driver models for cost-per-function remain unchanged for the the 2006 Update. The Cost table targets for both memory and logic represent the need to preserve the historical economic semiconductor device productivity trend for continuous reduction of the cost-per-function by -29% compound annual reduction rate (CARR) throughout the roadmap timeframe. Preserving this cost-per-function productivity trend in view of increasing packaging costs, plus the slowing of product function densities due to slower technology cycles (three-year versus two-year) and design factor improvements, represent the over-arching economic grand challenge for the industry.