ISWS 2003ISWS 2003

International SpaceWire Seminar (ISWS 2003)4-5 November 2003, ESTEC Noordwijk, the Netherlands

Tatiana Solokhina (1) , Jaroslav Petrichkovich(1), Alexander Glushkov(1), Yuriy Alexandrov(1), Vladimir Goussev(1), Yuriy Sheynin(2), Sergey Gorbachev(2), Elena Suvorova(2)

(1) “ELVEES” Russian State R&D Center of microelectronicsPO box 19,Technopark,124460, Moscow, Russia

E-mail: main@elvees.ru

(2) “Microprocessing Technologies”PO box 84, Glavpochtamt, 190 000 St. Petersburg, Russia

E-mail:sheynin@online.ru

MCFlight™MCFlight™SOC � BASED CHIPSET WITH SPACEWIRE

LINKS FOR AEROSPACE APPLICATIONS

MiT

�ELVEES� R&D Microelectronics Center profile:

ISWS 2003ISWS 2003

• was created in 1990 as a part of major in USSA space electronics corporation ELAS;

•in 1974 - the first in the USSA CMOS chip;

• more than 400 successfully developed chips;

•SOC&embedded systems& security

CONTENTS

!! General onGeneral on--board equipment architecture board equipment architecture -- integrated integrated architecture systems architecture systems

!! SpaceWire based MCFlightSpaceWire based MCFlight�� chipset chipset !! ELVEESELVEES��s s ��System System -- On On -- a Chipa Chip�� (SOC) (SOC) ��based open based open

design technology design technology ��MultiCorEMultiCorE��!! Dual Processors single chip Digital Signal Processors Dual Processors single chip Digital Signal Processors

(DSC(DSC--RISCRISC--Core+DSPCore) Core+DSPCore) �� ��MultiCore_xxRMultiCore_xxR��chips chips !! DDC/DUC with buildDDC/DUC with build--in ADC/DAC chips for prein ADC/DAC chips for pre--

processing processing �� ��MultiFlex_xxRMultiFlex_xxR�� Chips Chips !! Tools Tools �� ��MCStudioMCStudio��!! MCM&Unimodules (PC104plus) on Mflight Chips MCM&Unimodules (PC104plus) on Mflight Chips !! MCFlight applicationsMCFlight applications

ISWS 2003ISWS 2003

MiT

Distributed Integrated Modular Architecture for Spacecraft On-board Systems

Analogue S ignal P re-p rocessing Un its

ISDS In teg rated S ignal and Data

P rocessing System

ISDS M ultiprocessor node

M u ltiC ore_ xx(s) (data&signal p rocessin g),

M em o ry , N IC (s)

Sensor Fields (SF), E ffector�s Fields (EF)

DAC

AD

C

Spac

eWire

lin

ks

H etero-

d yne C IC , FIR

filters

M F lex-xxR (s)

A n ten na

Array

ADC

D

AC

Spac

eWire

lin

ks

E ffectors

PSS HDS P rogram m ab le Switch ing

System for H igh-Rate D ig ital S ignals

P rogram m ab le Switches

for SpaceW ire links (M CRouter-xxR)

Sam pled Signals D ata Tim e M arkers

High-rate serial SpaceW ire links H igh-rate serial

SpaceW ire links

SS pp aacc ee WW iirree P acket Routing Switches

SS pp aacc ee WW iirree Packet Routing Switches

SS pp aacceeWW iirree Packet Routing Sw itches ((MM CC RR oouu tteerr--xxxxRR ))

ISDS M ultiprocessor node

M ultiC ore_ xx(s) (data&signal p rocessin g),

M em o ry , N IC (s)

ISDS M ultiprocessor node M ultiC ore_xxR (s)

(data& signal processing), M emory, N IC (s)

High-rate serial SpaceW ire links

SW C tr-xxR

Sens ors ASP

ISWS 2003ISWS 2003MiT

The MCFlight� chipset *)

Scalable and flexible high performance Serial Communications SpaceWire Controller / Remote-User-Interface ASIC with SpW Links, 3Q2004 **)

" SWCorE-xxR

Multichannel (16 �channel for 1st realization) Routing switch chip with SpW, 4Q2004 **)

" MCRouter-xxR

SDR based DDC/DUC monochip series with SpW Links and built-in ADC/DAC (in plans), 2Q2004 **)

" MultiFlex (MFlex-xxR�)

Dual processor (RISC&DSP cores) mooched series of scalable and flexible DSC (Digital Signal Controllers) with SpW Links , 3- 4Q2003 **)

" MultiCore (MC - xxR�)

Functional purposeChips type

ISWS 2003ISWS 2003

*) radiation tolerant (in plans), 0.25µ **) silicon prototypingsilicon prototyping without radiation without radiation toleranttolerant

MiT

Applications

AlgorithmsSOC

DESIGNTECHNOLOGYSoftware Tools

ApplicationSoftware

TEST Chips examples

Architecture

IP-CORES LIBRARY

6-9 MONTHLY design flow

�MultiCorE�� Platform

SOFT HARD

ISWS 2003ISWS 2003

Openness, scalability and flexibility 6-9 month's ELVEESs ASIC design flow for SOC integration in Chips Multiple processors on the chip (RISC + DSP=DSC �Digital Signal Controller)Improved system performance for Digital Signal Controllers (tens GOPs, GFLOPs)SW/HW ASIC co - verification on CAD facilities and FPGA prototyping Reduced Chip&System Projects development cost and time to market : 3-5 timesPowerful Tools - MultiCorE Studio (MCStudio�)

What are the basic features of the �MultiCorE�� platform?:

ISWS 2003

Design Kit for technologyIP-cores topology

Design Kit for technologyIP-cores topology

IP-Cores Tlf ModelIP-Cores Tlf Model

IP-CORES Tlf, Lib modelsIP-CORES Tlf, Lib models

CUSTOMER: THE PROJECT specifications

CUSTOMER: THE PROJECT specifications

Verilog net list. Restrictions on the project. Blocks accommodation

Verilog net list. Restrictions on the project. Blocks accommodation

Behavioral models in C and Verilog languages

Behavioral models in C and Verilog languages

Modeling & generation of tests of Chip & FPGA-prototype

Modeling & generation of tests of Chip & FPGA-prototype

RTL-model, synthesis, the static time analysis

RTL-model, synthesis, the static time analysis

1-3rd

month1-3rd

month

1-3rd

month1-3rd

month

Verilog-net list Modelingwith SDF

Verilog-net list Modelingwith SDF

3rd month3rd month

4 � 5the

month4 � 5the

month

6th month6th month

Verilog RTL-modelXilinx - prototype creation

Verilog RTL-modelXilinx - prototype creation

Chips FPGA �prototypingChips FPGA �prototyping

Place & Route with DSM-EffectsPlace & Route with DSM-Effects

Formal verification.Check of physical / electric rules

Formal verification.Check of physical / electric rules GDSII Generation for

Russian or foreign FOUNDRYGDSII Generation for

Russian or foreign FOUNDRY

Chips floor planningChips floor planning

IP-Cores С, Verilog modelsIP-Cores С, Verilog models

ELVEES’s PARTNER or FOUNDRY

6-9 MONTHLY ELVEESs SOC DESIGN FLOW

ISWS 2003

уу

2003

МС_11Т

МС_12S 80 МHz

уу МС_11XX

уу МС_11XX

уу МС_11XX АDC

2004 2005

МС_12F 160 МHz МС_12B

80 МHz, 2Mb

МС_12F 160 МHz

PER

FOM

AN

CE

/ SY

STE

M N

TEG

RA

TIO

N DSC mini-configurations

МC_11XX and MC_12XX

Mass production

In plansTest chip

!System integration (multiprocessors, SIMD/MIMD)!Productivity on the float & fixed point!Volume of the internal memory!Presence built - in ADC/DAC, !special cores etc.

2003

МС_24S 100 МHz

МС_02F 200 МHz,

4DSP

2004 2005

МС_24F 200 МHz, 2DSP

2Mb, SW

МС_24R 80 МHz, SW

МСF_24 MC+Mflex,

МС_24RS 80 МHz, 2DSP

уу МС_01F 200 МHz,

2Mb

МС_02D 400 МHz,

4DSP

уу МС_01D 400 МHz,

4DSP уу МС_01S

200 МHz, 2Mb

PER

FOM

AN

CE

/ SY

STEM

IN

TEG

RA

TIO

N

DSC midi-configurations МC_24XX, MC_01XX, MC_02XX

PER

FOM

AN

CE

/ SY

STE

M I

NT

EG

RA

TIO

N

2003 2004 2005

DSC maxi-configurations МC_03 and МC_04

уу МС_03хх 400 МHz, 4 МС_01

уу МС_03D 400 MHz, 4 МС_01

МС_04xx 400 MHz,

4 MC02

МС_04D 400 МHz, 4 MC02

The project

DSC MC_xx series: MС_11/12/24/01/02/MFlex/MCF-xx� MC -xxR

ISWS 2003

MultiCore-11T. DSC mini-configurations with the fixed point for built-in applications (test chip - December 2002)

MultiCore-24. 2SIMD- configurations

DSC with the amplified fixed point for

built in applications (Test chip � Nov. 2003)

10M transistors &0.25-mkm &9.7*9.7 mm*mm

In a series - 1Q2004.:600MFlOPs/12800MOPs*1b/3600MOPs*8b/1600MOPs*16b/1000MOPs*32b

10M trans.&0.25-mkm& 9.7*9.7 mm*mmIn a series –1Q2004.:300MFlOPs/6400MOPs&1b/1800MOPs&8b/800MOPs&16b/500MOPs&32b

2.5M transistors & 0. 56 -mkm & 9.6*9.6 mm*mm:400MOPs*8b/150MOPs*16b/50MOPs*32b

MultiCore-12. Mini-configurations

DSC, float/fixed point for micro

miniature precision embedded

applications (Test chip-July 2003)

On the basis of MultiCore SoC technology "ELVEES" develops over 10 projects of modern complex multiprocessors monochips simultaneously (also MCFlight chipset with Space Wire Links). Only in 2003 will be developed and made 3 test MultiCore chips: MC-11/12/24 (series in 1Q2004)

ISWS 2003

““MultiCorEMultiCorE™™”” IP Cores library IP Cores library

!Set of similar MIPS32 architecture ELVEES�s RISC - cores((with MAC, without TLB, with FPU, rad hard - RISCorE_xxR™, etceteras)

!Set of 12 float/fixed SIMD scalable ELVEES�s DSP � cores(ELcore_11™/ELcore_12™/ ELcore_13™/ ELcore_14™ , etceteras)

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!Space Wire controller core (SWCorE�)

!Special cores: correlation Core for GPS/GLONASS navigation , DWT, DCT, CORDIC, Viterbi, MP3, special reconfigurable & scalable “ MultiFlex™” cores, Switch Matrix Cores, DAC, ADC…

! Peripherals Cores: PCI , USB, UART, I2C, DMA, MPORT…

SpaceWire link controller core SpaceWire link controller core (SWCorE�)(SWCorE�)

LVDS

Input Input BuffersBuffers

Output Output BufferBuffer

10

10 DMADMA(4 (4

channels)channels)32

32

ReceiverReceiverUnitUnit

TransmitterTransmitterUnitUnit

Target AMBA AHB

interface

Master Master AMBA AMBA AHB AHB

interfaceinterface32

32

Control UnitControl UnitProgrammable Programmable ClockClock

22--400 400 MHzMHz

AMBA

AHB

DS-macro

cell

SWCorESWCorE

ISWS 2003ISWS 2003

�MultiCorE�� IP cores librarySpace Wire controller core (SWCorE�)

MiT

FPGA –prototyping – 4Q2003 without PLL&LVDS, will be built-in the test Multiflex chip at 1Q2004 with PLL&LVDS

MPEG2 for DTV AUDIO INTERNET CHIP MFlex � DDC/DUC Multistandard transceiver

3D Graphic chip -MGraphCommunication modemChip -МultiСom

RISCore_xx

GPS/GLONASS/COM Cores

RISCore_xx

OpenGL -Cores

System Cores: PLL, DMA, Timer, OnCD

RISCore_xx

CORRELATORCore

RAM,ROM, CASH, FIFO

Peripheral Cores

RISCore_xx

DSP

ADC/DAC

RISCore_xx

Filters Cores

GPS/GLONASS - receiverChip with SMS function

Peripheral Cores Peripheral Cores

Peripheral Cores Peripheral Cores

System Cores: PLL, DMA, Timer, OnCD

System Cores: PLL, DMA, Timer, OnCD

RAM,ROM, CASH, FIFO RAM,ROM, CASH, FIFO

RAM, ROM, CASH, FIFO RAM, ROM, CASH, FIFORAM,ROM, CASH, FIFO

System Cores: PLL,DMA, Timer, OnCD ADC/DAC

System Cores: PLL,DMA, Timer, OnCD

System Cores: PLL, DMA, Timer, OnCD

RISCore_xx Video Cores

Peripheral Cores

RAM, ROM, CASH, FIFO

SOCSOC EXAMPLES ON THE BASIS OF THE EXAMPLES ON THE BASIS OF THE �MultiCorE� PLATFORM�MultiCorE� PLATFORM

ISWS 2003ISWS 2003

�MultiCorE�� RISC & DSP IP � cores parameters (preliminary):

~2.5 mm²~3.5 mm²Die DSP- Core Area (max. config. , without memory)

1680/33601200/2400MFLOP/Sec@32-bit (IEEE754), ~4SIMD:ELcore_14�/ ELcore_14F�/

0.560.4MFLOP/Sec@48-bit (32E16, Extended Floating Point ), ELcore_14F�, ~4SIMD:

4.53.2GOP/Sec@32-bit Elcore_14F�,~4SIMD:

96.4GOP/Sec@16-bit Elcore_14F�,~4SIMD:

20.214.4GOP/Sec@8-bit Elcore_14F�,~4SIMD:

71.751.2GOP/Sec@1-bit Elcore_14F�,~4SIMD

140 MHz100 MHzClock Speed for RISCore_xx/ Floating Point/ Fixed Point DSP Core (ELcore_14�),1Q2004

280 MHz200 MHzClock Speed for RISCore_xx/ Floating Point/Fixed Point fast DSP Core (ELcore_14F�), 2-3 Q2004

0.18 µm/1.8 V 0.25 µm/2.5 V Process / Voltage

ISWS 2003ISWS 2003

ISWS 2003ISWS 2003

MCFlight™. MultiCore (MC - xxR�) DSC �System �on �Chip� block-diagram.

M

Links

N

JTAG

Flash SRAM

SDRAM IO

SpaceWire interface

Serial interfaces

AMBA AHB CPU

(RISCorE)

AsymmetricSwitch with

ABMA AHB port interfaces

UART TIMERS Interrupt controller

On chip debugger (OnCD)

Link DMA

Serial port

DMA

SWCorE DMA

DSP (ELcore)

Dual-port RAM

External Memory

DMA

Design rule � CMOS ASIC, 0.25µµµµ & 3.3V (2.5V for core)Clock frequency � ~ 70 MHz (for the nominal temperature and voltage)On-Chip Memory: ~2MbExternal memory (managed via memory port) � up to 4GbytesProgrammable 32-bit interval timerExternal ports and buses: 3- 6 SpaceWire Links; Four ADI SHARC-compatible byte Links /GPIO, Two ADI SHARC-compatible Serial Ports (SPORTS ), UART port, Memory port � External Port for Interfacing to Off-Chip Memory & Peripherals, SDRAM / SRAM / DRAM / Flash ROM �Clueless� System Design, 64-bit data port, 32-bit address port. JTAG Test Access and debug port (IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture). 16-channel DMAPower consumption (3.3V) ~ no more than 2.0 W. Low power dissipation in the idle mode

ISWS 2003ISWS 2003

Kew features of the MultiCore DSC MC - xxR� (rad hard, preliminary):

MAC op./1 cycle• 64• 4• 4• 2• 2

Peak performance (for formats):• fixed point, 1b (MAC: 1*1+32)• fixed point,8b(complex MAC(8+j8)*(8+j8)+32/16)• fixed point, 16b (MAC: 16*16+32)• fixed point, 32b (MAC: 32*32+64)• Floating point (IEEE754) - (MAC: 32*32+32)

Arithmetic op. /1 cycle:• 128• 36• 16• 9• 6• ~0.4

Peak performance (for formats):• fixed point, 1b • fixed point, 8b • fixed point, 16b • fixed point, 32b • Floating point (IEEE754)• Floating point extended (32E16)

• 8/16/32• 24E8 (IEEE 754)• 32E16

Processing data formats:• Fixed point (hardware support)• Floating point (hardware support)• Floating point extended (HW/SW support)

ISWS 2003ISWS 2003

Some MultiCore (MC - xxR�) peak performance characteristics

Dual cores Digital Signal Controller (DSC) MultiCore(R&D Center ELVEES) vs. ADSP- 21160N

(ADI)

47 ns83 ns

46 ns80 ns

66 ns115 ns

Matrix Multiply:[3x3]*[3x1][4x4]*[4x1]

21 ns20 ns29 nsIIR Filter (per biquad section)

5.2 ns5 ns 7.2 nsFIR Filter (per tap)

190 MMAC/s200 MMAC/s140 MMAC/sConvolution (MAC operation)

97 mcs 106 mcs151 mcs FFT-1024, complex (radix 4)

570 MFLOP/s 600 MFLOP/s420 MFLOP/sPeak performance

ADSP- 21160N &95 MHz clock

0.18-µm/1.8V core(Not rad hard)

MultiCore &100 MHz

0.25-µm/2.5V core (Not rad hard)

MultiCore-xxR &70 MHz

0.25-µm/2.5V core (Rad hard)

Float point operations,

IEEE 754

ISWS 2003ISWS 2003

MCFlight™.MultiFlex (MFlex-xxR�)

MultiFlex (MFlex-xxR�) chips family is a series of single or multi-channel digital down and up converters with scalable architecture

Multi-standard transceiver Chip in ELVEES's MCFlight� family of customizable SOC chips with SpaceWire links and the interface compatibility with DSP chips

The application of MultiFLEX gives a great reduction of the analog part complexity in pre-processing for optical and antenna arrays applications

To

base

band

pro

cess

ing

ADC

ADC

I

Q

IF 0-100МГц BB 0-10МГцRF>>100MHz

Traditional analog receiver

To

base

band

pro

cess

ing

ADC

I

Q

IF 0-100МГц BB 0-10МГц

Digital receiver

RF >>100MHz

N

DDC

� High accuracy tuning• High sensitivity to the temperature and component parameters• Non-linear distortions• Hard to build filters with rejection below -60Db and reconfigurable filters

� No tuning• None-sensible to the temperature and component parameters• Simple implementation of programmable filters with rejection below �100Db• High accuracy of heterodyne phase and frequency setting

MCFlight�. MultiFlex (MFlex-xxR�) - DDC (digital down converter) for Soft Radio

18

NCO

MX

ADC12

16

ADC12

ADC12

16

ADC12

1-64

CIC2

1-32

CIC4-6

1-16

FIR32

1-16

FIR6416

MX

FIFONCO1-64

CIC2

1-32

CIC4-6

1-16

FIR32

1-16

FIR6416

NCO1-64

CIC2

1-32

CIC4-6

1-16

FIR32

1-16

FIR6416

NCO1-64

CIC2

1-32

CIC4-6

1-16

FIR32

1-16

FIR6416

4/8 bitLINK

16/32 bitPPORT

SPI

cont

rol

16

16

18

18

18

20

20

20

20

20

20

20

20

SpWLINK

ISWS 2003ISWS 2003

MF01 Four channel digital receiver

16/32 bit parallel port, serial port, SpaceWire port Configuration and control interface:

16/32 bit parallel port, 4/8 bit link port, SpaceWire port Output data interface:

2.5MS/s for each of four channel, 10MS/s combining all four channels in one

Output rate for 96 FIR filter:

32 and 64 TAPs of 1-16 decimation rate each Two stage FIR decimation and filtering:

CIC2 and CIC4-6 Two stage CIC decimation:

0.015°°°° / 0.015HzNCO phase and frequency accuracy:

~2000/GOPsEffective performance, MMAC/s/GOPs/

80Clock frequency, MHz

80/35 Input sample rate (external/internal ADC)

>105Dynamic range, Db

18Internal datawidht, bits

4 x12bit, 20MS/s Embedded ADC

4/1, Real or complex source signal on intermediate frequency or Baseband

Number of DDC channels (narrow/wide)

MF01 featuresISWS 2003ISWS 2003

nonenonenone4Embedded ADC

~2000

2,5

80

64 (96) TAPs

32 TAPsCIC2+CIC4-6

>100

4

4

MF01

~2000~1200260Effective performance, MMAC

2,51,251Throughput for 64-TAP channel filter , MS/s

808065Clock frequency, MHz

63(84) TAPs160 TAPs256 TAPsChannel FIR filter

21 TAPsnoneNoneFIR-decimatorCIC4CIC2+CIC5CIC2+CIC5CIC-decimation

>100>100>100NCO SFDR, Db

321Number of 16-bit inputs

441Number of channels

GC4016AD6634AD6620

ISWS 2003ISWS 2003

MF01(ELVEES) vs. others DDC (ADI&TI)

PROJECT

Project manager Editor Compilers Debugger Analizer

Simulator Connection program host/target

Connection program host/target

Host cross-system

Software execution environment

Development tools

Debugger tools Evolution boardEvolution board

MCFlight™ Software Development & Debugger Tools

MultiCore Composer Studio (MCStudio™)

MultiCore Composer Studio (MCStudio™)

ISWS 2003ISWS 2003

Projects Window

Editor Window with Program

Source

Disassembler Window

Memory Window

Locals WindowRISC-core Registry Window

Executed RISC commands

MCFlight™.Software Development Interface example with open project Windows

ISWS 2003ISWS 2003

MCFlight™ Cores&Chipsprototyping and verification technology

2Q2003. PCI Centaurus� modulemodule also as a part of Software as a part of Software Development Kit for Mflight chipsetDevelopment Kit for Mflight chipset

ISWS 2003ISWS 2003

MCFlight™.Software Development Kit (ver.2003)

DSC Evaluation module:

OS LINUX, RTOS, OnCD. JTAGDSC Evaluation module:

OS LINUX, RTOS, OnCD. JTAG

Software Development Kit :

Centaurus Module, OS LINUX, JTAG tools

Software Development Kit :

Centaurus Module, OS LINUX, JTAG tools

ISWS 2003ISWS 2003

1st

LEVEL -MULTICORE SOC (with SpW)

2nd LEVEL � Micro Modul SALUT™ (Multi Chip Micro Modul (MCM) with non-packaged memory chips assembling: 60x40mm*mm, DSC MultiCore test monochip (RISC Core+Float/fixed DSP Core)+512Mb SDRAM +64Mb FLASH). Different kinds of modules with SpW links (with Multiflex chips, SpW Controllers et.)

3rd LEVEL -Unimoduls™

3D stack extended Embedded PC104/Plus boards) – with 2 SALUT MCMs

3 LEVELS of " MCFlight™” utilization for custom specified aerospace systems (with SpW links in 2004-2005):

ISWS 2003ISWS 2003

MCFlight™. On-board satellite applications ( in plans)

!On-board functional control!Sensor data processing (including optical/radar), enhancement, compression.!Satellite’s telecommunication: radio modems, soft radio,antenna array digital beam forming for on-board satellite relay

MiT ISWS 2003ISWS 2003

MCxxR

CPU DSP

MEM SWCorE5

SWCorE0 MCxxR

MCxxR

Router

RouterMCxxR

ADC

DAC DS

SW

Cor

E �

RT

RT

��� �

10 м, 400 Mbps

Space Wire link

RT

ISWS 2003ISWS 2003MCFlight�. On-board satellite functional control with adaptive signal processing based on DSC chips (float data format processing & ELVEESs Mflight adaptive algorithms Library)

MCFlight�. ELVEES�s MCFlight chips based project for small satellite (200kg) with operative ecological on-board radar

ISWS 2003ISWS 2003

1

2

3

Operating of the small satellite with on-board high resolution SAR. 1 - radar survey; 2 - data transmission to the ground terminal; 3 battery recharge

MCFlight based onboard processor for small satellite high resolution SAR (Synthetic Aperture Radar)

Weight (including SAR antenna) - 250 kg Linear resolution - 3 meters (grid step 2.5 m)Frame dimensions - 10 km x 10 km Looks number (averaging) - 4Frame survey period - 30 secondsProcessor performance - 8 GOPs Number of MCxxR chips - 8Data compression ratio for downlink -min 30 timesDiameter of ground reception station antenna - 1 meter (may be mobile or consumer)Purpose of system: detailed radar images of natural and artificial origin objects for periodic ecological monitoring

RF1 MF_1 Buff1-1/2INPUT

SpaceWire

SWITCH

MCxxR_1OUTPU

T

SpaceWire

SWITCH

Buff1-1/2 MF_1 RF1

RFi MF_i Buff2-1/2

RF91

MF_23

Buff61-1/2

MCxxR_i

MCxxR_25

Buff2-1/2 MF_i RFi

Buff61-1/2 MF_23

RF91

3,5 MHz x 12b 3,5 MHz x 12b

DDC 16 x 2B 16 x 2B DUC

MCFlight�. Example of soft radio, antenna array digital beam forming for on-board satellite relay

ISWS 2003ISWS 2003

System use all types of Mflight Chips: •Mflex with ADC/DAC & SpW – for preprocessing,•SpW Switch chips,•DSC chips –for data processing

Conclusions

Both "ELVEESs MCFlight technology on the “System – on –chip level”"with ELVEESs MCM and 3D PC104Plus Unimodul "together with ESA Space Wire approach on the top system level can apply really scalable and customizable Distributed Integrated Modular Architecture for Spacecraft On-board Systems, as example, for the telecommunications

Thank for Your attention!Thank for Your attention!

“ELVEES” Russian State R&D Center of microelectronicsPO box 19,Technopark,124460, Moscow, RussiaE-mail: main@elvees.ru

(2) “Microprocessing Technologies”PO box 84, Glavpochtamt, 190 000 St. Petersburg, RussiaE-mail:sheynin@online.ru