Technical University of Denmark

Ørsted • DTU Automation

Project: SICAM - SIngle Conversion stage AMplifier

EFP-project no. 1273/02-0001

Isolated PDM and PWM DC-AC SICAMsInternal report Nr.3/03

Petar Ljusev

MSc., Ph.D. student

Supervisors:

• Michael A.E. Andersen, Technical University of Denmark

• Lars M. Fenger, Bang & Olufsen ICEpower a/s

May-July 2003Revised: March 2004

Project is funded under the grant of

Danish Energy Agency

Project partner and co-sponsor:

B&O ICEpower a/s

Isolated PDM and PWM DC-AC SICAMs

Petar Ljusev, MSc., Ph.D. student, Ørsted • DTU Automatione-mail: pl@oersted.dtu.dk

Abstract

In this report a class of isolated PDM and PWM DC-AC SICAMs is described, whichintroduce the audio reference only in the output stage. AC-DC power supply is implemented in itssimplest form: diode rectifier followed by a medium-size charge-storage capacitor. Isolation fromthe AC mains is achieved using a high frequency (HF) transformer, receiving the HF voltage pulsesfrom the input ”inverter” stage and transferring them to the output ”rectifier+inverter” stage, whichcan use either PDM or PWM. The latter stage is then interfaced to the load using an output low-pass filter. Each of the dedicated stages is discussed in detail. Measurements on the master/slavePWM DC-AC SICAM prototype are presented to help benchmarking the performance of this classof SICAMs and identify the advantages and drawbacks.

1 Introduction

DC-AC conversion principles are well established and investigated in the power electronicsfield [1], [2], and for use in audio technology there are also some very good references concerningclass D converters [3]. However, introducing isolation in the DC-AC converter itself and not inthe power supply represents a real challenge, and some simplifications concerning the power supplystructure as well as improved efficiency of the overall system are to be expected. This makes thisclass of DC-AC converters especially appealing for use in a SICAM.

In the first internal report [4], a class of isolated Pulse Density Modulated(PDM)/PulseWidth Modulated (PWM) DC-AC SICAM converters was presented, which can use the audioreference either in the input stage or in the output stage. The block diagram i.e. the structure ofthe proposed isolated DC-AC SICAM is given in figure 1. As depicted, simple AC-DC power supplyis implemented using a diode rectifier (half-wave or full-wave) and a charge-storage capacitor. This”medium” stabilized i.e. not very stiff DC voltage is input to a dedicated single-phase DC-AC highfrequency (HF) voltage source inverter (VSI), implemented by unidirectional i.e. two-quadrantswitches (2QSWs). Isolation is achieved using a HF transformer with/without central tap on theprimary/secondary side. Since HF AC voltage is obtained on the secondary side, the output stageshould take care of both the rectification of the input voltage, as well as its inversion to an ACvoltage to resemble the desired audio reference. Therefore, the output stage is implemented usingbidirectional i.e. four-quadrant switches (4QSWs). At the end, load is interfaced to the outputstage via low-pass output filter.

As already stated in [4], isolated DC-AC SICAMs can utilize the audio reference either inthe input stage or in the output stage. Although approaches where audio reference is used solelyin the input stage are already present [5], this report will concentrate only on the topologies andcontrol algorithms where the audio reference is used in the output stage. This means that theHF transformer input and output voltages will be independent of the audio reference, making itstraightforward to use the same transformer for deriving auxiliary supply voltages for the con-trol circuitry. According to the author this should also lead to simpler design, more predictabletransformer flux levels (avoiding conservative, bulky designs) and easier control synthesis as well.

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Figure 1: Block diagram of an isolated DC-AC SICAM

2 Power supply

This section will briefly make an overview of several simple power supplies, which can beused for this class of SICAMs. As already mentioned, the idea behind SICAM is to use simplepower supplies with lower losses and high efficiency, instead of using bulky switch-mode powersupplies (SMPS). This means that the switching action and isolation should be incorporated as anintegral part of the SICAM converter, lowering the number of possible energy conversions.

Due to the aforementioned considerations, the simplest power supply would comprise of adiode rectifier (half-wave i.e. single diode or full-wave i.e. four diodes) and an electrolytic, charge-storage, filter capacitor, shown in figure 2a. The capacitor value should be chosen as a compromisebetween the desired maximum output voltage ripple and capacitor size. This power supply can beused in a laboratory low-power test setup, where a SICAM prototype would be usually connected tothe AC mains using an AC autotransformer i.e. a variac, so the input AC voltage will be increasedin steps to allow for low capacitor charging current.

The second possible power supply, depicted in figure 2b should be reconsidered when theSICAM is to be connected directly to the AC mains, which means that the input voltage willincrease gradually at switch-on instant, causing a huge inrush current through the rectifier diodes.Adding a simple resistor between the rectifier module and the filter capacitor can lower the inrushcurrent, on behalf of a slight voltage drop across the resistance during the regular operation. Addinga Negative Temperature Coefficient (NTC) resistor results in even smaller losses, since after NTChas warmed up at the start up, its resistance stays low as long as enough current is pulled from therectifier. However, repetitive switching of the power supply on and off without letting the NTC tocool down is dangerous, since its low resistance will not limit the inrush current. In high powersupplies, losses in the resistor can be avoided by clamping it with a relay or semiconductor switchafter the start up [6].

Since the SICAM is supposed to work in switching mode, with high slew rates of theconverter voltages and currents caused by rapid semiconductor switching, it is expected that theradiated noise and EMI will be high. Although these problems can be alleviated by cautiouscircuit layout design, it is advisable to use a line choke in combination with a capacitance, so theswitching noise would be stopped from propagating through the net, causing problems in othersensitive equipment. The line choke can also limit the capacitor inrush current at converter switchon. Simple power supply with added differential-mode EMI filter is shown in figure 2c.

Since in all of the SICAMs the emphasis is on the power supply simplicity, it is expectedthat the performance of the supply is not very high and therefore special attention should be payedto the control algorithm synthesis, which should provide very high Power Supply Rejection Ratio(PSRR).

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Figure 2: Power supply: a) only rectifier and filter capacitor, b) limiting the inrush current with(NTC) resistor and c) adding an EMI filter

3 Input stage

3.1 Introduction

The input stage of the isolated DC-AC SICAM shown in figure 1 should accept the electricalenergy from the grid, in a form of DC voltage from a simple AC-DC power supply and transfer itthrough the isolation barrier, i.e. over the HF transformer. Since in the class of DC-AC SICAMsdiscussed in this report audio reference is not used in any way to modulate the transformer voltages,the input stage only role is to transfer the energy received from the power supply to the outputstage and this is what solely limits the possible output voltage waveform.

If we turn to the magnetics basics and Faraday and Ampere laws, it is obvious that magneticenergy can be stored in a piece of magnetic material by applying current (DC or AC) through anexcitation coil (primary winding) wound around the magnetic core. We can assume that besidethe excitation winding, one or more windings are situated on the same core too. Although we arefree to choose the character of the current through the excitation coil which will be used for energytransfer, one should be aware that even in the case of DC current, energy is impressed into themagnetic core during the transient process of magnetization, which is actually characterized withvariable voltages across the coil. When the transient process has ended, in the DC steady-statesituation no voltages are induced in either the excitation winding or the rest of the windings. Theinternal magnetic flux build-up Φ of the magnetic core is determined by the time integral of theinduced voltage vi :

Φ =1

N

∫ t

0vidt (1)

where N is the number of windings of the excitation coil.It is obvious that in the case of the electrical energy transfer through an isolation barrier

represented in a form of a HF transformer with two windings - primary and secondary, one doesn’tneed to store energy in the magnetic core (so, there is no need for air gaps in the magnetic corein order to increase the magnetization inductance) but rather transfer it over. So, a symmetricalAC voltage waveform v1 should be applied across the transformer primary winding during oneswitching period Ts to cause magnetic flux Φ reset at the end of each complete switching action ofthe input stage:

Φ =1

N1

∫ Ts

0v1dt = 0 (2)

where N1 is the number of turns of the primary winding.The magnetic flux swing in the common magnetic core will induce voltage v2 across the

secondary winding, given by:

v2 = N2dΦ

dt(3)

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where N2 is the number of turns of the secondary winding.When an operational output stage is connected to the transformer secondary winding,

induced voltage will cause a current through it, in that way closing the cycle of energy transferthrough the transformer. Although this discussion may seem notorious, it leads us to an importantconclusion. In this class of isolated DC-AC SICAMs, there is no known limitation on the waveformof the AC voltage applied across the transformer primary winding by the input stage, except forit being symmetrical, or at least having an average value of zero during one switching cycle Ts toallow for magnetic core flux reset:

v1,av =1

Ts

∫ Ts

0v1dt = 0 (4)

If we cannot make any conclusion about the waveform of the applied primary voltage, wecan certainly discuss its frequency. It is widely recognized that, regarding the magnetic design,the switching frequency i.e. the frequency of the applied AC voltage waveform should be increasedin order to decrease the magnetic flux swing (1) and the corresponding magnetic induction swing,which leads to smaller magnetic components and cheaper designs. The limiting factor for theswitching frequency is in the way the energy losses are created in the combination of the inputstage and the HF transformer.

As far as this magnetic transformer basic overview is concerned, it may seem that theenergy transfer is lossless. However, this is not the case, since losses are created in both thetransformer magnetic core (hysteresis losses and eddy-current losses), as well as in the windings(conduction losses, skin and proximity effects). These losses are not constant, but they are stronglydependent and increase with the frequency and magnitude of the voltages and currents applied tothe windings, which will define the magnetic flux levels. The applied primary voltage waveform iscreated by the switching action of the switches in the input stage, which also represents a lossyprocess even when no load current, except the transformer magnetization current is flowing throughthem. These are the so called switching losses, which are predominantly dependent on the frequencyof the switching as well as on the magnitude levels of the conducted current being switched andreverse voltage being blocked. On the other hand, conduction losses of the saturated switchesare dependent on the components internal resistance and conducted currents, and are thereforefrequency independent. As a conclusion, we can say that the selection of the switching frequency inthe input stage should be approached very cautiously, and a suitable optimization method shouldbe developed to determine the best operating point of the compound ”input stage+transformer”which is capable of delivering the necessary power to the output stage with minimal losses and inthe same time keeping the input stage volume and price low.

The other important factor is certainly the audio performance of the output stage. Althoughnot obvious at this point, the switching frequency of the input stage will affect the performanceof the audio amplifying output section in terms of generated HF switching harmonics. Therefore,the switching frequency of the input stage should be high enough not to interfere with the controlstructure of the output stage, and to be far away from the baseband of interest. Otherwise, audioperformance deterioration should be expected or even instability can be induced by severe switchingwithin the frequency bandwidth of the output stage closed-loop control.

3.2 Topology of the input stage

It is certainly advantageous to create an input stage which would operate on higher fre-quencies (hundreds of kiloHertz), leading to smaller HF transformer and EMI filter on the mainsside, and in the same time having low losses, improving the efficiency of the overall SICAM. If wetake a look at the input stage only, the obvious limiting factor are the switching losses, which canbecome especially severe when considering the magnitude of the DC voltage rectified directly from

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the mains. Therefore, special attention should be payed to those topologies or control strategieswhich can provide lower switching losses on expense of minor extra cost or extra control effort.

The following topologies were found interesting for further research:

• Resonant converters: series, parallel or series-parallel (LCC) - especially popular for highfrequency and lower power converters, offering very low switching losses and sinusoidal outputwaveforms with low THD, but lack of suitable design techniques as well as plenty of non-reparable drawbacks make them a less preferable choice, and

• Soft-switched ZVS PWM inverters with an emphasis on phase-shift control - an exten-sion to the classical PWM converters which can provide near zero switching losses (ZVS) fora wide range of load currents, only with minor changes in the control algorithm.

3.3 Resonant converter as an input stage

When compared to the ”classical” class D audio amplifiers, the unrestricted SICAM struc-ture itself should provide topological means for lowering the losses and improving efficiency. Thatis why the resonant converters, which are known for their energy efficiency and compact design athigh switching frequencies, appear to be an interesting alternative for an input stage to investigate.Associated voltage and current waveforms are almost purely sinusoidal, so it is possible to use atrain of this sinusoidal voltage pulses in the output stage to construct the desired audio outputvoltage using PDM or to create larger pulses with variable width to resemble traditional PWM.

Resonant converters can be found in several different topologies, depending on the topologyof the switches or the resonant tank structure. Apart from resonant-switch converters, which arenot investigated herein, the most popular switching topologies for resonant converters are class E,class D, half-bridge and full-bridge [7]. Although Class E converters comprise of one active switchonly, its high voltage and current stress (peak switch voltage Usw,p ≈ 3, 5Vd and peak voltagecurrent Isw,p ≈ 3Id) severely aggravate the possible implementation, especially when the converteris supposed to switch the DC input voltage rectified directly from the AC mains. Class D (totempole) resonant converter combines lower voltage and current stress with low component count - onlyone switch more than the class E resonant converter. Half-bridge and full-bridge resonant convertertopologies also have lower component stresses, but the component count increases. Therefore, ClassD switching converter is preferred over all of the other approaches. In the basic resonant converters,the resonant tank can consist from: series LC (figure 3a), parallel LC (figure 3b) and series-parallelLCC (figure 3c).

However, some problems associated with the implementation of resonant converters becomeobvious right away. For example, a lack of suitable ”engineering” time-domain design methods forexact representation of resonant converter waveforms forced us to use approximate frequency-domain methods [2], [8], [9], [10], [11], i.e. sinusoidal analysis at the dominant frequency, de-pending on the excited modes of the resonant tank by the switching action of the converter itself.Time-domain approaches [12], [13] were found too complex, offering accuracy and flexibility (bothcontinuous and discontinuous conduction modes of the resonant converter) which were actually notneeded.

Beside the analysis problem, some technical and performance problems were found evenmore restrictive and this will be explained in detail in few subsections, regarding the correspondingresonant converter topology.

It should be stressed out, however, that all of the authors of resonant converter referencesfound in the literature were using resonant converters in rectification schemes, so there are actuallyno references to any resonant converter used in combination with subsequent bidirectional bridgefor creating AC waveforms.

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Figure 3: Class D resonant converter types: a) series LC, b) parallel LC and c) series-parallel LCC

3.3.1 Series resonant converter (SRC)

In the SRC, both resonant elements L, Cs are in series with the load. This has an advantageof having a DC blocking capacitor in series with the HF transformer, thus successfully avoiding anyDC saturation. The efficiency at idle is very high, since there can be no circular current throughthe resonant tank at no load. SRC can only step down the output voltage, which for a converteroperated from rectified AC mains voltage is not a disadvantage, since the desired output voltagewill be always lower.

The main disadvantages are caused by the same elements, which were regarded as the majorbenefit of the topology. When reconsidering higher power levels and higher ripple load currents, theseries capacitor Cs can become bulky, thus compromising the light design of the SICAM. Outputvoltage control at lighter loads is problematic, so a wide range of switching frequencies is requiredin order to compensate for small load variations. When operating near the resonant frequencyfs ≈ fr, output short circuit can result in huge over voltages because of the undamped resonanttank, so a fast control loop is a necessity.

3.3.2 Parallel resonant converter (PRC)

In the PRC, the capacitor Cp appears in parallel to the load. The converter itself hasa voltage step-up and voltage step-down properties, depending on the switching frequency fs toresonant frequency fr ratio fs/fr, which is certainly an advantage over the SRC. And even more:

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output voltage control with wide range of load variation is achieved with smaller switching frequencyadjustments. This means that even at light load, output voltage control can be unaffected. Anotherimportant feature of PRC is that even when operating at switching frequencies near the resonantfrequency of the resonant tank fs ≈ fr, output short circuit current is essentially limited by theinductor L impedance.

The major drawback of PRC is due to the circular currents flowing in the resonant tankL, Cp even without any load applied, resulting in very low power efficiency at idle. On the otherhand, at light load the quality factor of the resonant tank Q rises, so fast output voltage controlmust be used to avoid any possible overvoltages.

3.3.3 Series-parallel resonant converter (SPRC)

SPRC attempts to take advantage of the best features of SRC and PRC and in the sametime mitigate some of their drawbacks. That is why a class D SPRC is a resonant converter ofchoice for many rectifying HF applications [10], [11], [12], [14], [15], [16], [17]. Therefore, a series-parallel LCC resonant converter was reconsidered for use in an isolated DC-AC SICAM, instead ofthe simpler SRC and PRC.

From an analysis point of view, SPRC is desirable since all the transformer parasitics canbe suitably incorporated in the calculations by moving all the transformer leakage inductance tothe primary and adding it to the inductor L and in the same time moving the parasitic windingcapacitance to the secondary side and adding it to the capacitor Cp.

3.3.4 Characteristics of resonant converters when used in a SICAM

It is obvious that the use of any resonant converter in an isolated DC-AC SICAM is far moredemanding than the use of latter in a rectifier. Using a bidirectional bridge in the output stage,loaded with an output low pass filter and a loudspeaker essentially emerges as a widely and rapidlyvarying load, depending on the audio reference. One obvious example is the use of 2-level or 3-levelmodulation [3]: when using 2-level modulation, the combination of output filter and loudspeakeris always connected to the both ends of the resonant converter, thus resulting in higher no-loadlosses; but if we employ 3-level modulation just to get rid of these losses (beware of the commonmode noise!), sometimes the combination of the output filter and the loudspeaker will be connectedto the same bus essentially unloading the resonant converter and causing immense overvoltages.Even more: when returning the energy from the load to the resonant converter through the outputstage bidirectional bridge, load current can charge the capacitors Cp, Cs and also cause unexpectedrise of output voltage.

In conclusion: the resonant converter load current can have any direction and magnitudesustained by the loudspeaker output low-pass filter and a bidirectional bridge state, which from theresonant converter control perspective can not be predicted. Resonant tank components L, Cs, Cp

cause the resonant converter to have high output impedance, resulting in rapid output voltageperturbations which are strongly dependent on the varying load characteristics, i.e. on the switchingaction of the subsequent output stage. This is a major drawback which makes the use of a resonantconverter without fast output voltage feedback control loop almost impossible to manage.

SPRC’s output impedance Zo(s) is obtained by short-circuiting the voltage source, whichessentially connects the series combination of L and Cs in parallel with Cp:

Zo(s) =

1sCp

(sL + 1sCs

)

sL + 1sCs

+ 1sCp

=s2LCs + 1

s3LCpCs + sCs(1 +Cp

Cs)

(5)

which is shown graphically for L = 11.6µH and Cs = Cp = 5.88nF as a Bode plot in figure 4.What means for control of the resonant converter output voltage are feasible?

8

103

104

105

106

107

−150

−100

−50

0

50

100

150

200

Mag

nitu

de (d

B)

Bode Diagram

Frequency (rad/sec)

Figure 4: Output impedance of an SPRC for L = 11, 6µH and Cs = Cp = 5, 88nF

• Frequency control - widely used method for creating variable output voltage, due to thefrequency dependant output characteristics of the resonant converters; generally this is not adesired solution since almost constant frequency operation is preferred to guarantee the sameperformance of the input stage all over the possible operational range and to obtain pulseswith the same width or same area (Volt-seconds) for use in PDM output stage,

• Duty cycle control - this type of control is reported in [16], but it fails to achieve the thedesired performance, since for switching duty ratios different from D = 0, 5 DC-offset isintroduced to the resonant tank input voltage, i.e. the totem pole switches start acting as arectifier with variable output voltage, and

• Phase control - introduced in [18]; consists of two phase-shifted PWM totem-poles forminga class D inverter with the resonant tank and the HF transformer connected in between thepoles or with two resonant tanks starting from the poles and connecting the HF transformerto the ground.

When the method of frequency control is used upon some of the resonant converters, thepreferred working frequency is usually above the resonant frequency. By switching the converter ata fixed frequency higher than the resonance point of the resonant tank, the L−Cs−Cp combinationappears as predominantly inductive load, causing the current to lag the applied input voltage. Be-cause of the conduction of the load current through the diode antiparallel to the observed transistorwhenever opposite transistor switches off, Zero Voltage Switching (ZVS) is obtained at turn-on.By applying small capacitor in parallel to the transistor, ZVS at turn off can be achieved as well,due to the time needed for the load current to charge this dummy capacitor. Therefore, operatingthe resonant converters above the resonant frequency is superior in terms of switching losses andperformance [8].

The method of phase control certainly looks appealing, since full control of the resonantconverter output voltage can be achieved by changing the amount of energy injected into theresonant tank, and not actually changing the frequency of switching. However, this is done onexpense of additional totem pole with two active switches and still the large output impedance ofthe resonant tank limits the performance of the input stage, making it a less preferable choice fora SICAM.

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3.4 Soft-switched ZVS PWM inverter as input stage

3.4.1 Introduction to ZVS PWM inverters

Decreasing the energy loss in the input stage of a SICAM is a desirable feature, so insteadof using a hard-switched PWM inverter a soft-switched ZVS PWM inverter can be implemented[19],[20], [21]. It has completely the same structure as a hard-switched PWM inverter, but theswitching events are little bit altered. This results in decreased switching losses, as well as reducedtransistor resonant voltage ringing, which can be observed during rapid hard switching. Theprinciple of operation will be described using the figure 5.

Figure 5: ZVS PWM inverter: a) power delivered to the load, b) capacitance of T3 gets discharged,c) freewheeling cycle and d) capacitance of T2 gets discharged

The main benefit of the ZVS PWM inverter results from the intentionally programmeddelay between the turn-off of one transistor and the turn-on of other transistor in a single bridgeleg. During this time, no transistor in that leg conducts, and the freewheeling current sustainedby the inductive nature of the load, the transformer magnetizing inductance and the transformerleakage inductance discharges the drain-to-source parasitic capacitance of one of the MOSFETs,and charges the other, allowing the ZVS. The phases of one half-cycle of output voltage are shownin figure 5 and are described as follows:

a. Diagonal transistors T1 and T4 are conducting, so power is delivered from the source andthrough the transformer to the load. Drain-to-source capacitance CDS3 of T3 is charged to+Vd and voltage across the drain-to-source capacitance CDS4 of T4 is almost zero, i.e. CDS4

is discharged. Current flowing through the transistors consists from the reflected load current( (N2/N1)Iload ) and the magnetizing current (Im).

b. T4 turns off, so the capacitance CDS4 gets charged and CDS3 gets discharged by the primarycurrent, raising the voltage of the middle point from 0V to +Vd. This action continuesuntil the body diode of T3 or external diode D3 turn on to clamp the voltage across it toapproximately -0,7V. Turn-off of transistor T4 is lossy, but adding an additional small external

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capacitance across it can keep the voltage to near zero Volts until the current through theMOSFET channel is completely switched off.

c. As soon as the voltage across T3 reaches zero volts, transistor T3 is turned on, producing noswitching loss, i.e. ZVS at turn-on occurs. Applied voltage across the transformer is zero.

d. Transistor T1 is now turned off, so the primary current is now diverted into the parasiticcapacitances of T1 and T2, charging the CDS1 and discharging the CDS2. When the voltageacross T2 reaches zero volts, it will be turned on in a non-dissipative manner, so a programmeddelay must be provided for ZVS at turn-on to take place. Again, T1 turn-off is lossy and T2

turn-on is lossless.

This description corresponds to the case of switching only one leg at a time. If we assumethat before switching of one inverter leg, the voltage across the transformer primary was equal tothe DC bus voltage, then after the process of charge displace and transistor turn-off has ended theprimary voltage will be zero. This situation will last until switching is performed in the secondleg, resulting in reverse DC bus voltage across the transformer primary. It is obvious that theoutput voltage average can be controlled by altering the delay in switching the second leg, so theconverter operated in this way is referred as Phase-shift ZVS PWM inverter. The advantage of thisapproach is that only one MOSFET is to be turned-off and only one to be turned-on, resulting inelectrical charge being displaced using the primary current between only these two parasitic drain-to-source capacitances. Phase-shift ZVS PWM inverter output voltage v1 and associated switchingwaveforms for T1, T2, T3 and T4 are shown in figure 6a.

When both legs are switched in the same time - simultaneously, the same action of displacingthe electrical charge between the MOSFET parasitic capacitances occurs. However, in this caseinstead of two, all of the MOSFET parasitic capacitances play a significant role at the same time.Eventually, this leads to even higher demand for energy stored in the transformer leakage andmagnetizing inductances. Actually, the same switching action occurs in classical PWM invertersusing the dead time instead of the programmed delay. Whenever the PWM inverter is switched ina prescribed way using previously calculated delays to facilitate the ZVS by the freewheeling of theprimary current, it will be referred as Simultaneous ZVS PWM inverter. Simultaneous ZVS PWMinverter output voltage v1 and associated switching waveforms for T1, T2, T3 and T4 are shown infigure 6b.

Figure 6: ZVS PWM inverter output voltage v1 and switching waveforms: a) phase-shift ZVSPWM inverter and b) simultaneous ZVS PWM inverter

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At this point, a very important remark should be made. In the presently available references(for example [19],[20], [21]), Soft-switched ZVS PWM inverter is used in conjunction with a rectifieron the secondary side, which results in a highly predictable primary and secondary winding currentdirection. In this case, energy is always transferred from the source to the secondary side rectifier.Reflected load current, as shown in figure 5 always helps the magnetizing current to displace thecharge between the MOSFETs output capacitances, thus leading to ZVS at turn-on. As alreadymentioned in the description of the switching process, MOSFET turn-off is still lossy except in thecases when small capacitive snubbers are added in parallel to the MOSFETs.

When Soft-switched ZVS PWM inverter is used with an audio-reference-guided bidirectionalbridge as an output stage, rectifier diodes are removed, so the primary and secondary windingcurrent directions depend on the applied audio reference, as well as current direction in the outputlow-pass filter prior to the switching instant. Now the energy transfer can be in either direction,i.e. energy can be also regenerated from the load to the source. This makes the analysis morecomplex, since the primary current can be also in opposite direction from the magnetizing current,so effectively aggravating the ZVS at turn-on. In this limit case, when the load current reflectedto the transformer primary dominates over the magnetizing current causing total current in theopposite direction, instead of two diagonal MOSFETs, current is conducted using the correspondingantiparallel or MOSFET body diodes. This in turn results in ZVS at turn-off, and turn-on becomesa lossy process. This obviously has a resemblance with the Zero Voltage Switching (ZVS) and ZeroCurrent Switching (ZCS) of the resonant converter, in which it depends upon the leading/laggingcharacter of the resonant current. The phases of one half-cycle of output voltage with a largereflected load current in opposite direction from the magnetizing current are shown in figure 7 andare described as follows:

a. Diagonal transistors T1 and T4 are turned on, which results in positive voltage applied acrossthe transformer primary, but the reflected load current is flowing through the diodes D1 andD4 in opposite direction. This means that energy is regenerated from the load at the secondaryside via the transformer to the source at the primary side. Drain-to-source capacitance CDS3

of T3 is charged to +Vd and voltage across the drain-to-source capacitance CDS4 of T4 is equalto the diode D4 voltage drop (VD4

≤ 1V ), i.e. CDS4 is discharged. Current flowing throughthe diodes consists from the reflected load current ( (N2/N1)Iload ) minus the magnetizingcurrent (Im).

b. T4 turns off, but the capacitance CDS4 can not get charged since reflected load current isflowing through the antiparallel diode D4, keeping the voltage at near zero Volts. Turn-off oftransistor T4 is therefore lossless (ZVS) at turn-off.

c. Transistor T3 is turned on, producing switching loss because of the voltage across itVT3

= Vd − VD4≈ Vd. Reflected load current is diverted to discharge the parasitic out-

put capacitance CDS3 of transistor T3 and in the same time charge the capacitance CDS4. Assoon as this transient process has ended, the applied voltage across the transformer is zero.

d. Transistor T1 is turned off in a lossless manner (ZVS at turn-off) and the reflected load currentcontinues to freewheel through T3 and D1. Transistor T2 is now turned on with the full DCbus voltage across it, causing large switching loss at turn-on. Current is diverted from thediode D1 to the opening channel of transistor T2, charging the CDS1 and discharging theCDS2.

What happens in between these limit cases, when the reflected load current is opposingthe magnetizing current, but it’s not enough to cause the total current in opposite direction andZVS at turn-off? Obviously, the switching losses at turn-on will be reduced but not completelyeliminated, if the magnetizing current was designed to solely displace the charge between the

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Figure 7: ZVS PWM inverter with reflected load current in opposite direction from the magnetizingcurrent: a) power regenerated from the load through D1 and D3, b) T4 is turned off with ZVS,c) capacitance of T4 gets charged and T3 gets discharged and d) capacitance of T1 gets charged andT2 gets discharged

parasitic capacitances without any ”load help”. From this perspective, an obvious intention is tohave large magnetizing inductance yielding small magnetizing current, since this will make theregion of partly lossy switching transitions smaller in width. As a result ZVS will depend mostlyon the load current reflected to the transformer primary side. Switching losses regions in relationwith the load current magnitude and direction for two different magnetizing currents Im1 = 2Im2

are shown in figure 8.

Figure 8: Soft-switched PWM inverter switching losses dependance on reflected load current I ′load

for two different magnetizing currents Im1 = 2Im2

Compared with the resonant converters where operation above resonance is preferred, inthe ZVS PWM inverters preferred state of operation is ZVS at turn-on i.e. energy transfer from thesource to the load. In this case ZVS at turn-off can be achieved by adding small external capacitorsin parallel with the MOSFETs, which is usually done in the resonant converters too.

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3.4.2 ZVS fundamentals in soft-switched full-bridge PWM inverters

In order to simplify the analysis, in the following section only the case when the load currentfacilitates the ZVS at turn-on or the load current being zero will be investigated.

Several problems become obvious right away: if in the classical full-bridge PWM convertersthe aim was to increase the magnetizing inductance in order to decrease the magnetizing current(and cope with the decreased current slew rate), in the case of ZVS PWM converter magnetizingcurrent must be of a certain level to facilitate the ZVS when the load current is insufficient to doso. If this is not done, at light loads the input stage will experience high switching losses and lowconduction losses, while at heavy loads the input stage will be in ZVS offering low switching losses,while the conduction losses will increase. Sometimes, in order to allow ZVS at turn-off, additionalexternal capacitances can be added to keep the voltage at zero until the MOSFETs completelyturn off.

Charging/disharging of parasitic CDS and any other external capacitances is done usingthe transformer primary current. One can distinguish the following cases:

• Input stage was delivering power to the output stage just prior to switching. The primarycurrent consists from the reflected secondary (load) current and the magnetizing current.This is the most favorable case, resulting in almost sure ZVS of the input soft-switched PWMstage.

• Output stage disconnected the load prior to the switching action (freewheeling in the outputstage, if provided, ceased to transfer energy back to the input stage), but the core itself is stillmagnetized since no opposite direction Volt-seconds were applied to reset it. Magnetizingcurrent only is flowing through the transformer primary, and if designed properly, this shouldbe enough to guarantee ZVS of the primary stage.

• The worst case appears when the output stage has disconnected the load, and the core itselfis reset prior to the switching due to the, for example, freewheeling action of the output stageeffectively shortening the secondary. In this case there is no magnetizing current, so the ZVSmust be accomplished by the energy stored in the transformer leakage inductance.

The necessary switching delay time for each of the legs will be calculated for the worstcase, where only the energy in the leakage inductance facilitates the ZVS of the input stage. Inthis case, the leakage inductance plus any additional inductance of the leads in the input stageforms a resonant circuit with the output (parasitic drain-to-source) capacitances of the turning-offand turning-on transistors. The process of charge displace is finished in a time interval equal toone-fourth of the resonant period:

td,res =T

4=

2π√

LrCr

4=

π

2

√

LrCr (6)

where Lr = Ll + Ladd is the resonant inductance, consisting of the leakage inductance Ll and anyadditional inductance in the loop Ladd and Cr is the resonant capacitance.

Special attention should be payed to determine the resonant capacitance Cr. Obviously, itconsists from the paralleled output capacitances of two affected transistors as well as the parasiticcapacitance of the transformer primary (usually very low). Simple derivation in [20] followed alsoherein, but with a slight alteration at the end can determine it very precisely.

The output capacitance of a MOSFET Coss is usually given in a datasheet for applied drain-to-source voltage of Voss = 25V , but it is far away from being constant. It is depletion dependentcapacitance and therefore decreases with the increase of a drain to source voltage:

CDS(VDS , n) = Coss

(

Voss

VDS

)n

(7)

14

where n is usually between 1/2 and 1/3.Energy stored in the output capacitance can be calculated in the following way:

E =

∫

vidt =

∫

vdQ

dtdt =

∫

vdQ =

∫

VDSCDS(VDS , n)dVDS (8)

which using the equation (7) transfers to:

E = CossVnoss

∫

V 1−nDS dVDS =

CossVnossV

2−nDS

2 − n(9)

Taking n=1/2:

E =2

3CossV

1

2ossV

3

2

DS (10)

or when having two output capacitances in parallel, like in the case of the switching instant shownin figure 9a, which we are investigating now:

E =4

3CossV

1

2ossV

3

2

DS =1

2· 8

3CossV

1

2ossV

3

2

DS (11)

which, when compared with the widely known expression for the energy stored in a capacitorE = 1/2 · CV 2, leads to the final result for the resonant capacitance:

Cr =8

3Coss + Cadd (12)

where Cadd represents the additional interwinding capacitance of the primary.When switching both inverter legs in the same time (simultaneous ZVS PWM), drain-to-

source capacitances appear on the place of each of the MOSFETs in the full bridge, like shownin figure 9b. This essentially connects the paralleled output capacitances of each leg in seriestogether and with the resonant inductance Lr, which results in two times lower resonant inductancecompared with (12):

Cr,sim =4

3Coss + Cadd (13)

Although this means that the resonant time td,res in (6) has decreased for a factor of√

2, theactual resonance inductance energy demand for charge displace has increased by factor of 2, sincenow there are two capacitances which should be discharged and their charge displaced. It should benoticed, however, that the role of the DC-blocking capacitor CDC during these transitions is onlymarginal, since its high capacitance keeps it discharged during normal operation and experiencingvery low impedance at the high switching frequencies.

Figure 9: Determining the resonant capacitance Cr when switching: a) single leg and b) both legsin the same time

15

After the initial resonant delay time td,res has been determined, we can calculate what is theminimum value of the magnetizing current Im,min, which can store enough energy in the leakageinductance of the transformer to perform the charge displace. Using the equation (11) and themagnetic energy stored in the leakage inductance:

1

2LlI

2m,min =

4

3CossV

1

2ossV

3

2

DS (14)

the final expression for the minimum magnetizing current becomes:

Im,min = 2

√

√

√

√2

3

CossV1

2ossV

3

2

DS

Ll(15)

Minimum magnetizing current Im,min will be achieved with a maximum magnetizing induc-tance Lm,max(and neglecting the leakage inductance Ll):

Lm,max =Φ

Im,min=

Vinton

Im,min(16)

In most of the cases, the transformer is designed using some method where the total losses inthe transformer (core and copper losses) are minimized choosing the number of primary windingsand the wounding technique (interleaving, paralleling several windings with smaller diameter -Litz wire etc.). Of course, this may lead to a design where the minimum leakage inductance andmaximum magnetizing inductance are already set, and the latter is too large to cause enoughmagnetizing current to facilitate the ZVS. Gapping the magnetic core will help to increase theleakage inductance and decrease the magnetizing inductance, which in turn has a positive effectupon the magnetic energy stored in the transformer leakage inductance. This will also lead to slightlinearization of the magnetic core characteristic, making it less susceptible to DC saturation and fluxcreepage. However, the energy efficiency will be compromised due to the increased magnetizingcurrent at all powers, but especially at idle. So, a sort of an optimization procedure should beundertaken to determine the optimal ratio of the switching and conduction losses, which will leadto lowest overall losses at idle.

Other approaches has been investigated in literature too, like adding an inductor or evensaturable inductor in series with the transformer primary winding [19], which allows ZVS operationof the converter down to very low loads. In the first approach the amount of stored magnetic energyin the primary path i.e. the resonant inductance Lr is increased by adding extra inductance andnot by increasing the transformer magnetizing current, like in the case of gapping the magneticcore. In the latter case, the saturable inductor used in conjunction with a DC-blocking capacitoris released during freewheeling when the primary current reaches zero Amperes and it holds it thatway, so ZCS at both turn-on and turn-off of particular switches is observed [22].

No matter the means used to achieve ZVS, caution should be exercised not to rely solelyon the calculated values for the resonant delay. This is especially true in the unloaded outputstage case. In the cases where the implemented resonant delay td,res, calculated according to (6)is low, and the magnetizing current is unable to perform the charge displace in the programmedtime due to the unrealistically low maximum magnetizing inductance Lm,max, the transistor inone leg is turned-on although the output capacitance of the other transistor is not fully charged.This means that a large inrush source current will flow through the output capacitance of theturning-off transistor, which will facilitate the complete discharge displacement and eventually leadto complete turn-off of the desired transistor. This is certainly not desired, but otherwise veryconservative delays should be implemented resulting in huge performance degradation. Therefore,some trade-offs must be done and this is especially important at higher DC-bus voltages, when thecharge stored in the MOSFET’s output capacitance is correspondingly large.

16

One possible approach is the following: calculate the maximal (very conservative) delaytime td,max to discharge one output capacitance and compare it with the resonant delay time td,res

(6). An assumption is made, that the input stage is unloaded, so that the constant magnetizingcurrent Im is the only one which performs the charge displace.

td,max = QIm

= 1Im

∫ Vin

0 CdV = 2Lm

VinTs

∫ Vin

0 Coss

(

Voss

V

)ndV = 2Lm

VinTsCossV

noss

∫ Vin

0 V −ndV =

= 2Lm

VinTsCossV

noss

V 1−n

1−n

∣

∣

Vin

0= 2Lm

VinTsCossV

noss

V 1−nin

1−n = 2LmCoss

Ts(1−n)

(

Voss

Vin

)n(17)

which for n = 1/2 becomes:

td,max =4LmCoss

Ts

√

Voss

Vin(18)

In the cases where this maximum delay time td,max is several times bigger than the resonantdelay time td,res, it makes no sense in using either of them, since using td,max results in hugeperformance degradation and using td,res results in large capacitive inrush current and stress.Therefore, letting the half of the charge stored in the output capacitance to be displaced by themagnetizing current Im and and the rest of it with the short-circuit current Isc makes an interestingalternative. Because of the nonlinear dependance of the output capacitance from the applied voltage(7), a coefficient a is introduced which determines at which drain-to-source voltage VDS = aVin thehalf of the charge Q is already displaced:

Q2 =

∫ aVin

0 Coss(Voss

V )ndV =∫ Vin

aVinCoss(

Voss

V )ndV∫ aVin

0 V −ndV =∫ Vin

aVinV −ndV

V 1−n

1−n

∣

∣

aVin

0= V 1−n

1−n

∣

∣

Vin

aVin

(aVin)1−n = V n+1in − (aVin)1−n

2a1−nV 1−nin = V 1−n

in

⇒ a =(

12

)1

1−n

(19)

which for n = 1/2 gives:

a =

(

1

2

)2

= 0, 25 (20)

Following the same procedure in (17), the half-charge delay time td,hc can be determined:

td,hc = QIm

= 1Im

∫ aVin0 CdV = 2Lm

VinTs

∫ aVin0 Coss(

Voss

V )ndV =

= 2Lm

VinTsCossV

noss

∫ aVin0 V −ndV = 2Lm

VinTsCossV

noss

V 1−n

1−n

∣

∣

aVin

0=

= 2Lm

VinTsCossV

noss

a1−nV 1−nin

1−n = 2LmCoss

Ts(1−n) a1−n(

Voss

Vin

)n

(21)

which for n = 1/2 becomes:

td,hc =4LmCoss

Ts

√a

√

Voss

Vin=

1

2· 4LmCoss

Ts

√

Voss

Vin=

1

2td,max (22)

So, reducing the maximum delay time to half allows the inrush capacitive current to displacethe other half of the charge stored in the output capacitance of the MOSFET much faster than themagnetizing current itself.

17

Utilization of the primary side DC-blocking capacitor in series with the transformer isusually referred as unsuitable engineering practice. Leaving aside the increased volume and priceof the product, adding a series capacitor to cope with any primary side imbalance is potentiallydangerous in terms of unequal charging (i.e. voltage) of the capacitor during the positive andnegative half-cycles, thus resulting in uneven alternate primary voltage pulses applied across thesecondary side load. Therefore, larger blocking capacitance Cb is needed to mitigate the situationand lower the imbalance voltage ∆V as a result of unequal charging ∆Q during each of the halfperiods (∆V = ∆Q/Cb). Although the wish is to avoid this approach, it is still a practice of choicewhen compared with the other techniques to cope with the imbalance problem, like the current-mode control and different balancing techniques for the primary current, which necessitate use ofcurrent transformers [6].

At the end, we can emphasize that the necessary delays for the legs of the ZVS PWMinverter largely depend on the character of the output stage. In the case of a simple rectifier like in[19], [20], [21], both legs can have different delays due to the different currents which displace thecharge in each of them: in one leg the charge displacement is always done with the reflected loadcurrent through the output inductor (current source) plus the magnetizing current and in the otherleg the charge displacement is always resonant with the leakage inductance. However, in the caseof an output stage in a form of a bidirectional bridge governed by a superimposed audio reference,input stage can not know what is the exact configuration of the initiated bidirectional switches,so the necessary delay times may vary at a large scale. Designing it conservatively for the worstcase seems as the only solution, which tends to fit all of the cases, except maybe for the lightestloads, when the load current actually is not so large so the conduction and switching losses will bealready low.

3.4.3 Integration of the ZVS PWM inverter input stage within the SICAM

PWM inverters, either half-bridge or full-bridge, have a desirable property of low outputimpedance, which makes the output voltage almost unaffected even by large load current vari-ations. The output voltage they produce has a rectangular form, which results in two possibleimplementations:

• PDM - AC HF rectangular-shape pulses are created on the secondary side of the HF trans-former, which are then used by the PDM output stage to create train of positive and negativevoltages across the load to resemble the desired audio signal, as shown in figure 10a, or

• PWM - AC rectangular-shape pulses with a frequency chosen to optimize the losses and thevolume of the combination ”input stage + HF transformer” are transferred to the outputstage, then subsequently chopped and inverted by the bidirectional bridge according to theaudio reference in a PWM manner, as depicted in figure 10b.

For PDM SICAM, a phase-shifted version of the HF ZVS PWM inverter input stage isreconsidered, since the duration of the power pulses can be altered according to the input voltagemagnitude to deliver same pulse area (Volt-seconds) at any moment, which will decrease the burdenimposed on the output stage control circuitry. For a simple PWM SICAM, ZVS PWM inverterwith medium switching frequency and maximum duty cycle is to be used, since energy must betransferred to the output stage all the time.

18

Figure 10: Input and output stage output voltage waveforms: a) PDM and b) PWM, with thedashed line showing the desired output stage output voltage

4 Output stage

4.1 Construction of 4QSWs

It was already mentioned in the introductory section, that the output stage consists frombidirectional i.e. 4QSWs in a bridge configuration for obtaining maximum output power. A verygood review of the bidirectional switch implementation and safe commutation is given in [23], withsome subsequent modifications and improvements presented in [24], [25], [26].

The operation of the bidirectional bridge can be split into two intertwined, inseparableparts: rectification and inversion. Although both processes occur simultaneously, we may think ofthe bidirectional bridge as making rectification of the AC input voltage from the inputs stage andin the same time performing the inversion according to the audio reference, like a full bridge ClassD amplifier.

A single quadrant switch (1QSW) is capable of conducting only one current direction andblocking only one voltage direction. Its characteristic is therefore completely situated in a singlequadrant of the V-I plane. Representatives of this group are simple switching elements: diode,BJT, IGBT etc.

A two quadrant switch (2QSW) operates in two quadrants of the V-I plane. It can be:

• voltage 2QSW - it is capable of blocking voltages of both polarities, but it conducts currentin only one direction; voltage 2QSW is usually constructed by series connection of a diodeand a transistor (BJT,IGBT); and

• current 2QSW - it is capable of conducting current in both directions, but it blocks voltageof only one certain polarity; this switch is usually made of an antiparallel pair of a diode anda transistor.

It should be stressed however, that because of the MOSFET being a representative ofmajority carrier devices and because of its body diode, there is a possibility of conduction ofcurrents with both directions through the MOSFET’s single type semiconductor channel. Thismakes the MOSFET itself a current 2QSW. MOSFET voltage 2QSW can be obtained by addinga series diode, thus effectively blocking one possible current direction.

4QSW is constructed by anti-parallel connection of two voltage 2QSWs, or by anti-seriesconnection of two current 2QSWs. In the cases where the 4QSW consists of two anti-parallelvoltage 2QSWs, the current paths for different current directions are clearly separated, and each

19

of the current directions can be separately controlled. This feature is not so obvious for the 4QSWconsisting of two current 2QSW, where these two cases are distinguished:

• both current paths are closing through the same element (for ex. a MOSFET), so withoutmeasuring the current sign we cannot determine the zero-crossing point to block a certaincurrent direction by turning off the element completely, or

• both current paths are clearly separated, but one path is closing through a passive, uncontrol-lable semiconductor element (diode), thus resulting in possible blocking of only one distinctivecurrent direction.

A way to control the current direction of a 4QSW consisting of two current 2QSW emergesonly after combining the two 2QSW together.

The intention is to make a bidirectional full-bridge consisting of high-power high-speed4QSWs. Obviously, the power MOSFET is a semiconductor component of choice for the powerlevels and speeds we are interested in. Also, having separately controllable current paths is adesirable or even a mandatory feature, since providing a continuous current path for the currentthrough the output stage filter inductor without short circuiting the transformer secondary issurely necessary. Otherwise, dangerously large induced voltage spikes should be expected acrossthe output filter inductor. Therefore, the preferable MOSFET 4QSW with clearly separated andcontrollable current paths consists of two MOSFET voltage 2QSWs connected in anti-parallel. Itsscheme is given in figure 11.

Figure 11: MOSFET bidirectional bridge as audio output stage

It is noticeable, that in each of the legs there is a series rectifier which will cause largelosses when conducting the load current. When compared with the combination of a SMPS anda classical switching mode Class D audio power amplifier, this corresponds to moving the SMPS’secondary side rectifier diodes to each of the paths of the bidirectional bridge This is an obviousdrawback of the approach, and the design section will show how much the losses are aggravated.Therefore, future research will concentrate on building a bidirectional bridge with 4QSW with twoMOSFETs connected in series, which has lower losses and better linearity.

4.2 Commutation strategies for bidirectional bridges

The bidirectional bridge introduced in the previous section can be also referred as a single-phase to single-phase matrix converter. This makes the matrix converter commutation techniquesapplicable to the aforementioned audio output stage. However, some limitations when transferringfrom the largely exploited three-phase case [23], [24], [25], [26] to a single-phase are observed.

20

The simplest strategies for commutation of the switches, which consist of providing a dead-time between the switches or allowing an overlap, result in disrupted load current or short circuitedsource voltage correspondingly, so they are both theoretically and practically unusable.

The basic commutation strategies therefore are:

• current controlled - the commutation strategy is strongly relying on accurate determinationof the load current sign, so that a continuous current path is provided without allowing ashort circuit of the source; and

• voltage controlled - the commutation strategy is based on the input voltage sign measurement,so that right switches are chosen which not result in any violation of the electrical laws.

Regarding the structure of the bidirectional bridge at figure 11, current controlled commuta-tion can be accomplished using the switching pattern in Table 1 and voltage controlled commutationusing the switching pattern in Table 2.

beginning state iout off on off on final state

1,6 & 3,8 > 0 3,8 4,7 1,6 2,5 2,5 & 4,7< 0 1,6 2,5 3,8 4,7

2,5 & 4,7 > 0 2,5 1,6 4,7 3,8 1,6 & 3,8< 0 4,7 3,8 2,5 1,6

Table 1: Current controlled commutation sequence of the bidirectional bridge in figure 11

beginning state vin on off on off final state

1,6 & 3,8 > 0 4,7 1,6 2,5 3,8 2,5 & 4,7< 0 2,5 3,8 4,7 1,6

2,5 & 4,7 > 0 3,8 2,5 1,6 4,7 1,6 & 3,8< 0 1,6 4,7 3,8 2,5

Table 2: Voltage controlled commutation sequence of the bidirectional bridge in figure 11

Both presented strategies have some practical pitfalls. Current controlled commutationstrategies are very popular in the motor drives community, since the load current is a measuredquantity in order to accomplish field oriented control. However, large current measurement andaccurate current zero-crossing detection in a same current sensor are two fighting goals, since forcurrent measurements (for ex. in motor drives) a wide range of load currents should be accommo-dated, while for zero current detection very low noise and high accuracy environment with verysmall currents should be provided. Therefore, poor results are reported with current controlledcommutation only because of the low sensitivity, high noise and offset levels of the present state-of-the-art current sensors. An obvious advantage of this approach is that load current can change itsdirection even when the commutation process has started. In that case, the other current directionwill be usually prohibited, so the load current will settle at zero until the commutation process hasended.

Voltage controlled strategies are facing the same problems of inadequate measuring sensorslike the current controlled strategies, despite of the additional volume and price burden imposedby their installation. However, they have an another disadvantage - input voltage reversal during acommutation is not allowed since this can result in having wrong switches turned on with possibledisastrous results.

21

Combination of both techniques are also investigated in some references. In these ap-proaches the alternative strategy is used whenever the first strategy enters into the uncertaintyregion where the voltage/current sign can not be accurately determined. Unfortunately, in the caseof both voltage and current sign being uncertain, further switching can be catastrophic. To avoidthis some retarding or prohibition techniques are executed where the switching is avoided as longas the voltage and/or current signs are uncertain, but the quality of the output voltage and inputcurrent are therefore compromised.

There are some three-phase techniques which can be used to overcome the pitfalls of theaforementioned strategies, like replacement [25] and prevention [26]. These consist of a smart com-mutation algorithm which changes the order of switching between the phases where the input linevoltage sign is not certain by putting the third phase for safe commutation in between. Basicallythis results in shifting from one uncertain commutation to two certain, but more lossy commuta-tions. Since in the case of the single-phase bidirectional bridge for audio-output stage there is noother phase to safely commute to, another approach must be found.

One possible approach to safe switching of a single-phase bidirectional bridge will be pre-sented in the next section.

4.3 Master/Slave operation of the input/output stage to accomplish output stagesafe commutation

Voltage controlled commutation is usually regarded as more inferior to the current controlledcommutation because of the incapability of successfully finishing the commutation if the inputvoltage sign changes during the process. This problem is especially emphasized in the case of threephase matrix converters, since the input voltage is taken right from the grid as it is, so there isnothing the converter on the user side can do to mitigate the commutation.

The AC-AC output section of the SICAM presented in this report is actually powered bythe output voltage of the DC-AC input stage, which operation as we have shown previously, istotally up to our choice. Therefore, by mindfully operating the input stage, every possible voltagesign change during an output stage commutation can be avoided. There are probably several waysto do that, but in this report we will present an approach referenced as Master/Slave operation ofthe input/output stage.

The premises for the operation of this compound input/output stage are like follows:

1. Each of the stages can be either a master or a slave,

2. Both stages can not be masters in the same moment,

3. It is possible for both stages to reside in a slave mode at the same time,

4. Transition of one stage from slave to master is done only if the other stage is in slave mode,

5. Transition back from master to slave of one stage does not depend on the internal events inthe other stage, but it allows the latter to transfer from slave to master, if it was waiting forpermit.

So we can imagine the SICAM like having a single logic ”master/slave” line, which can havetwo possible states. If we implement it with positive logic, than logic one (”1”) means that one ofthe stages is in master mode and logic zero (”0”) means that both stages are slaves. Each of thestages becomes a master, if premise 4 is satisfied and a command is issued to make a transition: forthe input stage it means that the voltage across the transformer primary is to be reversed and for theoutput stage it means that a commutation of the bidirectional bridge is to be undertaken in orderto accommodate the audio reference. Whenever a transition is to be made and the master/slaveline is idling at ”0”, the corresponding stage is pulling the master/slave line up to ”1” occupying

22

it for the time of its transition. Master/slave line will be released as soon as the transition hasended, but according to premise 5 this is done without any regards to the other slave stage. In thisway, the ”master” can take all the time needed to finish the transition safely. This is, however,done on expense of increased distortion, sacrificing some performance. Due to the premise 1, bothstages can not be in master mode in the same time, so transitions in both stages can not occursimultaneously, thus effectively avoiding any possible dangerous commutation.

If we implement the aforementioned master/slave control algorithm, the only thing theoutput stage control still needs to know is the input stage output voltage polarity, so that each ofthe commutation commands proceed according to the safe switching pattern in Table 2. This isdone using a single unidirectional logic-level line from the input to the output stage. Therefore,the block diagram of the master/slave control of isolated PDM/PWM SICAM obtains the formdepicted in figure 12.

Figure 12: Master/slave control of isolated PDM/PWM SICAM

In this way, the expensive or noisy current and/or voltage sensors, which are needed in all ofthe other methods are avoided, but on behalf of little performance degradation. In the case of theinput stage, if the transition is needed and the output stage is already making the commutation,thus being a master, prolonged voltage pulse will be applied which can cause increased flux in thetransformer magnetic core, maybe even causing saturation if there is only a minor safety margin.In order to avoid any imbalance in the applied Volt-seconds, the control algorithm should besupplemented with a possibility to apply an equally large pulse of opposite polarity for balancingpurposes, otherwise the applied DC offset will emerge across the DC blocking capacitor, possiblycausing an imbalance in the applied load voltage. On the other hand, when talking about the outputstage, any delay in the transition command will cause output voltage distortion, which should besubsequently compensated by the feedback control loop. Therefore, it is of prime interest to keepthe transition or commutation times low, thus effectively avoiding larger performance degradation.

5 Design of isolated PWM DC-AC SICAM

5.1 Specifications and preliminary calculations

Each design starts with some specification, and in this case only several were set:

• Input voltage (AC mains): Vin,rms = 230 V

• Output power (sinusoidal): Pout = 100 W

• Load impedance: Z = R = 8 Ω

23

For the output power range specified, an approach should be chosen, which will resultin modest component count and complexity - presumably half-bridge in the input stage (withcapacitors) and half-bridge in the output stage (ground referenced load). However, in order toinvestigate the possibilities of implementing the already proposed complex master/slave controlprinciple with larger bidirectional bridges for the highest output powers, it was decided to implementboth input and output stage as a full-bridge converters.

It is also important to choose appropriate switching frequency of both the input and outputstage. As it became obvious from the previous section, each time the input stage changes thepolarity of the power pulses, a transition of the output stage will follow to apply the correctpolarity of these pulses across the load. Therefore, the actual switching frequency of the outputaudio power amplifying stage is dependent upon the switching frequencies of both stages. We aredesigning a laboratory setup, so the switching frequency of both stages can be changed in a widerange, but it is supposed that neither will be lower than 100 kHz. Therefore, the transformer iscalculated using the lowest switching frequency of the input stage fs1,min = 100 kHz, when the fluxswing is the largest. The switching frequency of the output stage is chosen to be fs2 = 200 kHz,which should provide larger control bandwidth and less switching interference into the band ofinterest.

The output RMS voltage across the load (output filter + loudspeaker) is found to be:

Vout,rms =√

PoutR =√

100 · 8 = 28.28 V (23)

The maximum (peak) value of the output voltage, for sinusoidal waveform is:

Vout,max =√

2Vout,rms =√

2 · 28.28 = 40 V (24)

The maximum (peak) value of the output current, for sinusoidal waveform is:

Iout,max =Vout,max

R=

40

8= 5 A (25)

Assuming sinusoidal audio signal reference, the RMS value of the load current is found tobe:

Iout,rms =Iout,max√

2=

5√2

= 3.54 A (26)

and its average value is:

Iout,av =2

πIout,max =

2

π· 5 = 3.18 A (27)

In order to determine the maximum voltage on the secondary side of the transformer V2,additional 5 V of voltage drops throughout the secondary side switches, transformer secondary andoutput filter parasitics were added to the desired maximum output voltage Vout,max:

V2 = Vout,max + 5 = 40 + 5 = 45 V (28)

On the primary side, the maximum input voltage is:

Vin,max =√

2Vin,rms =√

2 · 230 = 325 V (29)

If we allow 10 V of voltage drops across the input stage switches, transformer primary, DCblocking capacitor and voltage ripple on the input filtering capacitor we arrive to the followingprimary voltage of the transformer:

V1 = Vin,max − 10 = 325 − 10 = 315 V (30)

So, the transformer voltage transfer ratio n is:

n =V1

V2=

315

45= 7 (31)

24

5.2 Input stage

The designed prototype is not intended to be a final product, but only a testing setup.Therefore it is generally desired to over-dimension the components and allow easy increase ofoutput power by changing the core element - the transformer transfer ratio.

The following MOSFETs are reconsidered for building the input stage:

• IRF730 from the HEXFET PowerMOSFET family of International Rectifiers, with data pro-vided in table 3, and

• SPP11N60C3 from the CoolMOS Power transistor family of Infineon Technologies, with dataprovided in table 4.

VDSS [V ] ID [A]/25 RDS,on [Ω] Ciss [pf ] Coss [pf ] QGD [nC]VDS=320V gfs [S] VGS,th [V ]

400 5.5 1.0 700 170 22 2.9 3

Table 3: Short summary of the electrical characteristics of IRF730

VDSS [V ] ID [A]/25 RDS,on [Ω] Ciss [pf ] Coss [pf ] QGD [nC]VDS=480V gfs [S] VGS,th [V ]

650 11 0.38 1200 390 22 8.3 3

Table 4: Short summary of the electrical characteristics of SPP11N60C3

IRF730 with its blocking voltage rating of VDSS = 400 V provides thinner N− layer andtherefore lower input capacitance Ciss and gate-to-drain (”Miller”) charge QGD. On the otherhand, SPP11N60C3 with its blocking voltage rating of VDSS = 650 V and larger current ratingID = 11 A (larger die) provides slower switching due to the increased internal parasitic capacitancesand associated charges and therefore higher switching loss. But the latter is certainly more robustchoice and a representative of more advanced technology.

In order to avoid the reverse recovery charge effects of the intrinsic body diodes in theMOSFETs, it is decided to put anti-parallel external ultra-fast low-loss controlled avalanche recti-fiers BYV27-400, produced by Philips Semiconductors. Electrical characteristics of the BYV27-400diode are summarized in table 5.

VR [V ] IF (AV ) [A] VF,max [V ] IR [µA] trr [ns] Cd [pF ]

400 1.9 0.82 5 50 80

Table 5: Short summary of the electrical characteristics of BYV27-400

Gate drivers for the MOSFETs are made using pulse transformers wound on two smallferrite (N30) 12.5x7.5x5 ring cores. The two cores are assembled with 8 turns 0.35 mm copperwire on the primary and two secondaries with 11 turns 0.35 mm copper wire each, for the diagonaltransistors. Three windings are distributed throughout the core, but due to the unequal numberof turns (no bifilar/trifilar wires), coupling is compromised. Primary windings are being suppliedthe pulses from an 1.5 A dual high-speed non-inverting MOSFET driver TC4427 from Microchip.Gate resistors were chosen to be RG = 3.3 Ω to allow for fast transition and low switching loss.

The hardest calculation to make is certainly the dead-time between the switching transitionsof two MOSFETs in the same leg. Since the SICAM which is being designed is PWM and not aPDM, we don’t need to control the Volt-seconds of the individual pulses. As we don’t need any

25

phase-shifted operation of the left and the right leg of the full-bridge input stage, both legs shouldswitch in a same time, with a small dead-time to avoid shoot-through phenomena and to allowdecrease of the switching loss by the mechanisms explained in the previous sections.

Due to the fact, that all of the switches are making their transitions simultaneously, (13) isused to calculate the resonant capacitance Cr,sim:

Cr,sim =4

3Coss + Cadd ≈ 4

3Coss (32)

As mentioned previously, this will decrease the resonant time td,res in (6) for a factor of√

2compared to the case of a single leg switching.

Using (15), one can determine what is the minimal primary current I1,min, as a sum of thereflected load and ripple current and the magnetization current, which can guarantee total chargedisplace and therefore ZVS:

I1,min = 2

√

√

√

√2

3

CossV1

2ossV

3

2

DS

Ll(33)

By making the calculations, it will become obvious that the minimum primary current whichprovides ZVS is very large. Therefore during normal operation without any saturable inductor onthe primary side to facilitate the transformer leakage inductance, the input stage will experienceswitching loss at the instants when the transformer core is reset (no magnetization inductanceinterfering) and the leakage inductance is not capable of storing enough magnetic energy for chargedisplace between the MOSFETs output capacitances.

Resonant capacitances, resonant times and minimum primary currents for ZVS with corereset for both MOSFETs are given in table 6, for measured leakage inductance of the transformerLr = 10 µH at fs1 = 200 kHz.

IRF730 SPP11N60C3

Coss [pF ] 170 390

Cr,sim [pF ] 227 520

td,res [ns] 75 113

I1,min [A] 1.21 1.84

Table 6: Resonant capacitances Cr,sim and resonant times td,res for simultaneous transitions ofboth legs

The actual implemented delay time was a little bit larger, just to allow ZVS at lowerload currents and to avoid any possible shoot through phenomena. The programmed delay wasimplemented as trimmed R-C-Diode combinations in front of the TC4427 driver.

5.3 Expected losses in the input stage

Calculation of the losses is very difficult in a complex and compound system like this. But,with several assumptions, an useful approximate can be made to reveal the performance in termsof energy savings.

5.3.1 Conduction losses

Conduction losses are the ones which occur during the conduction of the switches anddiodes, out of the transition phases. These will be calculated with assumption of having a positive

26

load current Iout > 0 and therefore positive reflected load current to the transformer primary I1 > 0corresponding to full output power and assuming maximum ripple current Ifr = Ifr,max throughthe output filtering capacitor, which occurs at zero output power.

Current flowing through the switches represents a sum of the reflected load and ripplecurrent and the transformer magnetizing current. When calculating the conduction losses, RMSvalues are taken into account:

I2sw1,rms = I2

1,rms + I2m,rms (34)

The peak-to-peak ripple current through the output filter capacitor can be found by mul-tiplying the slope of the ripple current Vout,max/Lf by the on-time of the secondary side switchesat zero power, i.e. duty cycle is D = 0.5. So, the maximum ripple current is:

Ifr,max =Vout,max · DTs

2Lf=

0.5Vout,max

2Lffs2(35)

It will be shown in the one of the following section, that the output filter inductor isLf = 2 · 21 µH = 42 µH, which gives the following result for the maximum ripple current:

Ifr,max =0.5Vout,max

2Lffs2=

0.5 · 402 · 42 · 10−6 · 200 · 103

= 1.19 A (36)

Assuming linear character of the ripple current, its RMS value is:

Ifr,rms =Ifr,max√

3=

1.19√3

= 0.69 A (37)

and its average value is:

Ifr,av =Ifr,max

2=

1.19

2= 0.60 A (38)

Having calculated the ripple current average and RMS value, we can proceed to the calcu-lation of the corresponding value for the output stage switches, i.e. for the transformer secondary.The RMS value of the secondary side current is found using:

Isw2,rms = I2,rms =√

I2out,rms + I2

fr,rms =√

3.542 + 0.692 = 3.61 A (39)

and its average value is:

Isw2,av = I2,av = Iout,av + Ifr,av = 3.18 + 0.60 = 3.78 A (40)

The RMS value of the reflected load and ripple current I1,rms is therefore:

I1,rms =I2,rms

n=

3.61

7= 0.52 A (41)

and the average primary current is:

I1,av =I2,av

n=

3.78

7= 0.54 A (42)

The RMS value of the magnetizing current Im,rms (assuming linear magnetization) is:

Im,rms =Im,max√

3(43)

27

and its average value is:

Im,av =Im,max

2(44)

where the peak value of the magnetizing current Imp is:

Im,max =Φmax

Lm=

Vin,max · DTs

2Lm(45)

From the parameters measurement of the transformer (to be designed in the next section)at different frequencies, it was determined that the magnetizing inductance at fs1 = 100 kHz isLm = 5.59 mH. With a switching period of Ts = 1/fs1 and a symmetrical duty ratio of D = 0.5,this yields a peak magnetizing current of:

Im,max =Vin,max · D

2Lmfs1=

325 · 0.52 · 5.59 · 10−3 · 100 · 103

= 0.145 A (46)

The magnetizing current RMS value in (43) becomes:

Im,rms =Im,max√

3=

0.145√3

= 0.084 A (47)

and its average value is:

Im,av =Im,max

2=

0.145

2= 0.073 A (48)

When (47) is compared with (41) it becomes obvious that the magnetizing current onlymarginally affects the system efficiency.

Finally, the input stage switches RMS current (34) is:

Isw1,rms =√

I21,rms + I2

m,rms =√

I21,rms + I2

m,rms =√

0.522 + 0.0842 =√

0.278 ≈ 0.53 A (49)

and its average value is:

Isw1,av = I1,av + Im,av = 0.54 + 0.073 ≈ 0.61 A (50)

At the beginning we made an assumption that the reflected load current has the samepositive direction throughout the whole period of the symmetrical modulating signal, so that twoMOSFETs are conducting essentially for half of the period followed by conduction of the twoantiparallel diodes for the other half. The conduction losses in the MOSFETs are:

Pcon1,T = 2

(

1

2RDSI2

sw1,rms

)

= RDSI2sw1,rms (51)

and in the diodes (VF = 0.6 V at IF = Isw1,av):

Pcon1,D = 2

(

1

2VF Isw1,av

)

= VF Isw1,av (52)

to give the total conduction losses in the input stage in excess of:

Pcon1 = Pcon1,T + Pcon1,D = RDSI2sw1,rms + VF Isw1,av (53)

Calculated MOSFETs’, diodes’ and total conduction losses are given in table 7.

28

IRF730 SPP11N60C3 BYV27-400

Pcon1,T/D [W ] 0.28 0.11 0.37

Pcon1 [W ] 0.65 0.48

Table 7: Conduction losses in the input stage

5.3.2 Switching losses

Switching losses at high switching frequencies and with the voltage levels in excess of severalhundreds of Volts can be quite severe. In this section, this will be analyzed in detail for the inputsection of the PWM master/slave DC-AC SICAM.

The transition process which was explained in the theoretical section about the input stageis rather complex. It was observed that the MOSFETs’ switching waveforms and power lossesare dependent on several nonlinear parameters in the same time: the output and input parasiticcapacitance of the MOSFETs, Miller charge, inserted dead time, as well as the magnetizing andreflected load current. The same problem can be solved in an approximative way, if the lossesassociated with the non-zero voltage and current during transition are separated from the lossesarising from the finite parasitic output capacitance.

First we will analyze the switching transitions and determine all the relevant time intervalsgiven in figure 13. Because of the specified positive current direction, when switching off theupper MOSFET load current I commutates to the lower freewheeling diode. Due to the pulsetransformers used to transfer the driving pulses to the gates of the MOSFETs, the gate drivecontinuously changes the sign VG = ±10 V. This leads to time intervals equations different fromthose given in [3]. However, it should be noticed that due to the leakage inductance of the pulsetransformer and the tracks used to connect them with the associated gate resistors and gate pinsof the MOSFETs, real switching time intervals can be significantly larger, as observed on theprototype. Therefore, the calculations made in this sections tend to be only approximative.

Figure 13: Switching transitions of the upper MOSFET in a switching leg: a) scheme and b) wave-forms

29

The time delay before rise tdr is found by solving the following exponential equation:

vg = −2VGe− t

RGCiss + VG

t = tdr =⇒ vg = VGS,th + Igfs

(54)

which results in:

tdr = RGCiss ln2VG

VG − VGS,th − Igfs

(55)

The time delay before fall tdf is found by solving the following exponential equation:

vg = 2VGe− t

RGCiss − VG

t = tdf =⇒ vg = VGS,th + Igfs

(56)

which results in:

tdf = RGCiss ln2VG

VG + VGS,th + Igfs

(57)

tdr and tdf represent the time delays from the moment the transition is initiated until themoment the corresponding transition is actually started and is visible as a change in the MOSFETvoltage/current. As obvious from the equations, these depend on the electrical characteristics of theMOSFET (Ciss, VGS,th, gfs), current I being switched, as well as the driving circuitry (VG, RG).

The rise time tr and the fall time tf on the other hand represent the time needed toaccomplish the desired transition of the switch voltage and are equal to the time the gate drivercurrent (±VG − vg)/RG needs to charge/discharge the Miller capacitance CGD:

tr = QGDRG

VG−VGS,th−I

gfs

tf = QGDRG

VG+VGS,th+ Igfs

(58)

When the reflected load current is positive, from the topology of the full-bridge in the inputstage, it is obvious that there will be one hard turn-on and turn-off for two diagonal MOSFETs andone soft (ZVS) turn-on and turn-off of the other two diagonal switches, clamped by the freewheelingdiodes. Hard switchings will cause switching loss, since the voltage across the switch and currentthrough the switch are non-zero for a short time interval (tr + tcr) during rise and (tf + tcf ) duringfall. tcr and tcf represent the time intervals for the switch current to rise/fall from 0/I to I/0correspondingly.

The current rise time interval tcr is found by solving the following exponential equation:

vg = (−VG + VGS,th)e− t

RGCiss + VG

t = tcr =⇒ vg = VGS,th + Igfs

(59)

which results in:

tcr = RGCiss lnVG − VGS,th

VG − VGS,th − Igfs

(60)

The current fall time interval tdf is found by solving the following exponential equation:

vg = (VG + VGS,th + Igfs

)e− t

RGCiss − VG

t = tcf =⇒ vg = VGS,th

(61)

30

which results in:

tcf = RGCiss lnVG + VGS,th + I

gfs

VG + VGS,th(62)

As already mentioned, switching losses are result of two effects: the first effect is the finitevoltage and current rise and fall time intervals associated with real switching elements, and thesecond one is the effect of the parasitic and nonlinear drain-to-source capacitance CDS of theMOSFETs. If we assume sinusoidal load current, than we can use its average value to calculatethe switching loss during one period of the modulating signal, i.e. I = Isw1,av.

The switching losses due to the finite time transitions of two MOSFETs in the full bridgeare found to be the area under the curve vsw · isw (triangle within a linear approximation) averagedin one switching period Ts = 1/fs1, i.e.:

Psw1,tr = 2 · 1

2fs1Vin,maxIsw1,av(tr + tcr + tf + tcf ) = fs1Vin,maxIsw1,av(tr + tcr + tf + tcf ) (63)

where the factor of 2 is obtained because of the two MOSFETs making a lossy switching transitions,two times per switching period (turn-on and turn-off).

The second term of the switching losses corresponding to the parasitic drain-to-source capac-itance CDS can be found by noticing that every switching period each of the MOSFETs’ parasiticoutput capacitances has been charged and discharged. Taking into account the nonlinear nature ofthe output capacitance CDC(V ), the energy lost during these transitions in each of the MOSFETsis given by (10). The total energy losses for the full bridge will be:

E = 4 · 2

3CossV

1

2ossV

3

2

DS =8

3CossV

1

2ossV

3

2

DS (64)

However, the idea behind the ZVS PWM inverter is to use the programmed delay to letthe reflected load and ripple current and the transformer magnetizing current to discharge theparasitic capacitances in a non-dissipative manner. We have already concluded that some additionalprimary side inductance is needed to achieve complete ZVS operation, but this will eventually limitthe available primary current slew rate. Therefore, we have intentionally decided to keep theinductance low by using only the one introduced naturally by the transformer, and cope with theincreased switching losses.

Let us take again a look at figure 5 and assume that both T1 and T4 are switching off atthe same time (simultaneous ZVS PWM). Although the turn-offs of T1 and T4 are both lossy, thereflected load current and the magnetizing current are charging the parasitic output capacitancesof these MOSFETs and in the same time discharging the parasitic output capacitances of T2 andT3. Therefore, when latter MOSFETs turn-on there is no associated power loss. The oppositeswitching transition is however lossy, since keeping the same current direction means that thereflected load current and the magnetizing current are freewheeling through D2 and D3. Parasiticoutput capacitances of T1 and T4 can now be discharged only by initiating their turn-on which willeventually dissipate the associated electrostatic energy.

So, by assuming that the primary current is positive I1 > 0, we conclude that this currentwill help discharge two of the output capacitances in the diagonal MOSFETs during the idlingperiod td,res, but leave the other two output capacitances unaffected when the switching back isperformed. If we assume that constant average switch current Isw1,av is flowing during the wholeidling period, the drain-to-source voltage of the two of the diagonal MOSFETs will be:

VDS,1 = Vin,max − Qrec

CDS= Vin,max − Isw1,avtd,res

43Coss

(65)

31

an for the other two diagonal switches:

VDS,2 = Vin,max (66)

This yields the final equation for the switching losses due to the finite parasitic outputcapacitance:

Psw1,cds = fs1

[

43CossV

1

2ossV

3

2

DS,1 + 43CossV

1

2ossV

3

2

DS,2

]

=

= fs1

[

43CossV

1

2oss(Vin,max − Isw1,avtd,res

4

3Coss

)3

2 + 43CossV

1

2ossV

3

2

in,max

] (67)

Total switching losses in the input stage are simply the sum of (63) and (67):

Psw1 = Psw1,tr + Psw1,cds (68)

For IRF730 and SPP11N60C3, the switching time intervals and the switching losses aregiven in table 8 for frequency fs1 = 100 kHz, gate resistance RG = 3.3 Ω and gate drive VG = ±10 V.

IRF730 SPP11N60C3

tdr [ns] 2.50 4.20

tdf [ns] 0.96 1.68

tr [ns] 10.69 10.48

tf [ns] 5.50 5.55

tcr [ns] 0.07 0.04

tcf [ns] 0.04 0.02

Psw1,tr [W ] 0.32 0.32

Psw1,cds [W ] 0.82 2.22

Psw1 [W ] 1.14 2.54

Table 8: Switching time intervals and switching losses in the input stage

From the results it is obvious that the switching losses at high switching frequencies areprevailing over the conduction losses. Moreover, faster MOSFETs (less parasitic capacitancesassociated with lower voltage MOSFETs) are having less switching losses due to the faster switchingtransitions, which means that putting MOSFETs with unnecessary higher voltage rating is likelyto worsen the efficiency.

5.3.3 Total losses in the input stage

Total losses in the input stage are found by summing the conduction and switching lossesin (53) and (68):

Ptot1 = Pcon1 + Psw1 (69)

Another interesting characteristic are the average MOSFET losses PinT,av, assuming thesame distribution of the losses throughout the full-bridge MOSFETs. The latter is obtained bysubtracting the diode conduction losses Pcon,D from the total losses Pin,tot and dividing it by 4:

P1T,av =Ptot1 − Pcon,D

4(70)

This quantity can be used to design the heat-sink.The results for the average MOSFET losses and total losses in the input stage are given in

table 9.

32

IRF730 SPP11N60C3

P1T,av [W ] 0.36 0.66

Ptot1 [W ] 1.79 3.02

Table 9: Average MOSFET losses and total losses in the input stage

5.4 Transformer design

As it was mentioned earlier, for this laboratory setup the transformer design was performedfor the lowest operation frequency fs1,min = 100 kHz, although it was desired later to run it at evenhigher frequencies. Some of the transformer specifications are already determined in the previoussections:

• transfer ratio n = V1/V2 = 7

• primary RMS current (41): I1,rms = 0.52 A

• secondary RMS current from (26) and (37): I2,rms =√

I2out,rms + I2

fr,rms = 3.60 A

If we neglect the losses in the output stage and in the output filter, and in the same timeallow losses in amount to 1% of the total transformed power, we arrive at the expected transformerloss of:

PTR,exp = 0.01Pout = 1 W (71)

When choosing the appropriate magnetic core, one should reconsider the power capacitywhich the transformer wound on that core can practically transfer, which is also connected withits thermal resistance and the allowed temperature rise over the ambient temperature. It wasdesired to build the transformer using an RM ferrite core which is capable of running at frequencieshigher than fs,min = 100 kHz without significant core losses. Therefore, H7C4 (similar to PC40)from TDK was chosen for core material, and two core sizes were considered: RM10 and RM12.Their power capacity Pmax, thermal resistance Rth as well as the expected temperature rise atPTR,exp = 1 W are given in table 10.

RM10 RM12

Pmax [W ] 173 366

Rth [K/W ] 45 29

∆T [K] 45 29

Table 10: Power capacity Pmax, thermal resistance Rth and expected temperature rise ∆T atPTR,exp = 1 W

Lacking the suitable data for the allowed temperature rise of TDK PC40 material andcomparing it with similar materials from other producers, it was decided that temperature riseup to ∆Tmax = 40 K should be tolerable. This eventually eliminated RM10, so that the finaltransformer is wound on RM12 transformer with PC40 core.

In order to determine the number of primary turns N1, the magnetic core and the copperlosses are determined as a function of N1 and their sum is subsequently optimized.

Core losses Pfe at certain frequency are given by the following equation [2]:

Pfe = kfe(∆B)βAelm = kfe(∆B)βVm = pfeVm (72)

33

where coefficients kfe and β are properties of the magnetic material, ∆B is the magnetic inductionswing, Ae is the equivalent cross area of the core perpendicular to the direction of the magneticfield, lm is the mean magnetic path length, pfe is the characteristic core loss (core losses per unitvolume) and Vm is the magnetic core volume.

Magnetic induction swing can be determined by noting that during the on-time of two ofthe diagonal MOSFET switches in the input stage, the magnetic induction B increases twice thevalue of the magnetic inductance swing ∆B:

∆B =λ

2N1Ae=

VgDTs

2N1Ae(73)

where λ is flux linkage and N1 is the number of primary turns.Equation (73) is put into (72) to obtain:

Pfe = kfe

(

VgDTs

2N1Ae

)β

Vm (74)

Some of the quantities which appear in (72) are tabulated in table 11. Coefficients kfe andβ are determined from the diagram of the power losses for the PC40 material for two points ∆B =100, 200 mT at fsin = 100 kHz (sinusoidal excitation), and averaging between core temperaturesof 23 C and 100 C. Duty cycle is symmetrical D = 0.5 and applied voltage is Vg = Vin,max.

kfe [kW/Tm3] β Ae [mm2] Vm [mm3] MLT [mm] Wa [mm2]

47.05 ·103 2.81 147.5 6195 61 73

Table 11: Characteristic values for RM12 with PC40 material

Copper losses are easily calculated using [2]:

Pcu = kacρ(MLT )N2

1 I2tot

Waku(75)

where kac is the lumped increase of the DC resistance due to skin and proximity effect (the primaryand the secondary side together), ρ = 23 ·10−9Ωm is the characteristic resistance of copper, (MLT)is the mean length of a turn, Wa is the core window area, Itot =

∑

NjIj/N1 is the total currentreferred to the primary, ku is the filling factor of the core window area. The AC resistance factoris initially set to kac = 3, to account for extra resistance when the copper winding is exposed to analternating electromagnetic field. The filling factor is chosen to be ku = 0.5, due to the additionalinsulation layers between the windings. Some of the quantities in (75) are given in table 11.

Total transformer losses PTR equal to:

PTR = Pfe + Pcu = Pfe + Pcu1 + Pcu2 (76)

A small program in MATLAB was written to calculate core losses Pfe, copper losses Pcu andtotal losses PTR as a function of the primary number of windings N1, as well as give the diameterof the copper wire and number of layers for the primary and secondary (forcing the same copperarea), after the initial number of primary turns N1 has been chosen. The resulting graph is givenin figure 14. The latter yields total transformer losses within the specified range of 1 W.

In order to obtain a secondary winding with an integer number of turns N2, primary numberof turns was chosen to be N1 = 56 resulting in N2 = 8. The other results from the MATLABprogram as obtained in the command window are:

34

0 10 20 30 40 50 60 70 80 90 1000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Number of primary turns N1

Loss

es P

[W]

Core losses Pfe

, copper losses Pcu

and total losses Pfe

+Pcu

PfePcuPfe+Pcu

Pcu

Pfe

Pcu

+Pfe

Figure 14: Core losses Pfe, copper losses Pcu and total losses PTR as a function of the primarynumber of turns N1

>> transformer_2w

Enter the primary number of turns?56

Secondary winding has 8 turns

Primary winding wire diameter: 0.644158 mm

Secondary winding wire diameter: 1.70428 mm

Primary winding in: 4.16729 layers

Secondary winding in: 1.44343 layers

A goal was set to reduce the skin and proximity effect losses by interleaving both windings.Therefore, it seemed logical to reduce the proposed wire diameter and manage to put the primarywinding in 4 layers and secondary winding in 1 layer, so interleaved in two sections we get effectively2 layers of primary winding and 1/2 layer of secondary winding. So finally, the transformer wasmade with the following specification:

• primary winding: N1 = 56 turns with copper wire diameter d1 = 0.6 mm (Irms = 1.53 A atcurrent density J = 600 A/cm2), interleaved in 2 layers,

• secondary winding: N2 = 8 turns with copper wire diameter d1 = 1.1 mm (Irms = 4.88 Aat current density J = 600 A/cm2), single layer, but effectively interleaved half layer forcalculating the kac2 factor.

The rest of the MATLAB program necessitates use of the kac = Rac/Rdc table for eddycurrent losses in [27], to calculate the core lossesPfe in (74) and the separate copper losses in theprimary and secondary windings:

Pcu1 = 4kac1ρ(MLT )N1

πd2

1

I21,rms

Pcu2 = 4kac2ρ(MLT )N2

πd2

2

I22,rms

(77)

The rest of the program in the MATLAB command window, stating the calculated lossesat fs1,min = 100 kHz, goes like this:

35

Enter the primary winding wire diameter [mm]?0.6

Enter the secondary winding wire diameter [mm]?1.1

Enter the operating frequency [Hz]?100000

Penetration depth: Dpen= 0.237171 mm

Primary winding layer thickness/penetration depth: Q1=lt1/Dpen= 2.09975

Secondary winding layer thickness/penetration depth: Q2=lt2/Dpen= 3.84955

kfe [W/Tm^3] for the core at specified frequency?47.05e+6

beta for the core at specified frequency?2.81

kac1 as found in table/graph?5

kac2 as found in table/graph?1.7

Core losses: Pfe= 0.398561 W

Primary copper losses: Pcu1= 0.367479 W

Secondary copper losses: Pcu2= 0.260211 W

Total losses: Ptr= 1.02625 W

The same calculation performed for switching frequency of, for example fs1 = 200 kHz,reveals two times higher losses:

Enter the primary winding wire diameter [mm]?0.6

Enter the secondary winding wire diameter [mm]?1.1

Enter the operating frequency [Hz]?200000

Penetration depth: Dpen= 0.167705 mm

Primary winding layer thickness/penetration depth: Q1=lt1/Dpen= 2.9695

Secondary winding layer thickness/penetration depth: Q2=lt2/Dpen= 5.44408

kfe [W/Tm^3] for the core at specified frequency?95.65e+6

beta for the core at specified frequency?2.64

kac1 as found in table/graph?9

kac2 as found in table/graph?3

Core losses: Pfe= 1.20752 W

Primary copper losses: Pcu1= 0.661462 W

Secondary copper losses: Pcu2= 0.459197 W

Total losses: Ptr= 2.32818 W

Summary of the transformer losses at switching frequency fs1 = 100 kHz is given in table 12.

Pfe [W ] Pcu1 [W ] Pcu2 [W ] Pcu [W ] PTR [W ]

0.40 0.37 0.26 0.63 1.03

Table 12: Transformer losses

From the presented calculations, it is obvious that some transformer optimization is neededin order to get within the power losses target band PTR,exp < 1 W, by reducing the layer thickness(thinner wire), using Litz wire (paralleling of several copper threads into a single wire), changingPC40 for some other HF ferrite core material with lower core losses etc. At this stage of the projectand for this internal report, transformer optimization is out of the scope and will be left for nearfuture.

5.5 Output stage

Concerning the current levels given in (39) and (40), the MOSFETS in figure 11 are chosento be IRF520 from the HEXFET PowerMOSFET family of International Rectifiers and the diodes

36

are ultra fast rectifiers MUR820 from On Semiconductor. Their electrical characteristics are givenin tables 13 and 14, correspondingly.

VDSS [V ] ID [A]/25 RDS,on [Ω] Ciss [pf ] Coss [pf ] QGD [nC]VDS=80V gfs [S] VGS,th [V ]

100 9.2 0.27 360 150 7.7 2.7 3

Table 13: Short summary of the electrical characteristics of IRF520

VR [V ] IF (AV ) [A] VF,max [V ] IR [µA] trr [ns]

200 8 0.98 5 35

Table 14: Short summary of the electrical characteristics of MUR820

Since the secondary bidirectional bridge is implemented as a full-bridge topology, in eachswitching action two diagonal MOSFETs supporting the same current direction are turned on/offtogether. This necessitates 4 pulse transformers and two gate drivers TC4427, for the followingcombinations of switches: 1&6, 2&5, 3&8 and 4&7. Gate drivers for the MOSFETs in the outputstage are made using pulse transformers wound on four small ferrite (N30) 12.5x7.5x5 ring cores.Cores are assembled with 6 turns 0.35 mm copper wire on the primary and two secondaries with 8turns 0.35 mm copper wire. Gate resistance was chosen the same as in the input stage RG = 3.3 Ω.

5.6 Expected losses in the output stage

5.6.1 Conduction loss

At the beginning we will make a similar assumption as in the input stage analysis, i.e. wewill adopt positive direction of the load current throughout the whole period of the symmetricalmodulating signal, so that two diagonal MOSFETs and series diodes are conducting for half of theperiod followed by conduction of the other two diagonal MOSFETs and series diodes supportingthe same current direction for the other half. The conduction losses in the MOSFETs are:

Pcon2,T = 4

(

1

2RDSI2

sw2,rms

)

= 2RDSI2sw2,rms (78)

and in the diodes (VF = 0.72 V at IF = Isw2,av):

Pcon2,D = 4

(

1

2VF Isw2,av

)

= 2VF Isw2,av (79)

to give the total conduction losses in the output stage in excess of:

Pcon2 = Pcon2,T + Pcon2,D = 2(RDSI2sw2,rms + VF Isw2,av) (80)

Calculated MOSFETs’, diodes’ and total conduction losses are given in table 15.

IRF520 MUR820

Pcon2,T/D [W ] 7.04 5.44

Pcon2 [W ] 12.48

Table 15: Conduction losses in the output stage

37

Conduction losses presented in table 15 show that the output stage bidirectional bridge withits 4QSWs built with series rectifiers is likely to be the most lossy element of the whole system,which is totally unacceptable. This has been already forecasted in the theoretical section of thisreport and there is a strong hope that the efficiency will drastically improve with the introductionof bidirectional bridge built from MOSFETs only.

5.6.2 Switching losses

The switching sequence in the output stage of a master/slave PWM DC-AC SICAM repre-sents a voltage controlled commutation. This means that, by knowing the correct input voltage ofthe bidirectional bridge, 4QSW switches in the corresponding legs are turned on and off in a waythat provides an uninterrupted load current path. This is similar to the input stage, where becauseof the unipolar input voltage, simple diodes can be used for freewheeling action. The latter resultsin two lossy turn-ons and turn-offs of the MOSFETs which are carrying the unidirectional andpositive reflected load current in the input stage (a suitable assumption). So, the same situationwill happen in the output stage, when unidirectional, positive load current Isw2 > 0 (ripple currentincluded) is assumed. Let us return to figure 11 and suppose that positive input voltage is appliedon the lower rail, while T1D1T6D6 are conducting the positive load current. Desired output voltageis for example positive, so the bidirectional bridge will switch to connect the left end of the outputfilter to the lower rail and the right end of the output filter to the upper rail. Switching sequencewill be like the following:

• T5 and T2 will turn on to provide an alternative current path for a negative load current,without danger of short-circuiting the transformer secondary due to the applied negativevoltage. Since the load current is positive Isw2 > 0, D2 and D5 will not conduct, so they willtake the whole applied input voltage across them and make the turn-on of T5 and T2 lossless(ZCS).

• Now the previous path for a negative load current can be cancelled, so MOSFETs T3 and T8,which are not carrying any current are turned off, also in a lossless manner.

• Since there is no possibility of creating a short-circuit of the transformer secondary anymore,MOSFETs T4 and T7 are turned on. They conduct when the load current is positive, so theywill take away the load current from T1 and T6, which results in a lossy turn-on.

• After the previous current commutation has ended, T1 and T6 can be turned off without anyadditional switching losses (ZCS).

A similar switching sequence will occur when switching back to the beginning state, resultingin another two lossy turn-ons when the load current is commutated back to T1 and T6. This makesa total of four lossy turn-ons per switching interval. Of course, there is an additional switching lossbecause the output stage will perform a switching transition with a frequency of fs1, whenever theinput stage changes the transformer voltage polarity. Therefore, the switching losses due to finitetime transitions Psw2,tr will amount to:

Psw2,tr = 4 · 1

2(fs1 + fs2)V2,maxIsw2,av(tr + tcr) = 2(fs1 + fs2)V2,maxIsw2,av(tr + tcr) (81)

where the switching time intervals are given with the same equations from the input stage sectionand I = Isw2,av.

The switching loss mechanism regarding the finite parasitic capacitances of the MOSFETCDS and the series diode CD is far more complex in the case of the bidirectional bridge. Let usdetermine the energy which is lost because of these parasitic capacitances in a switching actionsimilar to the above case of a positive load voltage Isw,av and negative rail voltage −V2,max, whileT1 and T6 are conducting:

38

• When T2 and T4 are turned off, the voltage drop across their combination with the seriesdiodes D2 and D4 is (neglecting the voltage drop across the upper switch in the leg):

VT2+D2= VT4+D4

= V2,max (82)

where both voltages are referenced to the upper end. Diode D4 is forward biased and thevoltage across it is approximately 0 V, which causes the input voltage to be blocked solely bythe turned-off MOSFET T4:

VT4= V2,max (83)

On the other hand D2 is reverse biased, so the voltage drops across T2 and D2 are determinedusing a capacitive divider:

VT2=

ZT2

ZD2+ZT2

V2,max =1

sCT21

sCD2

+ 1

sCT2

V2,max =CD2

CT2+CD2

V2,max

VD2= V2,max − VT2

=CT2

CT2+CD2

V2,max

(84)

Both parasitic capacitances CT2and CD2

are depletion dependent, i.e. they decrease withthe increase of the reverse voltage, like stated in the equation (7):

CT2= Coss

(

Voss

VT2

)n

CD2= CDt

(

VDt

VD2

)n (85)

where CDt is the diode parasitic capacitance at some test reverse voltage VDt. For MUR820,CDt = 90 pF at VDt = 10 V. Assuming n=1/2, energies stored in T2, D2 and T4 are foundusing (10):

ET2= 2

3CossV1

2ossV

3

2

T2

ED2= 2

3CDtV1

2

DtV3

2

D2

ET4= 2

3CossV1

2ossV

3

2

2,max

(86)

(86) can be used to derive the equivalent MOSFET and diode capacitance when comparedwith the energy equation E = 1/2 · CeV

2:

CT2= 4

3Coss

CD2= 4

3CDt

(87)

• T2 is turned on and the energy associated with its parasitic output capacitance ET2is dissi-

pated. The whole input voltage drops across the diode D2 and the stored energy is increasedto:

E′D2

=2

3CDtV

1

2

DtV3

2

2,max (88)

• T3 is turned off without any effect on the switching process.

• T4 is turned on and the voltage across the series connection of MOSFETs and diodes T2/D2

and T4/D4 is brought to near zero. Thus, the energy associated with the charged parasiticcapacitances ET4

and E′D2

is dissipated.

39

• T1 is turned off and the current commutates to T4.

The maximum switching loss in the output section, caused by switching of the outputsection (therefore index 2) Psw2,cds2,max is obtained by averaging the losses in one switching periodof the output section Ts2 = 1/fs2 and multiplying it by 4 similar switching actions per one switchingperiod:

Psw2,cds2,max = 4fs2(ET2+E′

D2+ET4

) = 4fs2

(

2

3CossV

1

2ossV

3

2

T2+

2

3CDtV

1

2

DtV3

2

2,max+2

3CossV

1

2ossV

3

2

2,max

)

(89)

The minimum switching loss in the output section, caused by switching of the output sectionPsw2,cds2,min is obtained when the MOSFET which is first turned on immediately starts to conductthe load current and discharges all of the associated parasitic inductances:

Psw2,cds2,min = 4fs2(ET2+ED2

+ET4) = 4fs2

(

2

3CossV

1

2ossV

3

2

T2+

2

3CDtV

1

2

DtV3

2

D2+

2

3CossV

1

2ossV

3

2

2,max

)

(90)

It makes sense to average the switching losses in (89) and (90), since one can not know inadvance which of them will prevail:

Psw2,cds2 =Psw2,cds2,max + Psw2,cds2,min

2(91)

Another switching loss due to the parasitic output capacitances of the MOSFETs anddiodes, originates from the input stage switching. Due to the master/slave operation of this SICAM,4QSW switches which are turned off and are already charged to certain voltage will experienceadditional losses when the input voltage to the bidirectional bridge reverses. The switching loss inthe input section, caused by switching of the input section Psw2,cds1 is obtained in a similar mannerlike (90), but it is proportional to the switching frequency of the input stage fs1:

Psw2,cds1 = 4fs1(ET2+ED2

+ET4) = 4fs1

(

2

3CossV

1

2ossV

3

2

T2+

2

3CDtV

1

2

DtV3

2

D2+

2

3CossV

1

2ossV

3

2

2,max

)

(92)

Total switching losses in the output stage are simply the sum of (81), (91) and (92):

Psw2 = Psw2,tr + Psw2,cds1 + Psw2,cds2 (93)

For IRF520, the switching time intervals and the switching losses are given in table 16for frequency fs1 = 100 kHz and fs2 = 200 kHz, gate resistance RG = 3.3 Ω and gate driveVG = ±10 V.

5.6.3 Total losses in the output stage

Total losses in the output stage are found by summing the conduction and switching lossesin (80) and (93):

Ptot2 = Pcon2 + Psw2 (94)

Another interesting characteristic are the average MOSFET losses P2T,av and average diodelosses P2D,av, assuming the same distribution of the losses throughout the bidirectional full-bridgeMOSFETs and diodes:

P2T,av =Pcon2,T + 1

2Psw2

8

P2D,av =Pcon2,D+ 1

2Psw2

8

(95)

40

IRF520

tdr [ns] 1.51

tdf [ns] 0.39

tr [ns] 4.54

tf [ns] 1.76

tcr [ns] 0.27

tcf [ns] 0.02

Psw2,tr [W ] 0.49

Psw2,cds1 [W ] 0.09

Psw2,cds2,max [W ] 0.19

Psw2,cds2,min [W ] 0.17

Psw2,cds2 [W ] 0.18

Psw2 [W ] 0.76

Table 16: Switching time intervals and switching losses in the output stage

When calculating the average losses per MOSFET and diode, it was assumed that the switchinglosses are equally distributed among all the constitutive parts of the bidirectional bridge. Thesequantities can be used for designing the heat-sink.

The results for the average MOSFET and diode losses and total losses in the output stageare given in table 17.

IRF520 MUR820

P2T,av [W ] 0.93

P2D,av [W ] 0.73

Ptot2 [W ] 13.24

Table 17: Average MOSFET and diode losses and total losses in the output stage

5.7 Output filter design

The output filter starts with the analysis of a half circuit output filter, with half of the loadimpedance (resistance Rh), like shown in figure 15a. The transfer function Hh(s) of this half circuitis:

Hh(s) =(Rh|| 1

sCh)

sLh + Rh|| 1sCh

=

Rh

sCh

sRhLh + Lh

Ch+ Rh

sCh

=1

s2ChLh + sLh

Rh+ 1

(96)

There are different possibilities for choosing the output filter type, but the most commonare:

• Butterworth filter (2nd order):

Hh,But(s) =1

s2

ω2c

+√

2 sωc

+ 1(97)

where ωc is the filter cut-off angular frequency (-3 dB).

41

Figure 15: Output filter: a) half circuit and b) full circuit

• Bessel filter (2nd order):

Hh,Bes(s) =1

13

s2

ω2c

+ sωc

+ 1(98)

Like stated in [28], Butterworth design is characterized by maximally flat magnitude re-sponse in the frequency pass-band, and the attenuation in the transition frequency band is betterthan Bessel. However, in time domain Butterworth filter step response experiences some overshootand ringing and therefore Bessel filter is generally preferred.

Comparing (96) with (98) leads to the following results:

Lh

Rh= 1

ωc=⇒ Lh = Rh

ωc= Rh

2πfc

ChLh = 13ω2

c=⇒ Ch = 1

6πfcRh

(99)

The final values for the inductors Lf and the capacitor Cf of the full circuit output filtershown in figure 15 are found by recognizing that R = 2Rh, Cf = Ch/2 and Lf = Lh:

Lf = R4πfc

Cf = 16πfcR

(100)

In the design, the filter frequency was chosen to be fc = 30 kHz, which results in Lf =21.1 µH and Cf = 220 nF.

The most common material for building output filter inductor is Micrometals -2, which haslow permeability and low core loss. With its reference permeability of µ0,ref = 10, relative cost 2.7and core loss of 19 mW/cm3 at 100 kHz/14 mT, -2 material is appealing for the design because ofthe lower operating AC magnetic induction (B = µH) resulting in lower core losses.

For the power levels we are interested in, iron powder toroidal core T106-2 seemed like alogical choice. Some of the electrical and the mechanical characteristics of T106-2 found in [29] aregiven in table 18.

For the coupled inductor with inductance L = 2 · 21.1 = 42.2 µH the following number ofturns is needed:

N =

√

L

AL,T106−2=

√

42200

13.5= 56 turns (101)

This was implemented as two sections with N/2=28 turns.The wire diameter was chosen to be df = 0.7 mm.

42

AL [nH/N2] ID [mm] Ae [cm2] V [cm3] MLT [cm] N [turns]

T106-2 13.5 14.5 0.659 4.28 4.49 56

Table 18: Electrical and mechanical characteristics of T106-2, with the calculated number of wind-ings

5.8 Expected losses in the output filter

5.8.1 Copper losses

Copper losses in the coupled output filter inductor are found by multiplying the windingresistance RL with the square of the current RMS value I2

sw2,rms (load current + ripple current):

Pcu,Lf= RLf

Isw2,rms = Nρ(MLT )

πd2

f

4

I2sw2,rms (102)

where for T106 core (MLT)=44.9 mm/turn is found in table 18. This finally leads to:

Pcu,Lf= 4N

ρ(MLT )

πd2f

Isw2,rms = 4 · 56 · 23 · 10−9 · 44.9 · 10−3

π · (0.7 · 10−3)2· 3.612 = 1.96 W (103)

5.8.2 Core losses

To simplify the investigation of the core losses, we will again assume that we have zeromodulation and thus zero output power, resulting in maximum ripple current Ifr,max. This meansthat rectangular voltage with magnitude Vout,max and duty cycle D = 0.5 is applied to the filterinductor L, resulting in magnetic induction swing:

∆B =λ

2NAe=

Vout,maxDTs

2NAe=

Vout,max

4Nfs2Ae(104)

After the magnetic induction swing ∆B has been determined, one can proceed to the coreloss tables for material -2 in [29] to determine the corresponding specific core loss pfe. Then thetotal core loss is obtained by multiplying the specific core losses pfe with the core volume Vm:

Pfe,Lf= pfeVm (105)

The results of calculations for the designed output filter on core T106-2, are given in table 19.

∆B [mT ] pfe [mW/cm3] Pfe [W ]

T106-2 13.5 40 0.17

Table 19: Magnetic induction swing and core losses for T106-2

It is obvious that the core losses are only a small fraction of the losses in the winding, dueto the low permeability and low core loss of the -2 material. However, it is a common practiceto tolerate even 20%/80% distribution between the copper and core losses, since in the inductorswound on toroidal iron powder cores, the heat removal is far more easier from a single layer windingthan from the inner parts of the core itself. Using a similar material -14 with a little bit higherpermeability and higher loss can make the different loss contributions to reach the aforementionedgoal.

43

5.8.3 Total losses in the output filter inductor

The total losses in the output filter inductor are obtained by summing the copper and corelosses in equations (105) and (102):

PLf= Pcu,Lf

+ Pfe,Lf(106)

For our case, the result is:

PLf= Pcu,Lf

+ Pfe,Lf= 1.96 + 0.17 = 2.13 W (107)

5.8.4 Losses in the output filter capacitor

Calculation of the losses dissipated on the capacitor equivalent series resistance (ESR) isvery hard without making assumptions, like assuming that the whole HF ripple current Ifr,rms isflowing entirely through the capacitor, leaving the LF modulated current flow through the load.The ESR can be found using the tangent of loss angle tan δ supplied by the manufacturer

ESR = tan δ · XC =tan δ

2πfC(108)

Output filter capacitor with capacitance value of C = 220 nF, was chosen to be polyesterfrom Philips due to the low tangent of loss angle tan δ. For C = 220 nF and frequency f = 100 kHz(highest frequency available data), the tangent of loss angle tan δ ≤ 225 · 10−4 leading to thefollowing worst case ESR:

ESR =tan δ

2πfCf=

225 · 10−4

2π · 200 · 103 · 220 · 10−9= 0.081 Ω (109)

The losses in the capacitor ESR due to the filter ripple current Ifr,rms are:

PCf= (ESR) · I2

fr,rms = 0.081 · 0.692 = 0.04 W (110)

which is negligible, and is well bellow the maximum allowed power dissipation PCf ,max = 60 mWfor a polyester capacitor with maximum width bmax = 4 mm and maximum length lmax = 12.5 mm.

5.8.5 Total losses in the output filter

Total losses in the output filter represent a sum of the losses in the filter inductor (107) andfilter capacitor (110):

Ptot,f = PLf+ PCf

= 2.13 + 0.04 = 2.17 W (111)

5.9 Simple power supply

In order to properly design the simple power supply, it is necessary to know the correctvalue of the power supplied to the input stage Pis, which represents a sum of the output powerPout and all of the losses encountered till now:

Pis = Pout + Ptot,f + Ptot2 + PTR + Ptot1 (112)

Results are given in Table 20.One of the ”rules of thumb” found in [6] says that for a full-wave bridge-rectified capacitor

input filter, the minimum specific capacitance is 1.5 µF/W, which gives a minimum total filtercapacitance of C = 169 µF and C = 171 µF for an input stage with IRF730 and SPP11N60C3,correspondingly. To improve performance, the filter capacitor is chosen to be aluminium electrolyticC = 470 µF/400 V from BC Components’ 198 PHR-SI series.

Input rectifier is chosen to be full-bridge B250C5000/3300 with a recommended input volt-age of Vrms = 250 V and rectified output current of Io = 5 A, which will certainly satisfy ourneeds.

44

IRF730 SPP11N60C3

Pis [W ] 118.23 119.46

Table 20: Power supplied to the input stage

5.9.1 Expected losses in the power supply

The losses in the filter capacitor depend on the capacitor ESR and its ripple current RMSvalue ICr,rms, which is on the other hand dependant upon the capacitor value C, total seriesresistance Rs lumped just before the capacitor, supplied power Pis (load+losses) and the inputvoltage RMS value Vin,rms.

The effective input current Ie, which represents the ”real” component of the input currentto satisfy the input stage power demand is:

Ie =Pis

Vin,rms(113)

Assuming effective input resistance of Rs = 0.5 Ω, this will give certain resistance factorRsf :

Rsf = RsPis (114)

Using the diagram at Fig.1.6.5 in [6], the capacitor ripple current RMS ICr,rms value canbe easily determined. Then, the power dissipated in the capacitor ESR is simply:

PC = (ESR) · I2Cr,rms (115)

where the ESR of the chosen capacitor is typically ESR = 0.215 Ω.Using the diagram at Fig.1.6.4 and Fig.1.6.6 in [6], the input RMS current Iin,rms and the

peak input current Iin,peak can be easily determined. These should help choosing rectifier diodeswith a proper rating, which is satisfied in our case.

Using the diagram at Fig.1.6.7 in [6], the mean DC (average) output voltage Vo,av of afull-wave bridge-rectified capacitor input filter can be found. If we suppose that the average powersupply current Io,av is provided solely by the rectifier and the ripple current ICr is flowing entirelythrough the filter capacitor (harsh approximation), we can determine Iin,av by assuming almostripple free capacitor filter voltage VC = Vo,av:

Iin,av = Io,av =Pis

Vo,av(116)

The power losses in the full-bridge rectifier are found using:

Prect = 2VF Iin,av (117)

where VF is the forward voltage drop per element (VF = 0.76 V at Iin,av = 0.38 A).The total power losses in the power supply represent a sum of (115) and (117):

Pps = PC + Prect (118)

Results of the power supply loss analysis at 100% output power are given in table 21.

45

IRF730 SPP11N60C3

IE [A] 0.51 0.52

Rsf [ΩW ] 59.04 59.65

ICr,rms [A] 0.67 0.68

Iin,rms [A] 0.80 0.82

Iin,peak [A] 2.40 2.45

Vo,av [V ] 312.8 312.8

Iin,av [A] 0.38 0.38

PC [W ] 0.10 0.10

Prect [W ] 0.54 0.56

Pps [W ] 0.64 0.66

Table 21: Power supply loss analysis

5.10 SICAM losses and efficiency

Finally, the power losses Plosses, input power Pin and the converter efficiency η can be foundusing:

Plosses = Pps + Ptot1 + PTR + Ptot2 + Ptot,f

Pin = Pout + Plosses

η = Pin

Pout

(119)

and results together with all of the previously calculated losses are given in table 22.

IRF730 SPP11N60C3

Pps [W ] 0.64 0.66

Ptot1 [W ] 1.79 3.02

PTR [W ] 1.03 1.03

Ptot2 [W ] 13.24 13.24

Ptot,f [W ] 2.17 2.17

Plosses [W ] 18.87 20.12

Pin [W ] 118.87 120.12

η [%] 84.1 83.3

Table 22: Review of the SICAM losses and the final input power and efficiency

Comments regarding the power losses, efficiency and possible improvements:

• During the analysis of the power losses, it became apparent that the main sources of lossesare the switching action of the input stage, due to the high input voltage, and the conductionlosses in the output stage, due to the large load current. Therefore, further increase of theinput voltage to the input stage with some boost conditioning stage for PFC, should beavoided, although it makes better use of the input filter capacitor (higher energy storage).Even more, different PFC conditioning stages which produce lower DC output voltage canbe incorporated at the SICAM entrance to provide lower switching loss of the subsequentinput stage. This may result in significant efficiency improvement with the right choice ofMOSFET components. Due to the inherent nonlinearity of the output stage series diodes

46

and the excessive conduction loss associated with their voltage drop, future investigationmust focus on avoiding the presented ”MOSFET+series diode” 4QSW and moving to ”2series MOSFETs” 4QSW.

• The full-bridge topology in the input stage and the full-bridge topology in the output stageshould be used at power levels above, for ex. P = 250 W, where higher loss doesn’t affect theefficiency so much and some of the SICAM components (ex. transformer secondary in a singlewinding, secondary switches with lower voltage rating) should be used up to their limits. Itis obvious from the previous power loss analysis for the output power of P = 100 W, that ifthe input stage is turned to half-bridge with capacitors in the other leg, and the output stageis built as a half-bridge with a tapped transformer secondary, near half of the losses in theinput stage and output stage could be recovered, on expense of little higher transformer lossesand increasing the voltage blocking capability of secondary side switches. This will certainlyboost the overall efficiency above 90%.

• Power loss in the MOSFET drivers and pulse transformers, although substantial, was notpresented in this report. The reason for this is that another auxiliary supply was used forpowering the control circuitry and the drivers. In the final prototyping stage, when theSICAM should be self-contained and capable of operation without any external assistance,these losses will be included in the analysis.

• Careful PCB design is of prime interes in these high speed application. The full bridge atthe secondary side necessitates 8 MOSFETs and 8 diodes in TO220 packages, which occupysignificant part of the whole PCB. Therefore, additional wiring inductance is experiencedbetween the switches, which results in severe ringing during the commutation of the bothinput and output stage, due to the parasitic charge displace. Making the PCB in two layersonly causes unnecessary long wiring of the gate circuitry, which increases the inductance ofthe latter and extends the switching times (increased switching losses).

The power circuit schematics is given in figure 16.

6 Open-loop control

The open-loop control circuit schematics is given in figure 17.In order to obtain symmetrical pulses (duty cycle D=0.5) for driving the input stage switches

timer/oscillator NE555 is used to create rectangular pulses with twice the frequency of the inputstage 2fs1. These pulses are fed into a JK flip-flop 74LS73 with both inputs wired permanentlyhigh, to result in symmetrical driving pulses for the input stage with frequency fs1. However, thedriving pulses are not immediately transferred to the driving circuitry, but are brought to 4-bitbistable latches with enable 74LS75, to gain control over the switching of the input stage. Transferof driving pulses to the driving circuitry is enabled as soon as it is concluded that the master/slaveline is not occupied (output stage is not requesting a transition). Quadruple S−R latches 74LS279are used to bring down the master/slave line and release it when the transition is over, helped byBC546B NPN transistor.

PWM for the output stage is created by comparing the triangular carrier at frequency fs2

created by the triangular wave generator built around MC33078 opamp (AD826 for higher fs2)with the reference signal using the AD790 comparator. Again, this signal is latched by 74LS75 andallowed through when no transition is performed by the input stage. The same circuitry is usedfor occupying and releasing the master/slave line.

The most complex part of the algorithm is the creation of the right commutation sequence,and this is performed by a bunch of Schmitt trigger inverters (74LS14), NAND (74LS00), AND

47

Figure 16: Power circuit schematics of the master/slave PWM SICAM48

Figure 17: Open-loop control schematics of the master/slave PWM SICAM

49

(74LS08), NOR (74LS02) and S − R flip-flops (74LS279). R-C-Diode combination are trimmedto provide delay times between the transitions of around 200ns, which should be certainly enoughto commutate the load current, although the gating signals and switching transitions are sloweddown by the leakage inductances of the pulse transformers and the wiring on the PCB. The correctcommutation sequence depends on the transformer secondary side voltage polarity, so the drivingsignals from the input stage are utilized to determine it (because of the master/slave operation, wedon’t need to measure the actual voltage polarity, since out of the transitions this must correspondto the driving pulses of the input stage MOSFETs).

7 Closed-loop control

The block diagram of the closed-loop control is presented in figure 18. Each of the transferfunctions will be analyzed in the following sections.

Figure 18: Block diagram of the closed-loop control

7.1 Reference shaper transfer function R(s)

As the name says, this front element of the SICAM is used for shaping the reference signal,which certainly helps improve the performance of the whole system. Usually it is chosen to besecond order filter [3]:

R(s) =1

1 + sQrωr

+ sω2

r

(120)

which compared to the Bessel filter (98) gives:

ωr =√

3ω

Qr = 1√3

(121)

For this design, cut-off frequency was selected fr = 40 kHz, which results in:

ωr = 2πfr = 251.3 · 103 rads

Qr = 1√3

= 0.577(122)

The Bode diagram of the reference shaper transfer function R(s) is depicted in figure 19.

50

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−40

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−10

0

10

20

Mag

nitu

de (d

B)

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105

106

107

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−135

−90

−45

0

Pha

se (d

eg)

Reference shaper R(s)

Frequency (rad/sec)

Figure 19: Bode diagram of the reference shaper transfer function R(s)

7.2 PWM modulator + amplifier transfer function Ga(s)

The easiest way to construct the PWM modulator + amplifier transfer function Ga(s) is toneglect any associated dynamics (delays, rises/falls, nonlinearities etc.) and use simple gains Kpwm

and Ka to represent the transfer functions of the PWM modulator and the power amplifier:

Ga(s) = KpwmKa (123)

If Vout,max is the maximum value of the output stage voltage and Vtr is the peak value ofthe triangular carrier, the aforementioned gains are given with the following expressions:

Kpwm = 1Vtr

Ka = Vsm

(124)

which gives the final form of the approximate PWM modulator + amplifier transfer function Ga(s):

Ga(s) =Vout,max

Vtr(125)

In our case Vout,max = 40 V and Vtr = 2 V resulting in:

Ga(s) = 20 (126)

7.3 Output filter transfer function Gf (s)

The transfer function of the output filter Gf (s) shown in figure 15b is similar to (96):

Gf (s) =1

1 + s2Lf

R + s22LfCf

(127)

where Lf = 21 µH, Cf = 220 nF, R = 8 Ω and the cut-off frequency ωc is given with:

ωc = 2πfc =1

√

2LfCf

(128)

The Bode diagram of the output filter transfer function Gf (s) is depicted in figure 20.

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0

10

20

Mag

nitu

de (d

B)

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105

106

107

−180

−135

−90

−45

0

Pha

se (d

eg)

Transfer function of the output filter Gf(s)

Frequency (rad/sec)

Figure 20: Bode diagram of the output filter transfer function Gf (s)

7.4 Voltage feedback transfer function Hfb(s)

In the case of feeding back the output voltage after the output filter, the usual way [3] isto implement a feedback with no dynamics and with a gain which brings the output voltage downto the level of the reference voltage:

Hfb(s) =1

Ga(s)=

1

KpwmKa(129)

Regarding the equation (126), Hfb(s) is given with the following expression:

Hfb(s) =1

Ga(s)= 0.05 (130)

7.5 Compensator transfer function Gc(s)

The easiest way to construct the compensator transfer function Gc(s) is to use Bode sta-bilization criterion and determine Gc(s) in order to have proper phase margin φm and amplitudemargin Am of the open-loop transfer function L(s):

L(s) = Gc(s)Ga(s)Gf (s)Hfb(s) (131)

The open-loop transfer function L(s) before any compensation is performed (Gc(s) ≡ 1) isgiven in figure 21.

Shaping starts by choosing the desired crossover frequency of L(s), for example:

fco = 80 kHz

ωco = 2πfco = 502.65 · 103 rads

(132)

We can proceed by putting some large gain in the compensator Gc(s) = Kc1, for exampleKc1 = 100 equivalent to 40 dB. The resulting open-loop transfer function L(S) is given in figure 22.

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20

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nitu

de (d

B)

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105

106

107

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0

Pha

se (d

eg)

Open−loop transfer function L(s) before compensation

Frequency (rad/sec)

Figure 21: Bode diagram of the open-loop transfer function L(s) before compensation

It can be seen in figure 22, that we need around -30 dB compensator gain at ωco to makethe crossover. Since this can not be achieved with one pole, we will put a double pole at angularfrequency ωp1, which will cause -15 dB each. The resulting compensator transfer function Gc1(s)is:

Gc1(s) = Kc1

(

1 + sωz1

1 + sωp1

)2

(133)

Since putting a pole at ωco/10 will cause attenuation of −20 dB at ωco, one can write thefollowing relations for the frequency ωp1:

log ωco−log ωco10

log ωco−log ωp1= 20

15

log ωp1 = log ωco − 34(log ωco − log ωco

10 )

(134)

which for our case is equal to ωp1 = 89.39 · 103 rad/s and we put a double zero at ωz1 = 2ωco =1.005 · 106 rad/s. The resulting open-loop gain transfer function is given in figure 23.

At the end, we need to make a lead (PD) compensator with a transfer function Gc2, whichwill improve the phase margin at the desired cross-over frequency ωco and in the same time keep itunchanged:

Gc2(s) = Kc2

1 + sωz1

1 + sωp1

(135)

where from [2]:

ωz2 = ωco

√

1−sin θ1+sin θ

ωp2 = ωco

√

1+sin θ1−sin θ

Kc2 =√

ωz2

ωp2

(136)

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−20

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0

10

20

30

40

50

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Mag

nitu

de (d

B)

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105

106

107

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−135

−90

−45

0

Pha

se (d

eg)

Open−loop transfer function L(s) with a pure gain compensator Gc(s)=100

Frequency (rad/sec)

Figure 22: Bode diagram of the open-loop transfer function L(s) with compensator Gc(s) = 100

where θ represents the phase improvement.For our case desired phase margin is φm = 30 deg, which gives θ = 75 deg, so the frequencies

ωz2, ωp2 and Kc2 are:

ωz2 = 66.18 · 103 rads

ωp2 = 3.8180 · 106 rads

Kc2 = 0.1317

(137)

The complete compensator transfer function is:

Gc(s) = Gc1(s)Gc2(s) (138)

and the final open-loop transfer function L(s) is given in figure 24.The closed loop transfer function B(s) is:

B(s) = R(s)Gc(s)Ga(s)Gf (s)

1 + L(s)(139)

and is given in figure 25.The closed-loop control circuit schematics is given in figure 26.The photographs of the master/slave PWM DC-AC SICAM without and with the closed-

loop control board included are given in figures 27 and 28 correspondingly.

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B)

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105

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108

−270

−225

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0

Pha

se (d

eg)

Open−loop transfer function L(s)

Frequency (rad/sec)

Figure 23: Bode diagram of the open-loop transfer function L(s) with compensator Gc1(s) =

Kc(1+s/ωz1

1+s/ωp1)2

−100

−50

0

50

Mag

nitu

de (d

B)

103

104

105

106

107

108

−180

−135

−90

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0

Pha

se (d

eg)

Open−loop transfer function L(s) − final

Frequency (rad/sec)

Figure 24: Bode diagram of the final open-loop transfer function L(s) with compensator Gc(s) =Gc1(s)Gc2(s)

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0

50

Mag

nitu

de (d

B)

103

104

105

106

107

108

−360

−315

−270

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−135

−90

−45

0

Pha

se (d

eg)

Closed−loop transfer function B(s)

Frequency (rad/sec)

Figure 25: Bode diagram of the closed-loop transfer function B(s)

56

Figure 26: Closed-loop control schematics of the master/slave PWM SICAM57

Figure 27: Photo of the master/slave PWM DC-AC SICAM prototype

Figure 28: Photo of the master/slave PWM DC-AC SICAM prototype with closed-loop control

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8 Measurements

In this section, the measurements performed on the master/slave PWM DC-AC SICAMwith SPP11N60C3 MOSFETs in the input stage will be presented.

8.1 Open-loop control

The first set of oscillograms is made with a positive reference signal higher than the trian-gular wave carrier, which means that the desired output voltage is maximum positive. This resultsin the output stage performing transition whenever the input stage makes a transition, leading tochange of the output voltage with regard to the polarity of the output stage rails.

In figure 29, the time diagrams of the driving signals for MOSFETs T1/T4 before and afterthe 74LS75 latch are shown, together with the latch enable signal and the resulting state of themaster/slave line (M/S). It is obvious that although master/slave line is free (”high”), the transitionof the input stage is delayed, which is obvious also from the latch enable signal, which is filteredthrough an R-C-Diode combination. This was done intentionally in order to leave some time forthe NPN transistor driving the master/slave line to completely bring it down to near zero Volts.Otherwise if this time is not long enough, as soon as the input stage transition is started the outputstage will start its own transition, since the master/slave line is sensed free (not brought successfullyand rapidly down by the input stage master/slave line driver).

Input stage M/S line driver base voltage, output stage M/S line driver base voltage, M/Sline voltage and input stage voltage polarity, which is essentially the T1/T4 driving signal out ofthe transition phases, are shown in figure 30. It is interesting to notice that, whenever the signalreference is not changed while the input stage is performing transition, the latter is followed by animmediate transition of output stage, just to conform with the signal reference. This can be seenfrom the base voltages of the M/S line drivers belonging to the input and the output stage, whichoccupy the M/S line immediately one after another.

The driving signal for the MOSFETs 2&5-4&7 before and after the latch, output stage latchenable signal and M/S line voltage are given in figure 31. Although this figure shows some resem-blance with figure 29, it should be pointed out that the signal 2&5-4&7 is not driving directly theMOSFETs, but this signal enters the commutation circuitry together with the information aboutthe polarity of the output voltage from the input stage to yield the safe commutation sequence. Itcan be also noticed from the figure, that the latch enable signal is not delayed by some RC combi-nation, since input stage transition is not correlated with the output stage transition, although wehave already seen that the opposite is true in figures 29 and 30.

The driving signals for the MOSFETs: 1&6, 2&5, 3&8 and 4&7 are given in figure 32,where the intentionally programmed delay of about 200 ns is easily observable. This transitionoccurs due to change of the output voltage of the input stage from negative to positive (upper railpositive), according to table 2 and starting from 2,5&4,7 turned on.

Again the driving signals for the MOSFETs: 1&6, 2&5, 3&8 and 4&7 are given in figure 33.This transition occurs due to change of the output voltage of the input stage from positive tonegative (upper rail negative), according to table 2 and starting from 1,6&3,8 turned on.

The driving signals for the MOSFETs in a larger time-scale are given in figure 34. Each ofthe depicted transitions is caused by the input stage changing its state, so it is basically with thefrequency of the input stage.

The following set of figures is made with a zero signal reference.The driving signals for the MOSFETs in a larger time-scale are given in figure 35, but with

a zero signal reference. Now the transitions are due to both the input stage switching and thePWM modulator output change. This can be better observed in figure 36, where the output stageline driver is bringing down the M/S line once after the input stage transition, and the second timebecause of the PWM modulator output (not correlated to the input stage event).

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Figure 29: 1) T1/T4 driving signal before the latch, 2) T1/T4 driving signal after the latch, 3) inputstage latch enable signal and 4) M/S line voltage (all probes 10x)

Figure 30: 1) Input stage M/S line driver base voltage, 2) output stage M/S line driver base voltage,3) M/S line voltage and 4) input stage voltage polarity (T1/T4 driving signal) (all probes 10x)

60

Figure 31: 1) MOSFETs 2&5-4&7 driving signal before the latch, 2) MOSFETs 2&5-4&7 drivingsignal after the latch, 3) output stage latch enable signal and 4) M/S line voltage (all probes 10x)

Figure 32: 1) MOSFETs 1&6 driving signal, 2) MOSFETs 2&5 driving signal, 3) MOSFETs 3&8driving signal and 4) MOSFETs 4&7 driving signal for positive rail voltage (all probes 10x)

61

Figure 33: 1) MOSFETs 1&6 driving signal, 2) MOSFETs 2&5 driving signal, 3) MOSFETs 3&8driving signal and 4) MOSFETs 4&7 driving signal for negative rail voltage (all probes 10x)

Figure 34: 1) MOSFETs 1&6 driving signal, 2) MOSFETs 2&5 driving signal, 3) MOSFETs 3&8driving signal and 4) MOSFETs 4&7 driving signal (all probes 10x)

62

Figure 35: 1) MOSFETs 1&6 driving signal, 2) MOSFETs 2&5 driving signal, 3) MOSFETs 3&8driving signal and 4) MOSFETs 4&7 driving signal (all probes 10x)

Figure 36: 1) Output of the PWM modulator (comparator AD790), 2) output stage M/S line driverbase voltage, 3) M/S line voltage and 4) MOSFETs 1&6 driving signal (all probes 10x)

63

8.2 Power amplifier section

Tests performed at this stage correspond to half the mains voltage Vin = 160 V.Figures 37 and 38 show the load voltage and the voltage out from the output stage (at

the output filter entrance) for a positive signal reference. It can be observed that despite thepositive reference, there is a small fraction of time when the output voltage is negative, whichoccurs always when the input stage makes a transition. Delays which are implemented to performa safe commutation of the bidirectional bridge and delays due to the inevitable pulse transformer+ tracks inductances are causing delayed transition of the output voltage to the desired value inexcess of 3 · 200 = 600 ns. Although this can be solved by careful trimming of the delaying RCcombinations and decreasing the delay time between transitions, this action was not performedherein.

Another interesting point to make is the ringing which is nicely depicted in figure 38. Aswe have mentioned earlier when performing switching loss calculation in the output stage, eachswitching transition of the input stage is causing charge displace among the parasitic capacitancesof the turned-off switches of the bidirectional bridge. Due to the increased number of the switches,their interconnections are growing in length, so that the corresponding track parasitic inductance isincreased as well. This unfortunately results in resonant ringing in the output stage voltage causedby input stage switching. The same phenomenon of ringing occurs when the output stage switchesto conform to the PWM modulator output. All these ringings result in additional performancedeterioration and decrease the efficiency.

Figure 39 is showing the load voltage, the voltage applied across the output stage anda reference signal, which is Vp−p = 2 V at f = 10 kHz. Due to the immense noise created bythe switching of both the input and the output stage, the measurement of the reference signal iscorrupted. The output voltage is following the signal reference, although the distortion is high.

8.3 Power amplifier section in closed-loop operation

Tests performed in this section are also corresponding to half of the final input voltage ofthe DC-bus Vin = 160 V, so the presented results apply to low power. Higher input voltages werefound problematic to reach with the present PCB layout.

The load voltage, the reference signal and the Fast Fourier Transform (FFT) of the loadvoltage, for output powers Pout = 0 W, 1 W and 10 W are given in figures 40, 41 and 42. It isobvious from the diagrams that the switching action of the prototype results in large quantitiesof noise injected in the closed loop, which disrupts the proper operation of the SICAM. Noise isobserved especially at the switching frequency of the output stage fs2 = 200 kHz, but also at theswitching frequency of the input stage fs1 = 100 kHz. PSRR is also compromised due to the lowoverall gain of the closed loop (KC1KC2 = 13.07), and this is observed as a harmonic with a highamplitude at frequencies near 0 Hz.

At the end, the measurement of efficiency for low output power levels and input voltage onthe DC-bus Vin = 160 V is given in table 23. The efficiency is steadily increasing, and it wouldn’tbe strange if it reaches the calculated levels or little bit less for the full output power.

9 Conclusion

The report proved that the idea of master/slave operation of the input and output stageis viable, and with a more careful converter design and commutation delay selection can operatesafely in a large range of input voltages and output powers. Therefore one can be sure that duringeach switching transition of the bidirectional bridge there is a path for the output filter + loadcurrent and no overvoltages are created due to its interruption.

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Figure 37: 1) Load voltage and 2) output stage voltage at output filter (all probes 50x)

Figure 38: 1) Load voltage and 2) output stage voltage at output filter (all probes 50x)

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Figure 39: 1) Load voltage, 2) output stage voltage at output filter and 3) reference signal (probes1 and 2 - 50x, 3 - 10x)

Figure 40: 1) Load voltage, 2) reference signal and M1) FFT (probe 1 - 50x, probe 2 - 10x)

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Figure 41: 1) Load voltage, 2) reference signal and M1) FFT (probe 1 - 50x, probe 2 - 10x)

Figure 42: 1) Load voltage, 2) reference signal and M1) FFT (probe 1 - 50x, probe 2 - 10x)

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Pout [W] η [%]

0 0.7

1 11.4

2 20

5 35

10 45

Table 23: Efficiency of the prototype

Operation of both the input and output stage are analyzed thoroughly. Even more, a powerloss analysis is performed using equations developed specifically for the topology concerned, whichis not found in the previous references (especially for the output stage).

Advantages and drawbacks of the design are clearly stated whenever a potential problemwas encountered or envisioned. Some of them, which were not mentioned previously will be addedhere, and some will be repeated for greater emphasis.

It goes beyond every possible discussion that the reduced power supply complexity of theSICAM should increase the converter efficiency, but in the same time cause an audio performancedeterioration due to the compromised PSRR. Although there are different linear and nonlinearcontrol techniques for fighting against the input voltage disturbances, significant improvement willbe very hard to reach. This will be left for analysis in near future and will be certainly one of theaims in the following reports.

The whole proposed topology shows strong resemblance with a compound SMPS and aClass D audio power amplifier. If we look at the input stage and the transformer as a simpleisolated SMPS, we may notice that the use of the large LC output filter of the complex SMPSis successfully avoided and there is no closed loop control implemented in the input stage. Thesecertainly represent a simplification not encountered before, but the SMPS rectifier diodes are actu-ally transferred in each of the legs of the bidirectional bridge in the output stage. Careful analysisshould be performed to determine to which extent economic savings are feasible. It was mentionedbefore that for lower output powers, full-bridges in the input and output stages are significant bur-den for the system complexity, efficiency and price, so these should be changed into half bridges.Another important side-effect of using too much power components is the increase of the para-sitic inductance in the tracks connecting the distributed components, resulting in unwanted delays,resonant ringing and increased losses.

The safe-commutation control algorithm using the master/slave principle is presented inthe report and is implemented in the prototype using discrete logic gates. This algorithm is rathercomplex and results in large number of gates needed. It is, however, feasible to implement theproposed control algorithm on a Programmable Logic Device (PLD) or even a microcontroller,which will eventually result in cost reduction, space savings and greater flexibility of the overallsystem.

The closed-loop control has been already seen in other Class D audio power amplifiers. So,there is nothing new about it and it took only a small fraction of time to design and implemented it,in comparison with the time spent on designing the power stage and the corresponding open-loopcontrol and safe-commutation circuitry. However, some other closed-loop control techniques maybe investigated in near future in conjunction with the same topology, provided they offer the sameor even better performance in terms of sensitivity reduction and frequency bandwidth.

Future research on DC-AC PWM SICAMs should orient towards topologies which use4QSWs made solely from MOSFETs: in terms of linearity and power losses this is the best solution.However, special care should be taken to avoid short-circuiting the transformer secondary and inthe same time providing a path for the output filter + load current or removing the stored magnetic

68

energy safely without causing any overvoltages. Another problem which should be alleviated is thegate delay when driving the 4QSWs from pulse transformers. One possible solution is moving thecontrol as close to the switches as possible, to avoid use of isolation barrier. However, in a complexsystem like SICAM, this is not always possible for both stages.

The experience gained during developing the master/slave PWM DC-AC SICAM prototypeand writing the report will prove invaluable for the research and investigation of topologies to follow.Most of the hands-on knowledge and theoretical investigations/formulae can be reused in similartopologies, which will speed up the process of prototype development. Knowing the possibilities ofthe real-world components, observed delays and desired switch and control structure, it is almostcertain that future prototypes will perform even better.

69

References

[1] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics - Converters, Applications,and Design. John Wiley and Sons, Inc., second ed., 1995.

[2] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics. Kluwer AcademicPublishers, 2001. Second edition.

[3] K. Nielsen, Audio power amplifier techniques with energy efficient power conversion. PhDthesis, Technical University of Denmark, Kgs. Lyngby, Denmark, April 1998.

[4] P. Ljusev, “Review of possible sicam topologies,” Tech. Rep. 01/02, DTU, December 2002.

[5] L. M. Fenger and H. Lynge, “Single converter stage amplifier,” Master’s thesis, TechnicalUniversity of Denmark, Kgs. Lyngby, Denmark, September 2001.

[6] K. Billings, Switchmode Power Supply Handbook. McGraw-Hill, 1999. Second edition.

[7] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics - Converters, Applications,and Design. John Wiley and Sons, Inc., third ed., 2003.

[8] R. Steigerwald, “A comparison of half-bridge resonant converter topologies,” Power Electron-ics, IEEE Transactions on, vol. 3, no. 2, pp. 174 –182, 1988.

[9] M. K. Kazimierczuk, W. Szaraniec, and S. Wang, “Analysis and design of parallel resonantconverter at high q−l/,” IEEE Transactions on Aerospace and Electronic Systems, vol. 28,no. 1, pp. 35–50, 1992.

[10] M. Kazimierczuk, N. Thirunarayan, and S. Wang, “Analysis of series-parallel resonant con-verter,” Aerospace and Electronic Systems, IEEE Transactions on, vol. 29, no. 1, pp. 88–99,1993.

[11] D. Czarkowski and M. Kazimierczuk, “Phase-controlled series-parallel resonant converter,”Power Electronics, IEEE Transactions on, vol. 8, no. 3, pp. 309–319, 1993.

[12] A. Bhat, “Analysis and design of a series-parallel resonant converter,” Power Electronics,IEEE Transactions on, vol. 8, no. 1, pp. 1–11, 1993.

[13] J.-H. Cheng and A. Witulski, “Analytic solutions for llcc parallel resonant converter simplifyuse of twoand three-element converters,” Power Electronics, IEEE Transactions on, vol. 13,no. 2, pp. 235–243, 1998.

[14] A. Bhat, “A resonant converter suitable for 650 v dc bus operation,” Power Electronics, IEEETransactions on, vol. 6, no. 4, pp. 739 –748, 1991.

[15] N. Pereira, B. Borges, and V. Anunciada, “Supra resonant fixed frequency full bridge dc-dcresonant converter with reduced switching losses,” Telecommunications Energy Conference,1996. INTELEC ’96., 18th International, pp. 833 –839, 1996.

[16] V. Durgesh, A. Muthuramalingam, and V. Sastry, “Operation of fixed frequency class-d series-parallel resonant converter on utility line with active control,” Applied Power ElectronicsConference and Exposition, 1999. APEC ’99. Fourteenth Annual, vol. 1, pp. 375–381 vol.1,1999.

[17] V. Belaguli and A. Bhat, “Operation of the lcc-type parallel resonant converter as a lowharmonic rectifier,” Industrial Electronics, IEEE Transactions on, vol. 46, no. 2, pp. 288–299,1999.

70

[18] S. Nagai, E. Hiraki, Y. Arai, and M. Nakaoka, “New phase-shifted soft-switching pwm seriesresonant inverter topologies and their practical evaluations,” Power Electronics and DriveSystems, 1997. Proceedings., 1997 International Conference on, vol. 1, pp. 318 –322 vol.1,1997.

[19] B. Andreycak, “Designing a phase shifted zero voltage transition power converter,” PowerSupply Design Seminar Handbook, no. Unitrode SEM-900, pp. 3.1–3.15, 1993.

[20] D. J. Hamo, “A 50w, 500khz, full-bridge, phase-shift, zvs isolated dc to dc converter using thehip4081a,” tech. rep., Intersil, April 1995. Application note AN-9506.

[21] M. K. Nalbant, “Phase modulated pwm topology with the ml4818,” tech. rep., Fairchild Semi-conductor, June 1996. Application note AN-42026.

[22] J. Cho, J. Sabate, G. Hua, and F. Lee, “Zero-voltage and zero-current-switching full bridgepwm converter for high power applications,” Power Electronics Specialists Conference, PESC’94 Record., 25th Annual IEEE, pp. 102–108 vol.1, 1994.

[23] N. Burany, “Safe control of four-quadrant switches,” Conference Record of the IEEE IndustryApplications Society Annual Meeting (Cat. No.89CH2792-0), pp. 1190–4 vol.1, 1989.

[24] M. Empringham, P. Wheeler, and D. Clare, “Intelligent commutation of matrix converterbi-directional switch cells using novel gate drive techniques,” PESC 98 Record. 29th AnnualIEEE Power Electronics Specialists Conference (Cat. No.98CH36196), pp. 707–13 vol.1, 1998.

[25] M. Ziegler and W. Hofmann, “Performance of a two steps commutated matrix converter forac-variable-speed drives,” 8th European Conference on Power Electronics and Applications.EPE’99, p. 10 pp., 1999.

[26] J. Mahlein, J. Weigold, and O. Simon, “New concepts for matrix converter design,” Indus-trial Electronics Society, 2001. IECON ’01. The 27th Annual Conference of the IEEE, vol. 2,pp. 1044–1048 vol.2, 2001.

[27] J. Lloyd H. Dixon, “Eddy current losses in transformer windings and circuit wiring,” Unitrodemagnetics design handbook, pp. R2.1–R2.10, 2001.

[28] B. C. Baker, “Anti-aliasing, analog filters for data acquisition systems,” tech. rep., MicrochipTechnology Inc, 1999.

[29] “Iron powder cores for power conversion and line filter applications,” tech. rep., Micrometals,June 2003. Issue K.

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