Introduction to Micro/Nano Electronics
Transcript of Introduction to Micro/Nano Electronics
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Introduction to Micro/Nano Electronics
David B. Janes
School of Electrical and Computer Engineering,
Birck Nanotechnology Center and Institute for Nanoelectronics and Computing
Purdue University, W. Lafayette, IN 47907
INAC
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A Brief Overview of Microelectronics
Semiconductor Band Diagrams
Basic Semiconductor Devices
Introduction to Circuits
Toward Nanoelectronics
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Enabling Technology: Microfabrication
Driving Technology:
Integrated Circuits
(microchips)
Photos from: Newcastle University Computing Service, IBM Archives, Dell/Palm/Motorola
1969: IBM System 360
1981: IBM PC
2005: Mobile, Wireless
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Silicon Boule and Processed Wafers
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Whats a Nanometer?Dimension
0.1nm
1 nm
10 nm
100 nm
1 m
100 m
10 m
1 mm
1 cm
10 cm
1 mHuman
Mouse
Fly
Gnat
(10-9 m)
1000 X
1000 X
1000 X
Bacteria
70 km (45 miles)
5 billion humans
(close-packed)
2 m tall, each
gets 1m x 1m
0.07 mm (0.003)
5 billion nanos
(close-packed)
2 nm tall, each
gets 1nm x 1nm
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Microns to Nanometers
Dimension
0.1nm
1 nm
10 nm
100 nm
1 m
100 m
10 m
Simple
Molecules
Atoms
Bacteria
Plant,
Animal Cell
Virus
Protein
DNA base
DNA turn
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Nanotechnology:
A Convergence of Enabling Technologies
Dimension (nm)
0.1nm
1 nm
10 nm
100 nm
1 m
100 m
10 m
Simple Molecules
Atoms
Gate Length in CMOS
Device Dimension in CMOSBiological Cell
Microelectronics
Oxide Thickness in CMOS
Chemical/Biological
Synthesis
Nanoclusters
Imaging/Manipulationof Structures
Scanning ProbesElectron Microscopy
Optical Microscopy
y)(x,VS
Voltage Control
Top-Down
Bottom-Up
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A Brief Overview of Microelectronics
Semiconductor Band Diagrams
Basic Semiconductor Devices
Introduction to Circuits
Toward Nanoelectronics
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E
MoleculeSemiconductor
Eg ~ 0.2 - 2.5 eV
EV
EC
E
Eg ~ 4 - 6 eV
HOMO
LUMO
EF
EF
Semiconductor and Molecular States
EVAC EVAC
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Semiconductor
EV
EC
EG
N atoms/cm3
Total number of bonding electrons in crystal = 4N(~ 1e23/cm3)
Valence Band: Mostly
filled with electrons
Count empty states
(holes)
Density of holes: p
Charge/hole: +q
Conduction Band:
Mostly empty of
electrons
Count electrons
Density of electrons: n
Charge/electron: -q
4N States
4N States
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E
N-type Semiconductor
Eg ~ 0.2 - 2.5 eV
EV
ECEF
Semiconductor Bands Doping Dependence
EVAC
E
Eg ~ 0.2 - 2.5 eV
EV
EC
EF
EVAC
P-type Semiconductor
Fermi Level position can be changed by addition of dopants
(donors and acceptors)
States are extended states electrons and holes can move freely
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N-type Semiconductor
EV
ECEF
Semiconductor Bands Doping Dependence
EVAC
EV
EC
EF
EVAC
P-type Semiconductor
Fermi Level position can be changed by addition of dopants
(donors and acceptors)
States are extended states electrons and holes can move freely
EC
Donor Levels
e- in C.B.
EV
Acceptor Levels
h+ in V.B.
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Energy Bands for Metals and Semiconductors
N-type
Semiconductor
EV
ECEF
EVAC
Recall: Electrostatic Potential: qV = - EVAC
E qM
EF
Metal
EVAC
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Molecule
E
Eg ~ 4 - 6 eV
HOMO
LUMO
EF
Molecule
E
Eg ~ 4 - 6 eV
HOMO
LUMO
EF
Oxidation: give up an electron
(M0 => M+ + 1e- )
Redox Processes in a Molecule
Reduction: accept an electron
(M0 + e- => M- )
e-
e-
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Conduction Process in a Semiconductor Device
Drift motion in an electric
field
EV
EC
EF
EVAC
JN Drift
EV
ECEF
EVAC
Diffusion motion due to
concentration gradient
JN Diff
Contact Contact
-q VAppl
electrons electrons
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A Brief Overview of Microelectronics
Semiconductor Band Diagrams
Basic Semiconductor Devices
Introduction to Circuits
Toward Nanoelectronics
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EC
EV
EG
EF
P-Type Semiconductor
p ~ NA
EC
EV
EG
EF
N-Type Semiconductor
n ~ ND
EC
EV
EG
EF
nn ~ ND
EC
EV
EG
EF
pn Junction
pp ~ NA qVbi
PN Junctions
EE455 Spring 2000 Lecture 2
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EC
EV
EG
EF
nn
~ ND
EC
EV
EG
EF
pn Junction
pp ~ NA qVbi
PN Junction Electrostatics
W (depletion width)
+ + + +
+ + + ++ + + +
- - - -
- - - -- - - -
= -q NA = +q ND
EE455 Spring 2000 Lecture 2
Electric Field
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EC
EV
EGEF
nn ~ ND
EC
EV
EG
EF
pp ~ NA
PN Junction Reverse Bias
W (depletion width)
EC
EV
EG
EF
nn ~ ND
EC
EV
EG
EF
pp ~ NA q(Vbi - VD)
PN Junction
Forward Bias
W (depletion width)
q(Vbi - VD)+
-
VD < 0
+
-
VD > 0
EE455 Spring 2000 Lecture 2
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Diode Current
ID = IS (eq VD/ nkT -1)
q = electronic charge (1.6 x 10-19 C)
n == ideality factor
k = Boltzmanns constant = 8.62e-5 eV/KT = temperature (K)
kT/q = 0.026 eV at room temperature
Reverse Junction Capacitance (Cj)
Cj = Si A/Wdepl
Si = Ksi 0 = 11.8 x 8.854 x 10-14 f/cm
Wdepl = (2 Si (Vbi - VD)/q (1/NA +1/ND) )1/2
Vbi = built-in potential = kT/q ln(NA ND/ni2)
EE455 Spring 2000 Lecture 2
ID
VD
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The basic building block of microelectronics:
The transistor switch
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An Idealized Switch
Controlled by
Gate Voltage
Ideal: Open Circuit (I=0)
when open
Also need gain.
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An Idealized Switch
Controlled by
Gate Voltage
Ideal: Open Circuit (I=0)
when open
A controlled
current sourceVGATE
Ideal: Open Circuit (I=0) when Vgate
< Threshold Voltage
When on: current increases with
gate voltage
Gain: small input level induces large
output response
MOSFET: small input current, large
output current (comparable voltages)
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MOS Transistor
NMOS Structure
p- substraten++ n++
Source Drain
VS (= 0) VD (> 0)Gate
Gate Oxide
VG (> 0 in Active)
D
S
G
ID
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NMOS Transistor -- Small VDS
Accumulation
p- substraten++ n++
Source Drain
VS (= 0) VD (> 0)Gate
Gate Oxide
VG ( 0)
Gate
Gate Oxide
VG ( > VT )
- - - - - - - - - - - - - - - - - - - -
VDS
ID
VDS
ID
EE 455 Spring 2000 Lecture 3
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NMOS Transistor -- VDS comparable to (VGS - VT)
p- substraten++ n++
Source Drain
VS (= 0)
VD = (VGS - VT)
Gate
Gate Oxide
VG ( > VT )
- - - - - - - - - - - - - - - -
p- substraten++ n++
Source Drain
VS (= 0) Gate
Gate Oxide
VG ( > VT )
- - - - - - - - - - - - - - - - - - -
0 < VD < (VGS - VT)
VDS
ID
VDS
ID
EE 455 Spring 2000 Lecture 3
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MOS Transistor I-V Characteristics
ID = n Cox/2 W/L (VGS - VTN)2
ID = n CoxW/L [(VGS - VTN)VDS -VDS2 /2 ]
Active Region
Triode
Region
VDS
ID
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MOS Transistor -- Subthreshold Region
ID = ID0W/L exp(q VGS /n k T)
n = (COX + Cdepl) / COX 1.5
Subthreshold Region: (VGS - VTN) < 0 V
VGS
log ID
VT
Ideal: ~ 60
mV/decade
log ION
log IOFF
Need high ON/OFF ratio (~ 1 e6)
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MOS Transistor -- Short Channel Effects
EE 455 Spring 2000 Lecture 7
Velocity Saturation:
Hot Carrier Effects:
Impact Ionization, Tunneling into Gate Oxide, Punch-Through
from Source to Drain:
Drain-Induced Barrier Lowering (DIBL):
p- substraten++ n++
Source Drain
VS (= 0)Gate
Gate Oxide
VG ( > VT )
- - - - - - - - - - - - - - - -
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CMOS = NMOS + PMOS
NMOS Structure
p- substraten++ n++
Source Drain
VS (= 0) VD (> 0)Gate
Gate Oxide
PMOS Structure
n- substratep++ p++
Source Drain
VS (= 0) VD (< 0)
VG (< 0 in Active)
Gate
Gate Oxide
VG (> 0 in Active)
D
S
G
D
S
G
ID
ID
on at positive gate voltages
on at negative gate voltages
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MOS Transistor -- Subthreshold Region -
- PMOS
ID = ID0W/L exp(q VGS /n k T)
n = (COX + Cdepl) / COX 1.5
Subthreshold Region: (VGS - VTN) < 0 V
VGS
log ID
VT
Ideal: ~ 60
mV/decade
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p- substrate
n++ n++
S D
VS (= 0) G
Gate Oxide
VG ( > VT )
- - - - - - - - -
Device Relevance of Metal-Semiconductor
Interfaces
1. Ohmic Contacts
Example: S/D contacts in MOSFET:
Good contacts: specific contact
resistance < 1x10-7 cm2
Low barrier height, heavy
doping (tunneling or thermionic
field emission).
Also relevant to most other semiconductor devices,
including optoelectronic devices.
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n- channel
n++ n++
S D
VS (= 0) GVG ( > VT )
Device Relevance of Metal-Semiconductor
Interfaces
Gate in metal-semiconductor FET
(MESFET):
Good Schottky barrier for gate
Gate modulates depletion
width, open channel region
Moderate barrier height,
moderate doping (small gate
current).
2. Schottky Barriers
Example: gate region in MESFET:
Also relevant to Schottky diodes (used as high
frequency rectifiers).
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A Brief Overview of Microelectronics
Semiconductor Band Diagrams
Basic Semiconductor Devices
Introduction to Circuits
Toward Nanoelectronics
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Silicon Wafer after Processing
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D
S
G VOUT
VDD
VIN
D
S
A Simple CMOS Circuit (Inverter)
VIN
VOUT
PMOS
NMOS
NMOS on,
PMOS off
PMOS on,
NMOS off
I ~ IOFF
I ~ IOFF
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Typical Cascade of Stages
First Stage drives 2nd Stage (and so on)
Each stage must be able to drive a replica of itself
(or larger gate)
D
S
G VOUT
VDD
VIN
D
S
PMOS
NMOS
D
S
G VOUT
VDD
D
S
PMOS
NMOS
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Operating Speed and Power Dissipation
D
S
G VOUT
VDD
VIN
D
S
PMOS
NMOS
During switching transient from high to low:
Transition speed ~ ION this sets operating
frequency
Dissipate power during switching
(dynamic)
NMOS IONCG2
D
S
G VOUT
VDD
D
S
PMOS
NMOS
Therefore, want large ION for
high operating frequency
(example: 3 GHz Pentium IV)
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Static Power Dissipation
D
S
G VOUT
VDD
VIN
D
S
PMOS
NMOS
During times when circuit is not switching:
Have leakage current IOFF
power dissipation ~ IOFF VDD
This is static power, and is wasted
NMOS IOFF
VDD
Therefore, want small IOFF for low power
dissipation
Need very small power/device, since have
~ 100 million devices/chip
(example: ~100 Watts in Pentium IV)
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D
S
G VOUT
VDD
A
D
S
A Basic CMOS Logic Gate (AND)
VIN
VOUT
PMOS
NMOS
Both A and B
high
A or B low
D
S
G
D
S
AB
B
I ~ IOFF
I ~ IOFF
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A Basic CMOS Memory Cell (DRAM)
D S
G
Storage
Capacitor
Enable Line
High 1
or Low 0
Voltage
A single bit (0 or 1) stored as
electronic charge on capacitor
Transistor acts as switch
charges switch if enabled (gate)and a high voltage applied to D
Readout is by sensing whether
capacitor is charged (generally
by trying to write another bit, andmonitoring the current)
Volatile charge eventually leaks
out and must be refreshed
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A Basic CMOS Memory Cell (DRAM)
D S
G
CSTORE
Word Line
Bit Line
Large memory arrays (Gigabits) arranged in word and bit-line arrays
D S
G
CSTORE
D S
G
CSTORE
D S
G
CSTORE
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Ideal Metal - Semiconductor Junction
Ideal M-S Junction: qB = qM - - (EC -EF)BULK
M-S Structure (Schottky)
N-Type
Semiconductor
EF
EC
Depth
Ener
gy
Metal
qB
EVAC
Bulk
Depletion Region
(~ 5 - 1000 nm)
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A Brief Overview of Microelectronics
Semiconductor Band Diagrams
Basic Semiconductor Devices
Introduction to Circuits
Toward Nanoelectronics
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Chiseling: Use lithography, etching,etc. to define devices, interconnects
Yields well optimized device
structures, nearly arbitrary interconnect
configurations
Si Substrate
PMOS deviceNMOS device
Lithography, etching, implant
Cross-Sectional View:
Microelectronic Device/Interconnect
StructuresTop View:
6-Transistor SRAM Cell
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Trends in Miniaturization of ICsMoores Law
#ofT
ransistors/
DRAM
Chip
4Kb64Kb
1Mb
16Mb
DRA
M
256Mb
10
100
1000
10000
1970 1980 1990 2000 2010 20201.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
1.E+111.E+12
Year
Minim
umFeature(nm
)
#o
fTransistors/DR
AMChip
MinimumDimension(nm)
# of Neurons in the
Human Brain
in 15cm3
2-3 years pergeneration
Time
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silicide
Strained Si
Intel: August 2002
www.intel.com/research/silicon/90nm_press_briefing-technical.htm
1.2nmSiO2
1970 1980 1990 2000 2010 2020
0.1
10
1
0.01
Conventional Micro to Nano- electronics
Interconnect
LinesPitch
Technology Node: pitch/2
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Reed, Yale
Purdue,Northwestern
Hersam, Northwestern
Dai, Stanford and McEuen, Cornell
LVoltage
Voltage
Nanoelectronics
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Cost of Fabrication Facility for ICsMoores 2nd Law
2001:
$ 5billion
$100 M
$1 B
$ 10 B
$100 B
1970 1980 1990 2000 2010 2020
Year
Cos
tofFabFacility
($)
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Fundamental Limits of Microelectronics
Quantum mechanics Speed of light Material limitations atomic scale manufacturing
Cost of a Silicon Fab:1967: $ 2M1997: $ 3B2010: $10B
From M. Lundstrom
100nm
IndividualAtoms
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Acknowledgements
Funding: NASA, NSF, ARO for funding
Thank you to Prof. Jerry Woodall, Dr. Saurabh
Lodha, Dr. Steven Howell and Prof. Supriyo
Datta for helpful discussions
INACThe NASA Institute for Nanoelectronics and Computing
INACThe NASA Institute for Nanoelectronics and Computing