Introduction - eee.hku.hkelec3441/sp19/handout/L01-intro-4up.pdf · 2019/1/17 1 Computer...
Transcript of Introduction - eee.hku.hkelec3441/sp19/handout/L01-intro-4up.pdf · 2019/1/17 1 Computer...
2019/1/17
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Computer ArchitectureELEC3441
2nd Semester, 2018-19Dr. Hayden Kwok-Hay So
Department of Electrical and Electronic Engineering
Introduction
What is Computer Architecture?
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Computer Architecture
Meltdown & Spectre
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Meltdown & Spectre
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This is a very intricate attack but the root cause is unflushed speculative state from the cache resulting in a timing variations.
Meltdown breaks the most fundamental isolation between user applications and the operating system.
Spectre breaks the isolation between different applications.
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What is Computer Architecture?
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Computer architecture is the studyof the design and implementation of
computing systems.
Design constraints
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PerformanceFunction
PowerCost
Compatibility
Compatibility
Cost of software development makes compatibility a major force in market
Architecture continually changing
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Applications
Technology
Applications suggest how to improve technology, provide revenue to fund development
Improved technologies make new applications possible
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Machine Learning è Architecture
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Computer in the 60s
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DEC’s PDP-10Src: http://www.computerhistory.org
Today’s Computer
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1
5
913
1824
51
80
117183
280
481649
9931,267
1,7793,016
4,1956,043 6,681
7,10811,865
14,38719,484
21,87124,129
1
10
100
1000
10,000
100,000
1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012
Per
form
ance
(vs
. VA
X-1
1/78
0)
25%/year
52%/year
22%/year
IBM POWERstation 100, 150 MHz
Digital Alphastation 4/266, 266 MHz
Digital Alphastation 5/300, 300 MHz
Digital Alphastation 5/500, 500 MHz AlphaServer 4000 5/600, 600 MHz 21164
Digital AlphaServer 8400 6/575, 575 MHz 21264Professional Workstation XP1000, 667 MHz 21264AIntel VC820 motherboard, 1.0 GHz Pentium III processor
IBM Power4, 1.3 GHz
Intel Xeon EE 3.2 GHz AMD Athlon, 2.6 GHz
Intel Core 2 Extreme 2 cores, 2.9 GHz Intel Core Duo Extreme 2 cores, 3.0 GHz
Intel Core i7 Extreme 4 cores 3.2 GHz (boost to 3.5 GHz) Intel Xeon 4 cores, 3.3 GHz (boost to 3.6 GHz)
Intel Xeon 6 cores, 3.3 GHz (boost to 3.6 GHz)
Intel D850EMVR motherboard (3.06 GHz, Pentium 4 processor with Hyper-Threading Technology)
1.5, VAX-11/785
AMD Athlon 64, 2.8 GHz
Digital 3000 AXP/500, 150 MHzHP 9000/750, 66 MHz
IBM RS6000/540, 30 MHzMIPS M2000, 25 MHz
MIPS M/120, 16.7 MHz
Sun-4/260, 16.7 MHz
VAX 8700, 22 MHz
AX-11/780, 5 MHz
Uniprocessor Performance
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Limited by Power, ILP, Memory speed
Multi-Core CPU
Intel Lynnfield processor(source: AnandTech)
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Warehouse Scale Computern A new class of computer for
massively parallel cluster of computers
n Datacenter as a computer• ~100,000 servers• include design choices in
electrical, electronic and building construction
n Exploit service level parallelism
n Designed for cloud-based services
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The End of the Uniprocessor Era
Single biggest change in the history of computing systems
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ELEC3441 Course Objectivesn To make a simple processor
• Construct a workable processor
n To make a uniprocessor runs fast• Various techniques developed through the 1990s
n To appreciate latest development in computer architecture research• Techniques to overcome Power Wall, ILP Wall,
Memory Wall
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A Quest into HW + SWn Computer architecture study requires deep
understanding of both hardware and softwaren Software:
• Assume you know basic C/C++/Java• Assume you know basic compilation flow• Will learn assembly languages in
homework/project/tutorial
• Linux programming
n Hardware:• You need to know basic digital system design concept
(will cover briefly in class)
• Good to take ELEC2302/3342 concurrently
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ELEC3441 Administrivia
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Dr. Hayden SoInstructors
TA Maolin Wang
Lectures
http://www.eee.hku.hk/~elec3441
Mo 12:30-2:20pmTh 12:30-1:20pm MB141
Tutorials No scheduled time. But will arrange additional office hours for homework
Web
Textbookn Reading materials will be drawn from two main
textbooks:• Mostly from COD, with later modules from CAQ
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“Computer Organization and Design: The Hardware/Software Interface”David Patterson, John Hennessy5th Edition; Morgan Kaufmann (2013)ISBN-13: 978-0124077263 COD
“Computer Architecture: A Quantitative Approach”John Hennessy, David Patterson 5th Edition; Morgan Kaufmann (2011)ISBN-13: 978-0123838728 CAQ
AssessmentsHomework 45% • 3 homework assignments
• mini-project• Include hands on with
building real processorsQuiz 15% • 3 in-class quizzes
• A way to make sure you follow class progress
Exam 40% Cumulative of entire semester
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Agenda for this semestern The Basics
• Single cycle processor
n Improving CPI• Memory Hierarchy• Simple Pipelining
n Breaking the CPI=1 barrier• Out-of-order execution• Super-scalar processor
n Advanced Architectures• Multi-core processors• Vector processors• VLIW
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THE BASICSModule 1
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Computer Architecture: HW/SW Interface
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Applications
Operating System
Assembler
Compiler
Microarchitecture
Digital Design
Circuit Design
Transistors
Instruction Set Architecture
Sof
twar
eH
ardw
are
Processor Memory I/O
Instruction Set Architecture (ISA)n The contract between software and hardwaren Typically described by giving all the programmer-
visible state (registers + memory) plus the semantics of the instructions that operate on that state
n IBM 360 was first line of machines to separate ISA from implementation (aka. microarchitecture)
n Many implementations possible for a given ISA• E.g., the Soviets build code-compatible clones of the
IBM360, as did Amdahl after he left IBM.• E.g.2., today you can buy AMD or Intel processors that run
the x86-64 ISA.• E.g.3: many cellphones use the ARM ISA with
implementations from many different companies including TI, Qualcomm, Samsung, Marvell, etc.
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ISA to Microarchitecture MappingnISA often designed with particular
microarchitectural style in mind, e.g.,– Accumulator Þ hardwired, unpipelined– CISC Þ microcoded– RISC Þ hardwired, pipelined– VLIW Þ fixed-latency in-order parallel pipelines– JVM Þ software interpretation
nBut can be implemented with any microarchitectural style
– Intel Ivy Bridge: hardwired pipelined CISC (x86) machine (with some microcode support)
– Simics: Software-interpreted SPARC RISC machine
– ARM Jazelle: A hardware JVM processor
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Notable ISAs
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Alpha 1992 DEC; in 21264 processors, etc
MIPS 1986 research/MIPSPA-RISC 1986 HP; HP Workstations in the 90s
PowerPC 1993 IBM/MotorolaSPARC 1987 Sun MicrosystemARM 1985 ARM
x86 1978 IntelVAX 1977 DEC
IBM360 1964 IBM; “defined” computer architecture
DominateToday
Too complex for undergrad teaching…See Appendix K of H&P for a
survey of major ISAs
This Course: RISC-V ISAn RISC-V is a new simple, clean, extensible
ISA that was originally developed at Berkeley
for education and research
• RISC-I/II, first Berkeley RISC implementations
• Berkeley research machines SOAR/SPUR
considered RISC-III/IV
n Both of the dominant ISAs (x86 and ARM) are
too complex to use for teaching
n RISC-V ISA manual available on web page
n Full GCC-based tool chain available
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Electronic Numerical Integrator and Computer (ENIAC)n Inspired by Atanasoff and Berry, Eckert and Mauchly designed
and built ENIAC (1943-45) at the University of Pennsylvanian The first, completely electronic, operational, general-purpose
analytical calculator!• 30 tons, 72 square meters, 200KW
n Performance• Read in 120 cards per minute• Addition took 200 µs, Division 6 ms• 1000 times faster than Mark I
n Not very reliable!
Application: Ballistic calculations
angle = f (location, tail wind, cross wind, air density, temperature, weight of shell,propellant charge, ... )
WW-2 Effort
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Electronic Discrete Variable Automatic Computer (EDVAC)
n ENIAC’s programming system was external• Sequences of instructions were executed independently of the
results of the calculation• Human intervention required to take instructions “out of order”
n Eckert, Mauchly, John von Neumann and others designed EDVAC (1944) to solve this problem• Solution was the stored program computer
Þ “program can be manipulated as data”
n First Draft of a report on EDVAC was published in 1945, but just had von Neumann’s signature!• In 1973 the court of Minneapolis attributed the honor of inventing
the computer to John Atanasoff
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Stored-Program Computer
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Get the current
instruction
Execute the instruction
Determinesthe next
instruction to fetch
Program = A sequence of instructions
Ex: Calculating Class Grades*grade = 0.1 ´ lab + 0.2 ´ mt
+0.3 ´ hw + 0.4 ´ proj;
grade = 0;tmp = 0.1 ´ lab;grade = grade + tmp;tmp = 0.2 ´ mt;grade = grade + tmp;tmp = 0.3 ´ hw;grade = grade + tmp;tmp = 0.4 ´ proj;grade = grade + tmp;
Time
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And in conclusion…n The study of computer architecture allows us
to construct better computer systems• Performance, power
n Computer architecture is a study that crosses software and hardware
n We will use RISC-V as main ISA for class work, but design principles applicable to other computer designs
n Stored programmed computer will be the basic computing model studied
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Acknowledgementsn These slides contain material developed and
copyright by:• Arvind (MIT)• Krste Asanovic (MIT/UCB)• Joel Emer (Intel/MIT)• James Hoe (CMU)• John Kubiatowicz (UCB)• David Patterson (UCB)
n MIT material derived from course 6.823n UCB material derived from course CS152,
CS252
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